JPH0727901B2 - Multilayer wiring formation method - Google Patents
Multilayer wiring formation methodInfo
- Publication number
- JPH0727901B2 JPH0727901B2 JP6862486A JP6862486A JPH0727901B2 JP H0727901 B2 JPH0727901 B2 JP H0727901B2 JP 6862486 A JP6862486 A JP 6862486A JP 6862486 A JP6862486 A JP 6862486A JP H0727901 B2 JPH0727901 B2 JP H0727901B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- insulating film
- opening
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は、半導体集積回路装置における多層配線の形
成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring in a semiconductor integrated circuit device.
（従来の技術） 半導体集積回路装置（IC）において、多層配線は、従
来、第２図に示すようにして形成されている。すなわ
ち、まず、IC基板１上に絶縁膜２（例えばSiO2またはPS
G）を形成した後、該絶縁膜２上に第１配線層のAl−Si
系合金膜３を形成する。その後、該合金膜３上に層間絶
縁膜４（例えばPSG）を形成した後、この層間絶縁膜４
はホトリソ・エツチングによつて開孔部５を選択的に形
成する。その後、前記開孔部５を通して前記Al−Si系合
金膜３（第１配線層）に接続される第２配線層としての
Al−Si系合金膜６を前記層間絶縁膜４上に形成する。(Prior Art) In a semiconductor integrated circuit device (IC), a multilayer wiring is conventionally formed as shown in FIG. That is, first, the insulating film 2 (for example, SiO 2 or PS) is formed on the IC substrate 1.
After forming G), Al-Si of the first wiring layer is formed on the insulating film 2.
The system alloy film 3 is formed. Then, after forming an interlayer insulating film 4 (for example, PSG) on the alloy film 3, the interlayer insulating film 4 is formed.
Selectively form the opening 5 by photolithography etching. Then, as a second wiring layer connected to the Al—Si alloy film 3 (first wiring layer) through the opening 5.
An Al—Si alloy film 6 is formed on the interlayer insulating film 4.
しかしながら、このような方法では、開孔部５のアスペ
クト比が大きくなるに従つて開孔部５の段差において第
２配線層（Al−Si系合金膜６）のステツプカバレージが
悪くなり、くびれ７を生じ、断線を起しやすくなるとい
う欠点があつた。However, in such a method, as the aspect ratio of the opening 5 becomes larger, the step coverage of the second wiring layer (Al—Si alloy film 6) becomes worse at the step of the opening 5, and the constriction 7 is formed. However, there is a drawback that it is easy to cause disconnection.
そこで、第２配線層形成直前の表面形状を平坦化する様
々な方法が提案されており、その一つとして、無電解め
つき法を用いて層間絶縁膜の開孔部を金属で埋める方法
がある。この方法を第３図により説明する。第３図
（ａ）に示すように、IC基板１上に絶縁膜２、第１配線
層としてのAl−Si系合金膜３、層間絶縁膜４を形成し、
この層間絶縁膜４に開孔部５を形成した後、該開孔部５
内に無電解めつきを行う前処理として、開孔部５内の第
１配線層（Al−Si系合金膜３）表面に活性化層11を形成
する。この活性化層11は、弱酸性塩化パラジウム（PdCl
2）溶液に室温で一分間浸す方法、もしくは、Pdの真空
蒸着を行つた後、開孔部５を形成した際のレジストを利
用して不要部のPdをリフトオフする方法などにより形成
される。そして、このようにして前処理を行つた後に、
無電解めつき液に浸すことにより、第３図（ｂ）に示す
ように、開孔部５に選択的にニツケル系めつき層12を層
間絶縁膜４と段差が生じない厚さに形成する。その後、
そのニツケル系めつき層12を介して第１配線層としての
Al−Si系合金膜３に接続される第２配線層としてのAl−
Si系合金膜を形成する。Therefore, various methods of flattening the surface shape immediately before the formation of the second wiring layer have been proposed, and one of them is a method of filling the openings of the interlayer insulating film with a metal by using an electroless plating method. is there. This method will be described with reference to FIG. As shown in FIG. 3A, an insulating film 2, an Al—Si alloy film 3 as a first wiring layer, and an interlayer insulating film 4 are formed on the IC substrate 1,
After forming the opening 5 in the interlayer insulating film 4, the opening 5 is formed.
As a pretreatment for electroless plating, the activation layer 11 is formed on the surface of the first wiring layer (Al—Si alloy film 3) in the opening 5. The activation layer 11 is made of weakly acidic palladium chloride (PdCl
2 ) It is formed by a method of immersing it in a solution at room temperature for 1 minute, or by performing vacuum deposition of Pd and then lifting off unnecessary portions of Pd using the resist used for forming the opening 5. And after performing the preprocessing in this way,
By immersing in the electroless plating solution, the nickel plating layer 12 is selectively formed in the opening 5 to a thickness that does not cause a step with the interlayer insulating film 4, as shown in FIG. 3 (b). . afterwards,
Through the nickel-based plating layer 12 as the first wiring layer
Al-as the second wiring layer connected to the Al-Si alloy film 3
A Si-based alloy film is formed.
（発明が解決しようとする問題点） しかしながら、この第３図の方法を、無電解めつき液と
して市販されているニポジツト468（シプレー社）を使
用して本発明者が実験を行つたところ、めつきのつきま
わり性が悪いため、開孔部５へのめつき層12の埋め込み
の歩留りが悪く、技術的に満足できるものは得られなか
つた。(Problems to be Solved by the Invention) However, when the present inventor conducted an experiment on the method of FIG. 3 by using Nipositot 468 (Chipley Co., Ltd.), which is commercially available as an electroless plating solution, Since the throwing power of the plating is poor, the yield of embedding the plating layer 12 in the openings 5 is poor, and no technically satisfactory product was obtained.
この発明は上記の点に鑑みなされたもので、その目的
は、層間絶縁膜の開孔部にめつき層を歩留り良く埋め込
むことができる多層配線の形成方法を提供することにあ
る。The present invention has been made in view of the above points, and an object thereof is to provide a method for forming a multi-layered wiring in which an plating layer can be embedded in an opening of an interlayer insulating film with high yield.
（問題点を解決するための手段） この発明では、層間絶縁膜開孔部の第１配線層上にパラ
ジウム活性化層を形成した後、金属供給源としてニツケ
ル塩，還元剤にジメチルアミンボラン，錯化剤にマロン
酸またはアスパラギン酸,pH調整剤としてアンモニアを
用いた無電解めつき液により前記層間絶縁膜開孔部にニ
ツケル系めつき層を形成する。(Means for Solving the Problems) In the present invention, after a palladium activation layer is formed on the first wiring layer in the opening of the interlayer insulating film, nickel salt is used as a metal source, dimethylamine borane is used as a reducing agent, A nickel plating layer is formed in the opening portion of the interlayer insulating film by an electroless plating solution using malonic acid or aspartic acid as a complexing agent and ammonia as a pH adjusting agent.
（作用） パラジウム活性化層を形成した後、前記無電解めつき液
により無電解めつきを施すと、めつきのつきまわりが良
く、確実に層間絶縁膜開孔部をめつき層で歩留りよく埋
めることができる。(Function) When a palladium activation layer is formed and then electroless plating is performed with the electroless plating solution, the plating coverage is good and the inter-layer insulating film openings are reliably filled with the plating layer with good yield. be able to.
（実施例） 以下この発明の一実施例を第１図を参照して説明する。(Embodiment) An embodiment of the present invention will be described below with reference to FIG.
まず、第１図（ａ）に示すように、IC基板21上に絶縁膜
22（例えばSiO2またはPSG）を6000Å厚に形成した後、
その絶縁膜22上に第１配線層としてのAl−Si系合金膜23
（6000Å厚）を形成する。First, as shown in FIG. 1A, an insulating film is formed on the IC substrate 21.
After forming 22 (eg SiO 2 or PSG) to a thickness of 6000Å,
An Al--Si alloy film 23 as a first wiring layer is formed on the insulating film 22.
Form (6000 Å thickness).
次に、第１図（ｂ）に示すように層間絶縁膜24（例えば
PSG）を6000Å厚に前記Al−Si系合金膜23上に形成した
後、この層間絶縁膜24に前記Al−Si系合金膜23に通じる
開孔部25をホトリソ・エツチングによつて選択的に形成
する。Next, as shown in FIG. 1B, the interlayer insulating film 24 (for example,
PSG) is formed on the Al-Si alloy film 23 to a thickness of 6000 Å, and then the opening 25 communicating with the Al-Si alloy film 23 is selectively formed in the interlayer insulating film 24 by photolithography etching. Form.
その後、前記ホトリソ・エツチングに使用したレジスト
を残したまま、全面にパラジウムを100〜120Å厚に真空
蒸着し、次いで前記レジストによるリフトオフにより不
要部のパラジウムを除去することにより、前記第１図
（ｂ）に示すように開孔部25内のAl−Si系合金膜23上に
のみパラジウムの活性化層26を形成する。Then, while leaving the resist used for the photolithography etching, palladium is vacuum-deposited on the entire surface to a thickness of 100 to 120 Å, and then the unnecessary portion of palladium is removed by lift-off by the resist to remove the palladium as shown in FIG. ), The palladium activation layer 26 is formed only on the Al-Si alloy film 23 in the opening 25.
次に、無電解めつきを行うが、その時の無電解めつき液
の組成は、金属供給源としての塩化ニツケル0.05〜0.2m
ol/，還元剤としてのDMAB（ジメチルアミンボラン）
0.05〜0.15mol/，錯化剤としてのアスパラギン酸0.1
〜0.3mol/であり、アンモニアでpHを８〜10に調整
し、液温度を70℃とする。この無電解めつき液に第１図
（ｂ）の構造体を浸し、第１図（ｃ）に示すように開孔
部25に選択的にニツケル系めつき層27を層間絶縁膜24と
段差が生じない厚さに形成する。Next, electroless plating is performed, and the composition of the electroless plating solution at that time is nickel chloride 0.05 to 0.2 m as a metal supply source.
ol /, DMAB (dimethylamine borane) as a reducing agent
0.05〜0.15mol /, aspartic acid 0.1 as complexing agent
~ 0.3mol /, adjust pH to 8 ~ 10 with ammonia, and make liquid temperature 70 ° C. The structure shown in FIG. 1 (b) is dipped in this electroless plating solution, and as shown in FIG. 1 (c), the nickel plating layer 27 is selectively stepped with the interlayer insulating film 24 in the opening 25. It is formed to a thickness that does not cause
その後、ニツケル系めつき層27上を通る第２配線層とし
てのAl−Si系合金膜28（1200Å厚程度）を第１図（ｄ）
に示すように層間絶縁膜24上に形成する。Then, an Al-Si alloy film 28 (about 1200 Å thickness) as a second wiring layer that passes over the nickel plating layer 27 is formed in FIG. 1 (d).
It is formed on the interlayer insulating film 24 as shown in FIG.
なお、この例は２層配線構造の場合であるが、上記工程
を繰り返すことにより３層以上の多層配線構造を得るこ
とができる。Note that this example is a case of a two-layer wiring structure, but a multilayer wiring structure of three layers or more can be obtained by repeating the above steps.
また、無電解めつき液で、錯化剤としてアスパラギン酸
の代りにマロン酸を用いる場合は、塩化ニツケル0.05〜
0.2mol/,DMAB0.05〜0.15mol/，マロン酸0.2〜0.5mo
l/とし、アンモニアでpHを６〜７に調整し、液温度を
70℃とする。また、金属供給源として塩化ニツケルを使
用したが、他のニツケル塩、具体的には硫酸ニツケルを
使用することもできる。When using malonic acid instead of aspartic acid as a complexing agent in an electroless plating solution, nickel chloride 0.05-
0.2mol /, DMAB0.05〜0.15mol /, malonic acid 0.2〜0.5mo
Adjust the pH to 6-7 with ammonia and adjust the liquid temperature.
Set to 70 ° C. Although nickel chloride was used as the metal source, other nickel salts, specifically nickel sulfate, can also be used.
（発明の効果） 以上説明したように、この発明の方法によれば、層間絶
縁膜開孔部の第１配線層上にパラジウム活性化層を形成
した後、金属供給源としてニツケル塩，還元剤にジメチ
ルアミンボラン，錯化剤にマロン酸またはアスパラギン
酸,pH調整剤としてアンモニアを用いた無電解めつき液
により前記層間絶縁膜開孔部にニツケル系めつき層を形
成するようにしたので、めつきのつきまわりが良く、開
孔部内に歩留り100％で前記ニツケル系めつき層を形成
できる。因みに、市販のめつき液であるニポツド468を
用いた場合、歩留りは20％程度であつた。(Effect of the Invention) As described above, according to the method of the present invention, after the palladium activation layer is formed on the first wiring layer in the opening of the interlayer insulating film, nickel salt and a reducing agent are used as the metal supply source. Since a dimethylamine borane, a complexing agent malonic acid or aspartic acid, and an ammonia electroless plating solution as a pH adjuster are used to form a nickel plating layer in the inter-layer insulation film opening, The nickel-based plating layer can be formed in the aperture with a good yield and a 100% yield. Incidentally, when Nipotud 468, which is a commercially available plating solution, was used, the yield was about 20%.
本発明者が錯化剤にアスパラギン酸を用いて実験を行つ
たところ、1000個の開孔部のチエーンで接続を確認し
た。これによつて、この発明の方法によれば、下層配線
層と上層配線層との良好な接続を得ることができ、同時
に段差のない良好な平担性を持つ半導体集積回路装置を
得ることができる。When the present inventor conducted an experiment using aspartic acid as a complexing agent, the connection was confirmed in a chain of 1000 holes. As a result, according to the method of the present invention, it is possible to obtain a good connection between the lower wiring layer and the upper wiring layer, and at the same time, to obtain a semiconductor integrated circuit device having good levelness and no step. it can.
また、この発明の方法における無電解めつき液によれ
ば、従来、めつき液として使われているナトリウム（N
a）塩が含まれていないため、半導体プロセスにおける
不純物汚染を防ぐことができる。Further, according to the electroless plating solution in the method of the present invention, sodium (N
a) Since no salt is contained, it is possible to prevent impurity contamination in the semiconductor process.
第１図はこの発明の多層配線の形成方法の一実施例を示
す工程断面図、第２図は従来の多層配線の形成方法の第
１の例を示す断面図、第３図は従来の方法の第２の例を
示す工程断面図である。 23……Al−Si系合金膜、24……層間絶縁膜、25……開孔
部、26……活性化層、27……ニツケル系めつき層、28…
…Al−Si系合金膜。FIG. 1 is a process sectional view showing an embodiment of a method for forming a multilayer wiring according to the present invention, FIG. 2 is a sectional view showing a first example of a conventional method for forming a multilayer wiring, and FIG. 3 is a conventional method. FIG. 6 is a process sectional view showing a second example of FIG. 23 ... Al-Si alloy film, 24 ... Interlayer insulating film, 25 ... Opening area, 26 ... Activation layer, 27 ... Nickel-based plating layer, 28 ...
... Al-Si alloy film.
Claims (1)
る工程と、 （ｂ）その層間絶縁膜に上記第１配線層に通じる開孔部
を形成する工程と、 （ｃ）その開孔部の上記第１配線層上にパラジウム活性
化層を形成する工程と、 （ｄ）その後、金属供給源としてニツケル塩，還元剤に
ジメチルアミンボラン，錯化剤にマロン酸またはアスパ
ラギン酸,pH調整剤としてアンモニアを用いた無電解め
つき液により前記開孔部にニツケル系めつき層を形成す
る工程と、 （ｅ）そのニツケル系めつき層上を通る第２配線層を前
記層間絶縁膜上に形成する工程とを具備してなる多層配
線の形成方法。1. A process of forming an interlayer insulating film on a first wiring layer, and a process of forming an opening communicating with the first wiring layer in the interlayer insulating film. A step of forming a palladium activation layer on the first wiring layer in the opening, and (d) thereafter, nickel salt as a metal source, dimethylamine borane as a reducing agent, and malonic acid or aspartic acid as a complexing agent. a step of forming a nickel plating layer in the opening with an electroless plating solution using ammonia as a pH adjuster; and (e) forming a second wiring layer passing over the nickel plating layer on the interlayer. A method of forming a multi-layer wiring, comprising the step of forming on an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6862486A JPH0727901B2 (en) | 1986-03-28 | 1986-03-28 | Multilayer wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6862486A JPH0727901B2 (en) | 1986-03-28 | 1986-03-28 | Multilayer wiring formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62226643A JPS62226643A (en) | 1987-10-05 |
| JPH0727901B2 true JPH0727901B2 (en) | 1995-03-29 |
Family
ID=13379089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6862486A Expired - Lifetime JPH0727901B2 (en) | 1986-03-28 | 1986-03-28 | Multilayer wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727901B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0611073B2 (en) * | 1987-03-19 | 1994-02-09 | 日本電気株式会社 | Multilayer wiring formation method |
-
1986
- 1986-03-28 JP JP6862486A patent/JPH0727901B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62226643A (en) | 1987-10-05 |
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