JPH0611073B2 - Multilayer wiring formation method - Google Patents
Multilayer wiring formation methodInfo
- Publication number
- JPH0611073B2 JPH0611073B2 JP62066564A JP6656487A JPH0611073B2 JP H0611073 B2 JPH0611073 B2 JP H0611073B2 JP 62066564 A JP62066564 A JP 62066564A JP 6656487 A JP6656487 A JP 6656487A JP H0611073 B2 JPH0611073 B2 JP H0611073B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- forming
- film
- wiring
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 14
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000011229 interlayer Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 238000007772 electroless plating Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 230000003197 catalytic effect Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線の形成方法に関し、特に金属配線間に
絶縁膜を設けて形成される半導体集積回路の多層配線の
形成方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a multilayer wiring, and more particularly to a method for forming a multilayer wiring of a semiconductor integrated circuit formed by providing an insulating film between metal wirings.
半導体集積回路における多層配線の実現のためには層間
膜の平坦化およびスルーホール部の金属の埋め込みが必
要である。層間膜の平坦化法としてはポリイミド等の塗
布膜を用いる方法があり、スルーホールの金属埋め込み
法としては無電解メッキによる方法がある。In order to realize multi-layer wiring in a semiconductor integrated circuit, it is necessary to flatten the interlayer film and bury the metal in the through holes. There is a method of using a coating film of polyimide or the like as a method of flattening the interlayer film, and a method of electroless plating is a method of embedding a metal in the through hole.
上述したポリイミドによる層間平坦化法は、ポリイミド
イの微細加工が難しいため、スルーホールサイズが１．
０μｍ程度では開孔が困難である。また、メッキによる
スルーホールの穴埋めもスルーホールサイズが１．０μ
ｍ程度になると、アスペクト比が高くなるためメッキ液
がスルーホール底部まで十分に供給されず、スルーホー
ル埋め込み金属内部に「す」が生じてしまうという問題
がある。In the interlayer flattening method using the polyimide described above, since it is difficult to finely process the polyimide, the through hole size is 1.
If it is about 0 μm, opening is difficult. In addition, the filling of the through holes by plating has a through hole size of 1.0μ.
When the thickness is about m, the aspect ratio becomes high, so that the plating solution is not sufficiently supplied to the bottom of the through hole, and there is a problem that “spots” are generated inside the through hole embedded metal.
本発明の目的は、このような問題点を解決し、平坦で多
層線間の断線のない多層配線の形成方法を提供すること
である。An object of the present invention is to solve such problems and to provide a method for forming a flat multi-layered wiring without disconnection between the multi-layered wirings.
本発明の多層配線の形成方法は、半導体基板の絶縁膜上
に形成された第１配線上に物理蒸着あるいは化学蒸着に
より第１の層間絶縁膜を形成する工程と、この第１の層
間絶縁膜上にフォトレジストを形成し、第１のスルーホ
ールを開孔する工程と、基板全面に無電解メッキのため
の触媒金属を蒸着する工程と、フォトレジストをリフト
オフ材としてリフトオフを行ない、スルーホール内部に
のみ触媒金属を残す工程を、触媒金属を用いて無電解メ
ッキを行ない第１のスルーホールをメッキ金属で埋める
工程と、基板全面に有機系塗布膜による第２の層間絶縁
膜を形成する工程と、第１のスルーホール上の第２の層
間絶縁膜に少なくとも第１のスルーホールより第２のス
ルーホールを開孔する工程と、メッキ金属により埋め込
まれた第１のスルーホールおよび第２のスルーホールを
介して第１配線と接続するように第２配線を形成する工
程とを含んで構成される。A method of forming a multilayer wiring according to the present invention comprises a step of forming a first interlayer insulating film by physical vapor deposition or chemical vapor deposition on a first wiring formed on an insulating film of a semiconductor substrate, and the first interlayer insulating film. A step of forming a photoresist on the top and opening a first through hole, a step of depositing a catalytic metal for electroless plating on the entire surface of the substrate, and a lift-off process using the photoresist as a lift-off material The step of leaving the catalytic metal only on the substrate, the step of electroless plating using the catalytic metal to fill the first through hole with the plated metal, and the step of forming the second interlayer insulating film by the organic coating film on the entire surface of the substrate. A step of forming at least a second through hole from the first through hole in the second interlayer insulating film on the first through hole, and a first through hole filled with plated metal. Configured and forming a second wiring so as to be connected to the first wiring through the hole and a second through-hole.
次に本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（Ａ）〜（Ｇ）は本発明の一実施例の製造工程を
示す断面図である。1 (A) to 1 (G) are cross-sectional views showing a manufacturing process of an embodiment of the present invention.
まず、半導体基板１上に構成された絶縁膜２上に厚さ約
１．０μｍの第１のＡｌ配線３を形成し（第１図
（Ａ））、全面にプラズマ法で窒化膜４を厚さ５０００
Å成長し、フォトレジスト５を用いて所定の位置にサイ
ズが１．０μｍのスルーホールを開孔する（第１図
（Ｂ））。次に基板全面にＰｄ膜６を５００Åスパッタ
蒸着し（第１図（Ｃ））、フォトレジスト５をリフトオ
フしてスルホール部にのみＰｄ膜６が残るようにする
（第１図（Ｄ））。次に、Ｎｉの無電解メッキを行なう
が触媒であるＰｄ膜６の存在する場所だけＮｉが成長す
るためにスルーホール部がＮｉ７により埋め込まれる
（第１図（Ｅ））。次に基板全面にポリイミド前駆体を
塗布し焼成し、配線上で５０００Åとなるようにポリイ
ミド膜８を形成する（第１図（Ｆ））。次に窒化膜４に
開孔されたスルーホール上のポリイミド膜８にサイズ
１．５μｍのスルーホールを開孔し、第２のＡｌ配線９
を形成する（第１（Ｇ））。First, the first Al wiring 3 having a thickness of about 1.0 μm is formed on the insulating film 2 formed on the semiconductor substrate 1 (FIG. 1A), and the nitride film 4 is formed on the entire surface by the plasma method. 5000
Å Growth is performed, and a through hole having a size of 1.0 μm is formed at a predetermined position using the photoresist 5 (FIG. 1 (B)). Next, the Pd film 6 is sputter-deposited on the entire surface of the substrate by 500 Å (FIG. 1 (C)), and the photoresist 5 is lifted off so that the Pd film 6 remains only in the through hole portion (FIG. 1 (D)). Next, electroless plating of Ni is performed, but Ni is grown only in the place where the Pd film 6 as a catalyst exists, so that the through hole portion is filled with Ni 7 (FIG. 1 (E)). Next, a polyimide precursor is applied to the entire surface of the substrate and baked to form a polyimide film 8 having a thickness of 5000 Å on the wiring (FIG. 1 (F)). Next, a through hole having a size of 1.5 μm is opened in the polyimide film 8 on the through hole opened in the nitride film 4, and the second Al wiring 9 is formed.
Are formed (first (G)).
第２図は本発明の第２の実施例の断面図である。製造方
法は第１の実施例と同じであるが窒化膜の代わりにスパ
ッタ法により酸化膜１４を２０００Å形成し、ポリイミ
ド膜１７は８０００Åとなっている。メッキ膜厚を６０
００Åとしているため、メッキ形状は図に示すようなも
のとなる。この第２の実施例では窒化膜を使っていない
ため、配線容量が低いという利点がある。FIG. 2 is a sectional view of the second embodiment of the present invention. The manufacturing method is the same as that of the first embodiment, but the oxide film 14 is formed to 2000 Å by sputtering instead of the nitride film, and the polyimide film 17 is set to 8000 Å. Plating film thickness 60
Since it is 00Å, the plating shape is as shown in the figure. Since the second embodiment does not use the nitride film, there is an advantage that the wiring capacitance is low.
以上説明したように、本発明は最終的な層間膜厚の約半
分の深さのスルーホールを無電解メッキにより埋め込ん
でいるため、スルーホールのアスペクト化が高くなって
も完全に埋め込むことができる。また、第２の層間膜の
ポリイミド膜をエッチングする際第１の層間膜のＳｉＮ
膜やＳｉＯ2膜はほとんどエッチングされていないた
め、多少の目ズレやオーバーエッチに対して問題は起ら
ない。これらのことから、第２Ａｌ配線のスパッタの際
のスルーホール部での第２の配線の断線を防ぐことがで
きる。さらに、ポリイミド膜を用いているため第Ａｌ配
線による段差が緩和され、配線段部での第２配線も生じ
ない。As described above, according to the present invention, since the through hole having a depth of about half the final interlayer film thickness is filled by electroless plating, the through hole can be completely filled even if the aspect ratio of the through hole becomes high. . Also, when etching the polyimide film of the second interlayer film, the SiN of the first interlayer film is etched.
Since the film and the SiO 2 film are hardly etched, there is no problem with some misalignment or overetching. From these facts, it is possible to prevent disconnection of the second wiring in the through hole portion at the time of sputtering the second Al wiring. Furthermore, since the polyimide film is used, the step due to the Al wiring is reduced, and the second wiring does not occur at the wiring step.
第１図（Ａ）〜（Ｇ）は本発明の第１の実施例の工程を
示す断面図，第２図は本発明の第２の実施例を示す断面
図である。 １，１１……半導体基板、２，１２……絶縁膜、３，１
３……第２Ａｌ配線、４……窒化膜、５……フォトレジ
スト、６，１５……パラジウム膜、７，１６……ニッケ
ル、８，１７……ポリイミド膜、９，１８……第２Ａｌ
配線、１４……酸化膜。1 (A) to 1 (G) are sectional views showing the steps of the first embodiment of the present invention, and FIG. 2 is a sectional view showing the second embodiment of the present invention. 1, 11 ... Semiconductor substrate, 2, 12 ... Insulating film, 3, 1
3 ... second Al wiring, 4 ... nitride film, 5 ... photoresist, 6,15 ... palladium film, 7,16 ... nickel, 8,17 ... polyimide film, 9,18 ... second Al
Wiring, 14 ... Oxide film.
Claims (1)
線上に第１の層間絶縁膜を形成する工程と、該第１の層
間絶縁膜上にフォトレジストを形成し第１のスルーホー
ルを開孔する工程と、基板全面に無電解メッキのための
触媒金属を蒸着する工程と、前記フォトレジストをリフ
トオフ材としてリフトオフを行ないスルーホール内部に
のみ触媒金属を残す工程と、該触媒金属を用いて無電解
メッキを行ない前記第１のスルーホールを金属で埋める
工程と、基板全面に有機系塗布膜による第２の層間絶縁
膜を形成する工程と、前記第１のスルーホール上の該第
２の層間絶縁膜に第２のスルーホールを少なくとも第１
のスルーホールより大きく開孔する工程と、金属により
埋め込まれた第１のスルーホールおよび第２のスルーホ
ールを介して第１配線と接続するように第２配線を形成
する工程とを含む多層配線の形成方法。1. A step of forming a first interlayer insulating film on a first wiring formed on an insulating film of a semiconductor substrate, and a step of forming a photoresist on the first interlayer insulating film and forming a first through film. A step of forming a hole, a step of depositing a catalytic metal for electroless plating on the entire surface of the substrate, a step of performing lift-off using the photoresist as a lift-off material to leave the catalytic metal only inside the through-hole, and the catalytic metal Electroless plating to fill the first through hole with a metal, a second interlayer insulating film made of an organic coating film over the entire surface of the substrate, and a step of forming the second through hole on the first through hole. At least a first through hole is formed in the second interlayer insulating film.
Multilayer wiring including a step of forming a larger hole than the through hole and a step of forming a second wiring so as to be connected to the first wiring through the first through hole and the second through hole embedded with metal. Forming method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066564A JPH0611073B2 (en) | 1987-03-19 | 1987-03-19 | Multilayer wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066564A JPH0611073B2 (en) | 1987-03-19 | 1987-03-19 | Multilayer wiring formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63229840A JPS63229840A (en) | 1988-09-26 |
| JPH0611073B2 true JPH0611073B2 (en) | 1994-02-09 |
Family
ID=13319569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62066564A Expired - Lifetime JPH0611073B2 (en) | 1987-03-19 | 1987-03-19 | Multilayer wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611073B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100220297B1 (en) * | 1991-12-02 | 1999-09-15 | 김영환 | Contact manufacturing method of multilayer metal wiring structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53121489A (en) * | 1977-03-31 | 1978-10-23 | Toshiba Corp | Semiconductor device |
| JPS57170524A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62172741A (en) * | 1986-01-27 | 1987-07-29 | Oki Electric Ind Co Ltd | Formation of multilayer interconnection |
| JPH0727901B2 (en) * | 1986-03-28 | 1995-03-29 | 沖電気工業株式会社 | Multilayer wiring formation method |
| JPS62298136A (en) * | 1986-06-18 | 1987-12-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
-
1987
- 1987-03-19 JP JP62066564A patent/JPH0611073B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63229840A (en) | 1988-09-26 |
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