JPH0728238B2 - Multiplex automatic switching device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device having a k-out-of-n configuration,
The present invention relates to a multiplex automatic switching device capable of automatically switching and repairing a failure occurring in the device.

(Prior Art) FIG. 1 shows a configuration of a conventional 2-out-of-4 configuration switching device, where 1 is a block composed of units X _{0 to} X ₃ of the same configuration, and 2 is a unit of the same configuration. It is a block consisting of Y _{0 to} Y ₃ .

This switching device has a function of selecting two normal units in these two blocks and connecting them in a one-to-one relationship.
One unit of block 1 and one unit of block 2 connected in pair 1 are referred to as a unit pair.

This unit pair works normally when both units are normal. 3 is a switching circuit for connecting the unit of block 1 and the unit of block 2, MU ₀ , MU ₁ ,
It consists of DU ₀ and DU ₁ . MU ₀ and MU ₁ are multiplexer units that select one from the data outputs of the three units of block 1, and DU ₀ and DU ₁ select the output of the multiplexer unit to any of the three units of block 2. It is a demultiplexer unit that is added by adding. Q is a switching control signal, which is a signal for determining input / output selection of the multiplexer unit and the demultiplexer unit.

If two or more units are normal in each of block 1 and block 2, at least two normal unit pairs can be obtained by controlling the connection between the units by the switching control signal. However, this switching device has a drawback that the failure of the switching circuit cannot be relieved.

In order to eliminate this drawback, a switching device in which a switching circuit is multiplexed is the multiplexing switching device proposed in Japanese Patent Application No. 58-232683.

FIG. 2 shows the configuration of the multiplexing switching device for the 2-out-of-4 configuration. A switching circuit 4 is composed of switching circuit units S _{0 to} S ₃ having the same configuration.

The switching circuit unit is a circuit that selects one from the data outputs of the three units of block 1 and adds it to the unit of block 2. P is a switching control signal, which is a signal for selecting the input of the switching circuit unit. Similar to the switching device of FIG. 1, in the multiplex switching device of the present invention, in blocks 1 and 2, if two or more units are normal,
Two or more normal unit pairs can be generated.

For example, as shown in FIG. 3, consider an example in which X ₀ and X ₃ of block ₁ and Y ₁ and Y _{2 of} block ₂ have failed. In the figure, a normal unit is represented by 0 and a defective unit is represented by X.

In this example, two normal pairs of (x ₁ , Y ₃ ) and (x ₂ , Y ₀ ) are formed. By the way, the failure of the switching circuit unit
It is equivalent to a failure of the unit of the block 2 to be connected and can be remedied. For example, if S ₁ and S ₂ fail, then Y ₁
This is equivalent to a Y ₂ failure and can be remedied by the inter-unit connection of this example.

As described above, the present multiplex switching device has a high fault relief capability.
However, since the user determines the connection between the units according to the failure status of the unit, the switching operation is complicated and the switching time is long.

(Object of the Invention) An object of the present invention is to solve the drawback that a user demands an inter-unit connection for a multiplex switching device capable of relieving a failure of a unit and a switching circuit, and automatically determine the inter-unit connection. It is to add a function.

(Structure of the Invention) The multiplex automatic switching device of the present invention has the same structure n (n ≧ n
2) For each block k consisting of n units Y ₀ , Y ₁ , ..., Yn _-1 , which has the same structure as the block 1 consisting of the units X ₀ , X ₁ , ..., Xn _-1 , the normal k (1 The most main feature is that the following inspection circuit, switching circuit, and switching control circuit are provided in order to automatically connect ≤k <n) units one-to-one.

An inspection circuit is provided for each unit so that the normality of the unit can be determined from the inspection output. The switching circuit is composed of n switching circuit units SU ₀ , SU ₁ , ..., SUn _-1 .

The switching circuit unit SUi switches both the data output and the inspection output of the block 1 unit so that the normality of the selected block 1 unit can be displayed.

That is, the switching circuit unit SUi is the data output D of the unit Xi.
With Xi and CXi as a pair, (n−k + 1) pairs (DXi, C
Xi), (DXi ₊₁ , CXi ₊₁ ), ..., (DXi ₊ j, CXi ₊ j), ...,
_{(DXi + n - k, CXi} + n - k) 1 set of pairs selected from (DXSi, CX
Si) is output. (Where i = 0, 1, ..., N−1. J = 0,
1, ..., nk. i + j is the sum of mod n. ) Further, the switching control circuit confirms that k or more normal unit pairs have been generated from the inspection outputs of CXS ₀ , CXS ₁ , ..., CXSn _-1 and the units Y ₀ , Y ₁ , ..., Yn _-1. It is determined and the switching by the switching circuit unit is controlled according to the result.

In the prior art, the user determines the connection between the units based on the result of testing the individual units. On the other hand, the multiplex switching device can automatically request inter-unit connection.

(Description of Embodiments) The configuration of the multiplexing automatic switching device proposed here will be described in 2-out-o.
A description will be given based on a specific example of f-4. General k-out
The switching device having the -of-n switching configuration can be easily expanded from the following description.

FIG. 4 is an explanatory diagram of a multiplex automatic switching device having a 2-out-of-4 switching configuration. X _{0 to} X ₃ are units of block 1, Y ₀
~ Y ₃ is a unit of the block 2 and is a circuit to be switched.

DX _{0 to} DX ₃ are outputs of X _{0 to} X ₃ , respectively, and DY _{0 to} DY ₃ are outputs of Y _{0 to} Y ₃ , respectively. CKX _{0 to} CKX ₃ are inspection circuits provided in X _{0 to} X ₃ , and CX _{0 to} CX ₃ are inspection outputs thereof.

In addition, CKY _{0 to} CKY ₃ are the inspection circuits provided in Y ₀ to Y ₃ , and
_{0 to} CY ₃ is the inspection output. Inspection circuit CKX ₀ ~CKX _3, CKY
_{0 to} CKY ₃ have the function of detecting a failure by monitoring the output of the circuit under test. Test output CX ₀ ~CX _3, CY ₀ ~CY
_{According to 3} , the inspection result is displayed as follows.

When Xi is normal (failure) CXi = 1 (0) When Yi is normal (failure) CYi = 1 (0) where i = 0,1,2,3. A specific example of the inspection circuit will be described later.

A switching circuit 5 is composed of switching circuit units SU _{0 to} SU ₃ . The switching circuit connects X _{0 to} X ₃ and Y ₀ to Y ₃ as shown in FIG. However, in FIG. 2, the block 1 and the switching circuit 2 are
The wiring for data output was between the two, but here it is wiring for a pair of data output and inspection output. That is, the switching unit SUi is (DXi, CXi), (DXi _{+ 1} , CXi _{+ 1} ), (DX
i ₊₂ , CXi ₊₂ ) three sets of bears are input, and one set of the bears is output to (DXSi, CXSi). Here, + represents addition of mod 4.

A switching control circuit 6 generates a switching control signal P,
This is a circuit that determines the connection method between the units. Also, 7
Is an input signal of X _{0 to} X ₃ , and 8 is an output signal of Y ₀ to Y ₃ .

The operation of the multiplex automatic switching device of FIG. 4 is performed as follows.

(1) A pulse is applied to the signal INIT to set the switching control circuit 6 to the initial state.

(2) Test inputs CKY _{0 to} CKX _{3 by} adding test inputs from 7.
And the CKY ₀ ~CKY _3, respectively to test the X ₀ to X ₃ and Y ₀ to Y _3.

(3) The switching control circuit 6 determines whether or not the inspection results CXS _{0 to} CXS ₃ and CY ₀ to CY ₃ and the switching control signal P satisfy the connection conditions.

(4) If the connection conditions are satisfied, fix the current inter-unit connection. If not satisfied, when a clock pulse is input to the signal CLOCK, the switching control circuit 6 newly generates a switching control signal. (3) is repeated for a new inter-unit connection corresponding to this switching control signal.

The connection conditions will be described later.

In this multiplex automatic switching device, if there are two or more normal units in each of the blocks 1 and 2, it is possible to find a connection method for making two or more sets of normal unit bears.

This means that even if a sufficient number of clock pulses are added to the switching control circuit 6 to generate all the connection methods, this failure cannot be remedied unless the above switching operation is completed.

Now, as a concrete example of the inspection circuit, FIG. 5 shows 1-out-of-
4 shows a test circuit for a 4-decoder.

A and B are inputs to the 1-out-of-4 decoder, and G ₀ , G ₁ , G ₂ and G ₃ are outputs. When the circuit under test is normal, A, B
Depending on the input value of, any one output of D _{0 to} D ₃ is “1”
Becomes At this time, C outputs "1". However, when a failure occurs in the circuit to be inspected and the output of an even number of G _{0 to} G ₃ becomes "1", C becomes "0". Therefore, by monitoring C, it is possible to detect the failure of the circuit to be inspected.

By the way, in FIG. 4, for the sake of simplicity, the switching circuit unit is not provided with an inspection circuit.

For the switching circuit unit, for example, a check circuit for performing a parity check for the data signal and a 1 / n check for the switching control signal can be provided. If the logical sum of the output of the inspection circuit of the switching circuit unit SUi and the inspection output CYi of the unit of the block 2 is set to CYi again, the failure of the switching circuit unit can be automatically relieved.

Next, the configuration of the switching control circuit 6 will be described. The switching control circuit 6 has two types of realization methods, a brute force method and a permutation method. The brute force method is a method in which the connection method between all the units to be connected is generated by a counter.
In addition, the permutation method uses only one block 1 and block 2 unit.
This is a method in which only the connection method for connecting to pair 1 is generated by the permutation generation circuit.

[Embodiment 1] FIG. 6 shows a configuration of a switching control circuit 6 by the brute force method.
The switching control circuit 6 includes a switching destination determination circuit 11 and an overlap selection detection circuit.
12, a normal unit pair detection circuit 13, a normal unit pair threshold circuit 14, and a clock control circuit 15. The relationship between 11 and 15 will be explained using FIG.

FIG. 7 shows a circuit example of the switching destination determining circuit 11. The circuit consists of four ternary counter CTR ₀ ~CTR ₃ was continued connection.

In the brute force method, according to the contents ai of CTRi, the switching circuit unit
SUi connects unit Xi ₊ ai and unit Yi (however,
i = 0,1,2,3. ai = 0,1,2).

That is, the switching destination determination circuit 11 uses the switching control signal P = (a ₀ , a
₁ , a ₂ , a ₃ ) is generated and the switching circuit 5 is controlled.

FIG. 8 shows an example of a ternary counter used in the switching control circuit, and 601 and 602 are T-type flip-flops.

Let the contents of 601,602 be U ₀ and U ₁ , respectively, and combine these,
I will write it as (U ₀ , U ₁ ).

When a pulse is applied to the signal INIT, 601 and 602 are reset and (U ₀ , U ₁ ) becomes (0, 0).

Then, when pulses are added to the signal CIN one after another, (0,0) →
The transition is (0,1) → (1,0) → (0,0), and this is repeated thereafter.

When (U ₀ , U ₁ ) is (1, 0), the signal COUT outputs a pulse to the ternary counter in the next stage.

When (U ₀ , U ₁ ) is (0,0), (0,1), (1,0), the signals D ₀ , D ₁ , and D ₂ are “1”, respectively.

That is, the content ai of the counter CTRi is displayed when the signal Dai outputs "1". In this case, since Yi and Xi ₊ ai is connected, it referred to the signal Dai to hereinafter ▲ P ^{i + ai} _x ▼. However, T is the addition of mod.4.

Here, let us describe the connection between units of block 1 and block 2 as an integer string as follows.

The unit connected to the unit Yi is Xbi, and the units connected to the four units Y _{0 to} Y ₃ are integer strings [b ₀ , b ₁ , b ₂ ,
b ₃ ].

In the brute force method, b ₁ = i + ai holds. However, + is mod
It is an addition of 4.

The switching destination determination circuit 11 has a switching control signal P = (0,0,0,0),
According to (1,0,0,0), (2,0,0,0), ..., (2,2,2,2), [0123], [1123], [2123], ..., respectively. (2301)
It generates 3 ⁴ connection methods.

Initial state (connection method conceived of integer sequence [0123])
Is set by resetting all counters by sending a pulse to the signal INIT.

In the brute force method, the same unit in block 1 may select a plurality of units in block 2 in duplicate. For example, in the conceivable connection method of [1123], the unit X ₁ is selected by overlapping the units Y ₀ and Y ₁ .

Each unit pair of the multiplexing automatic switching device performs independent processing for different data input.

Therefore, in this example, even if all three units X ₁ , Y ₀ , Y ₁ are normal, two unit pairs (X ₁ , Y ₀ ), (X ₁ , Y ₁ )
Only one of them can be used. Therefore, it is necessary to prohibit the connection method in which the same unit of block 1 is redundantly selected by a plurality of normal units of block 2.
For this reason, the circuit that detects duplicate selection is the duplicate selection detection circuit.
Twelve.

FIG. 9 shows a circuit of the duplicate selection detection circuit 12. THC _{0 to} THC ₃
Is a threshold circuit, and two or more of the three inputs E ₀ , E ₁ , and E ₂ are “1”. FIG. 10 shows a circuit example of the threshold circuit. THCl inputs three signals ▲ P ^l _1-j ▼ (where l = 0,1,2,3, j = 0,1,2, where l−j is the difference of mod 4).

Therefore, THCl outputs "1" to T when the unit Xl is selected as the normal unit of block 2. The duplication selection detection signal HS outputs "1" when any of the units X _{0 to} X ₃ is duplication selected.

FIG. 11 shows a circuit example of the normal unit pair detection circuit 13.
The good unit pair detection circuit 13 is a circuit that determines whether or not the unit pair is normal. Normal unit pair detection GP
Is expressed as GP = (GP ₀ , GP ₁ , GP ₂ , GP ₃ ). Where GPi
Is a signal that outputs "1" when it is determined from the inspection result CXSi of the unit of block 1 and the inspection result CYi of block 2 that the unit pair including Yi is normal.

FIG. 12 shows a circuit example of the normal unit pair threshold circuit 14.

Normal unit pair threshold circuit 14 has 2 normal unit pairs
It is a circuit that determines that there are more than a set (k sets or more in a general k-out-of-n configuration switching circuit), inputs a normal unit pair detection signal GP, and outputs a threshold value determination signal GEK.

When two or more signals among GP _{0 to} GP ₃ are “1”, GEK takes “1”.

FIG. 13 is a circuit example of the clock control circuit 15. this is,
It has a function of stopping the clock of the switching destination determination circuit 11 when the following connection conditions are satisfied.

[Connection condition of brute force method]

(1) There are two or more normal unit pairs (at this time, GEK = "1").

(2) The same unit of block 1 is not duplicatively selected by a plurality of normal units of block 2 (at this time,
MS = "0").

When the condition (1) or (2) is not satisfied,
The clock pulse input to the signal CLOCK is the signal CLOCK1.
Then, the counter of the switching destination determination circuit 11 increments. As a result, a switching control signal P is newly generated,
The connection method is updated.

[Second Embodiment] A switching control circuit 6 based on the permutation method will be described. First, let us explain permutations.

FIG. 14 is an explanatory diagram of permutation taking 4! As an example. Set {0,
Let [b ₀ , b ₁ , b ₂ , b ₃ ] be an integer sequence formed by using the four elements of 1, 2, 3} once. Where bi (i = 0,1,2,3)
Is the (i + 1) th element from the left that constitutes the integer sequence.

Now, [b ₀ , b ₁ , b ₂ , b ₃ ] is obtained as follows according to the arrow in FIG.

b ₀ is 0, 1, 2, or 3.

b ₁ is one of the three elements except the element selected in b ₀ .

b ₂ is one of the remaining two elements except the element selected by b ₀ and b ₁ .

b ₃ is the remaining one element except the element selected by b ₀ , b ₁ , and b ₂ .

According to this rule, as _{[b 0, b 1, b 2} , b 3 ] [0123]
[0132], ..., [3012] 4! = 24 integer strings can be created.
A set of integer sequences obtained by changing the arrangement of elements in this way is called a permutation.

In general, an integer sequence of length n [b ₀ , b ₁ , ..., bn _-1 ] that can be arranged by using n elements of the set {0, 1, ..., n-1} only once
Since n! Can be generated, this is called n! Permutation because it can generate n!

Now, as mentioned before, if the connection between units is expressed by an integer sequence [b ₀ , b ₁ , b ₂ , b ₃ ], X ₀ ~ X ₃ and Y ₀ ~ Y ₃
All connection methods that connect 1 to 1 can be represented by a permutation of 4 !.

On the contrary, if the permutation of 4! Is generated, all the connection methods for connecting the above units one to one can be generated. From this point of view, the permutation method is a method of determining the connection between units by permutation.

FIG. 15 shows the configuration of the switching control circuit 6 by the permutation method. It should be noted that the previously mentioned signal names have the same functions as the brute force method unless otherwise noted. The switching control circuit 6 includes a permutation generation circuit 21,
It includes a normal unit pair detection circuit 22, a normal unit pair threshold circuit 14, and a clock control circuit 23.

The relationship between the normal unit pair threshold circuit 14 and the circuits 21 to 23 is shown in the 15th section.
It will be described with reference to the drawings.

The permutation generation circuit 21 generates a switching control signal P corresponding to an integer sequence. Therefore, this circuit is a circuit corresponding to the switching destination determination circuit 11 in the brute force method. The configuration and operation of the permutation generation circuit 21 will be described later.

Since the permutation method guarantees a one-to-one connection between the units, the same unit in block 1 is not redundantly selected as in the brute force method. Therefore, the duplicate selection detection circuit is unnecessary.

However, the permutations of 4! Include integer sequences that cannot be replaced by unit-to-unit connections. For example, as shown in FIG.
Since Y ₀ and X ₃ have no connection relation, there is no connection method corresponding to the integer sequence [3012]. Therefore, in the permutation method, it is necessary to judge whether or not there is a connection method corresponding to an integer sequence.

FIG. 16 shows a circuit example of the normal unit pair detection circuit 22.
This is a circuit for confirming that the connection method corresponding to the integer sequence exists and that the generated unit pair is normal. It differs from the normal unit pair detection circuit of the brute force method in that it has the former function. Signal GPi (i =
0,1,2,3) unit Yi is connected to unit Xbi,
Moreover, when the unit pair is normal, "1" is output.

The normal unit pair threshold circuit 14 is the first one described in [Embodiment 1].
It is the circuit of Figure 12.

FIG. 17 shows a circuit example of the clock control circuit 23. When the threshold judgment signal GEK of the normal unit pair threshold circuit 14 is “1”,
This circuit outputs the signal C from the clock pulse applied to the signal CLOCK.
Two-phase clock is generated for LOCK1 and signal CLOCK2, and GEK is "0".
When, the two-phase clock is stopped. The permutation display section and the cyclic mode control section of the permutation generation circuit 21 are alternately operated by this two-phase clock.

Now, the connection conditions of the permutation method are as follows.

[Connection condition of permutation method]

 (1) There is a connection method corresponding to an integer sequence.

(2) There are two or more normal unit pairs.

Normal unit pair detection circuit 22 and unit pair threshold circuit 14
Determines the above conditions (1) and (2). Condition (1),
If both (2) are satisfied, GEK becomes "0" and the permutation generation circuit 21 is supplied with a two-phase clock. As a result, the switching circuit 5 retains the current connection method.

When condition (1) or condition (2) is not satisfied, GE
K becomes "1", and the two-phase clock is supplied to the permutation generation circuit 21. As a result, the switching circuit 5 updates the connection method.
The above is the description of the switching control circuit based on the permutation method.

Next, the 4! Permutation generation circuit 21 applied to the multiplex automatic switching device having the 2-out-of-4 configuration will be described. This permutation generating circuit 21 is an algorithm proposed by London GG (An Algorithm for generating permutations CACM 1
0, p298-299, 1967) is a dedicated hardware circuit.

FIG. 18 shows the configuration of the permutation generation circuit 21 of 4 !, 31 is a permutation display unit, 32 is a cyclic mode control unit, 33 is a 3-way multiplexer, and 34 is a clock generation circuit.

R _{0 to} R ₃ are registers that store the elements b _{0 to} b ₃ , respectively, and their outputs serve as switching control signals.

The permutation display unit 31 has a function of displaying an integer sequence [b ₀ b ₁ b ₂ b ₃ ] and generating a new integer sequence [b ₀ ′ b ₁ ′ b ₂ ′ b ₃ ′] from this.

The partial sequence of integers [b ₀ ... bi _-1] Right cyclic length i (i = 2,3,4), by connecting the remaining part integer sequence [bi ... b _3] The integer column [ b ₀ ′ b ₁ ′ b ₂ ′ b ₃ ′], the cyclic mode Mi
It will be called derivation by. That is, at this time, the integer sequence [b ₀ ′ b ₁ ′ b ₂ ′ b ₃ ′] can be described as follows using [b ₀ b ₁ b ₂ b ₃ ].

First, the right-circulating sub-integer sequence is b ₀ ′ ← bi _-1 b ₁ ′ ← b ₀ b ₂ ′ ← b ₁・ ・ ・ b ′ i _-1 ← bi _-2 bi b'i ₊₁ ← bi ₊₁ ... b ₃ ′ ← b ₃ Therefore, the permutation display unit 31 operates as follows.

The data stored in the registers R ₀ , R ₁ , ..., Ri _-1 circulate right, and the data stored in the registers Ri, Ri ₊₁ , ..., R ₃ are not updated.

In addition, the maleplexer 33 selects from the registers R ₁ , R ₂ and R ₃ .
Select the output that will be Ri _-1 and input it to register R ₀ . The clock generation circuit 34 is a register that stores data that circulates to the right.
Supply clock to R ₀ , R ₁ , ..., Ri _-1 .

FIG. 19 shows a circuit example of the clock generation circuit 34. Signal CLK1
Is the clock signal that feeds registers R ₀ and R ₁ ,
CLK2 and CLK3 are clock signals supplied to the registers R ₂ and R ₃ , respectively.

Cyclic mode Mj _+1, Mj _+2, ..., when the M _4, the clock pulse from the CLOCK2 to CLKj to DenHata. As a result, register Rj
The content of is updated.

The traveling mode control unit 32 is a circuit that determines the traveling mode Mi. This internal structure will be described later.

In the operation of the permutation generation circuit 21 of FIG. 18, first, the permutation display unit 31 and the cyclic mode control unit 32 are set to the initial state. The initial state will be described later.

Next, the clock control circuit 23 alternately generates clock pulses in the order of the signals CLOCK1 and CLOCK2. Each time a clock pulse is applied, the cyclic mode control unit 32 sets the cyclic mode,
Based on this, the permutation display unit 31 sequentially generates new integer sequences. In this way, the permutation generation circuit 21 can generate 4! Permutations.

Next, the permutation generation procedure of the permutation generation circuit 21 will be described with reference to FIG.

[Procedure for generating permutation of 4!] (1) Initialize integer sequence A = [0123]. When the M ₂ mode is repeated twice, an integer string [0123] is generated in the process and the original integer string A is returned. (“1”, “2”) (hereinafter “1” to “40” indicate the order of occurrence) (2) In the M ₃ mode, the left three elements of A are circulated right, and a new integer sequence B = [ 2013]. ("3") (3) Perform the above operations (1) and (2) on B, and as a result, newly obtain integer sequences [0213] and [1203].
(“4”, “5”, “6”) (4) Perform the above operations (1) and (2) on C, and as a result, obtain a new integer sequence [2103] and return to A.
(“7”, “8”, “9”) (5) In the M ₄ mode, all the elements of A are right-circulated to obtain a new integer sequence D = [3012]. (“10”) (6) Perform the above operations (1) to (5) on D and select [03
21], [1302], [3102], [0132], [1032] 5
Obtain an integer sequence and generate an integer sequence E = [2301].
(“11” to “20”) (7) Perform the above operations (1) to (5) on E and select [32
01], [0231], [2031], [3021], [0321] 5
Obtain an integer sequence and generate an integer sequence F = [1230].
("21" to "30") (8) Perform steps (1) to (5) above on F and select [21
30], [3120], [1320], [2310], [3210], [12
30] and get back to A. ("31", ~ "4
0 ”) When this algorithm is expressed recursively, it becomes as follows.

[Operation [G ⁴ ₃ ]] (1) The partial integer sequence [b ₀ , b ₁ ] is circulated rightward twice. (M ₂
Mode) (2) The partial integer sequence [b ₀ , b ₁ , b ₂ ] is rotated rightward once.
(M ₃ mode) [Operation ▲ G ⁴ ₄ ▼] (1) Repeat operation ▲ G ⁴ ₃ ▼ three times.

(2) The integer sequence [b ₀ , b ₁ , b ₂ , b ₃ ] is circulated once to the right. (M
₄ mode) The algorithm to be obtained based on the above preparation is [Permutation generation algorithm of 4!] Operation [G ⁴ ₄ ] is repeated 4 times for the initial state [0123].

From the above, it can be seen that the permutation generating circuit of FIG. 18 that right circulates a partial integer sequence of lengths 2 to 4 has a function of generating the sequence 4 !. In this algorithm, the permutation is derived by right-circulating the partial integer sequence, but it is clear that the permutation can be similarly derived by left-circulating.

Now, the traveling modes that appear in the process of generating the sequence of 4! Are as follows.

M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ , M ₄ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ , M ₄ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ , M ₄ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ M ₂ , M ₂ , M ₃ , M ₄ This cyclic mode sequence is represented as 4 (3 (2M ₂ , M ₃ ), M ₄ ). Here, the integer before the symbol of the cyclic mode Mi indicates the number of repetitions of Mi. Also, the integer before the left parenthesis indicates the number of times the portion enclosed by the parentheses is repeated.

In the above cyclic mode sequence, 2M ₂ repeats M ₂ twice, 3 (2M ₂ , M ₃ ) repeats sequence 2M ₂ , M ₃ 3 times, and 4 (3 (2M ₂ , M 3 ₃ ), M ₄ ) means repeating series 3 ((2M ₂ , M ₃ ), M ₄ ) four times.

The above cyclic mode sequence is generated according to the following rules.

(1) Generate a cyclic mode sequence of 2M ₂ and M ₃ .

(2) When the M ₃ mode appears three times, the M ₄ mode is generated after the third M ₂ mode.

Fig. 21 shows the cyclic mode control unit operating based on this rule.
An example of 32 circuits is shown. The generation of the cyclic modes M ₂ , M ₃ , M ₄ is indicated by setting the signal lines M ₂ , M ₃ , M ₄ to “1”, respectively.

Cyclic shift register according to the D-type flip-flop 701 to 704, when generating a cyclic mode sequence 2M _2, M _3, M _4, a cyclic loop of length 3, round mode sequence 2M _2, M _3, M ₄ generation When forming, a cyclic loop of length 4 is formed. CTR is quaternary counter, generated M ₄ mode on the basis of rule (2).

Figure 22 shows an example of CTR configuration.

The circuit operation of the cyclic mode control unit 32 of FIG. 21 is as follows.

(1) Add a pulse to the signal INIT to set it to the initial state. That is, in the cyclic shift register, the contents of 701 are set to "1" and the contents of 702 to 704 are set to "0". Also, CTR
Set the content of to "0". (At this time, the M ₂ mode is generated.) (2) Every time a clock pulse is applied to the signal CLOCK1, the data "1" is shifted by the cyclic shift register. At the third clock pulse, data “1” circulates in the loop of length 3 of the cyclic shift register, and the first clock pulse is added to CTR. (M ₂ and M ₃ are generated.) (3) In the same way as (2), in the loop of length 3 of the cyclic shift register, the data “1” circulates and a clock pulse is added to CTR. (2M ₂ and M ₃ are generated.) (4) In the loop of length 4 of the cyclic shift register, data “1” circulates and a clock pulse is added to CTR. At this time, the CTR generates M ₄ . (2M ₂ , M ₃ and M ₄ are generated.) (5) When the above operations (2) to (4) are repeated three times, the initial state is restored.

The above is the description of the cyclic mode control unit 32 of FIG. 21 that generates a cyclic mode sequence of 4 (3 (2M ₂ , M ₃ ), M ₄ ).

As a cyclic mode series to generate even 4! Permutations In addition to _{this, 4 (2 (3M 3,} M 2), M 4) 3 (4 (2M 2, M 4), M 3) 3 (2 (4M 4 , M ₂ ), M ₃ ) 3 (2 (4M ₄ , M ₂ ), M ₃ ) 2 (4 (3M ₃ , M ₄ ), M ₂ ) 2 (3 (4M ₄ , M ₃ ), M ₂ ) There is.

The above cyclic mode sequence t ₄ can be collectively expressed as follows.

t ₂ ＝ r ₂・ Mr ₂ t ₃ ＝ r ₃・ (t ₂ ,, Mr ₂ ) t ₄ ＝ r ₄・ (t ₃ ,, Mr ₄ ) where the three elements of the set {2,3,4} are Using 3! = 6 integer strings [r ₂ , r ₃ , r ₄ ] that can be used once each as an element,
Define r ₂ , r ₃ and r ₄ . In the above specific example, r ₂ = 2, r ₃ = 3, r ₄
= 4.

The above is the description of the permutation generation circuit of 4 !. By using this permutation generation circuit, a switching control circuit by the permutation method can be created.

The proposed multiplex automatic switching device has been described based on a 2-out-of-4 switching configuration. A multiplexing automatic switching device in a general k-out-of-n switching configuration can be easily inferred from this example.

(Effects of the Invention) As described above, the present invention has an advantage of providing a switching configuration for relieving a failure of a unit and a switching circuit itself,
It is applied as follows.

In manufacturing an LSI, if a circuit to be switched is multiplexed and a multiplexing automatic switching device according to the present invention is provided, a defective unit is detected by an inspection circuit, and this is switched to a normal unit for use. Has a high yield by
Can manufacture LSI.

Further, with respect to the circuit under normal processing, the multiplex automatic switching device according to the present invention can detect the fixed fault and the intermittent fault by the inspection circuit and switch to the normal unit, thereby realizing the high reliability of the device.

Since the above defects and failures are automatically switched, they are quickly repaired without bothering the user.

[Brief description of drawings]

FIG. 1 is a diagram showing an application example of a 2-out-of-4 switching configuration of a conventional switching device, and FIG. 2 is a 2-out-of the multiplexing switching device proposed in Japanese Patent Application No. 58-232683. -4 is a diagram showing an application example of the switching configuration, FIG. 3 is a diagram showing a method of repairing a failure of the multiplex switching device of FIG. 2, and FIG. 4 is a 2-out-of-of the multiplex switching device of the present invention. FIG. 5 is a diagram showing an application example of a 4-switching configuration, FIG. 5 is a diagram showing a 1-out-of-4 decoder and its inspection circuit, FIG. 6 is a configuration diagram of a switching control circuit 6 of the brute force method, and FIG.
FIG. 8 is a diagram showing an embodiment of the switching destination determination circuit 11, FIG. 8 is a diagram showing an embodiment of a ternary counter (CTR _{0 to} CTR ₃ ), and FIG. 9 is a diagram showing an embodiment of the duplicate selection detection circuit 12. FIG. 10 is a diagram showing an embodiment of a threshold circuit (THC _{0 to} THC ₃ ), FIG. 11 is a diagram showing an embodiment of a normal unit pair detection circuit 13 of the brute force method, and FIG. 12 is a normal unit pair threshold value. FIG. 13 is a diagram showing an embodiment of the circuit 14,
The figure shows an embodiment of a clock control circuit 15 of the brute force method,
FIG. 14 is an explanatory view of the permutation of 4 !, FIG. 15 is a configuration diagram of the switching control circuit 6 of the permutation method, FIG. 16 is a diagram showing an embodiment of a normal unit pair detection circuit 22 of the permutation method, and FIG. Is a diagram showing an embodiment of a clock control circuit 23 of the permutation method, FIG. 18 is a block diagram of the permutation generation circuit 21 of 4 !, FIG. 19 is a diagram showing an embodiment of the clock generation circuit 34, and FIG. Figure 21 shows an example of the permutation generation procedure for!
FIG. 22 is a diagram showing an embodiment of the cyclic mode control unit 32 of the 4! Permutation generating circuit, and FIG. 22 is a diagram showing an embodiment of a quaternary counter. 1,2 ... Block, 3,4,5 ... Switching circuit, 6 ... Switching control circuit, 7 ... Block 1 input, 8 ... Block 2 output, 9 ... 1-out-of-4 Decoder inspection circuit, 11 ...
… Switching destination determination circuit, 12 …… Duplicate selection detection circuit, 13 …… Round robin method normal unit pair detection circuit, 14 …… Normal unit pair threshold circuit, 15 …… Brute force clock control circuit,
21 ... permutation generation circuit, 22 ... permutation method normal unit pair detection circuit, 23 ... permutation method clock control circuit, 31 ... permutation display section, 32 ... cyclic mode control section, 33 ... 3way multiplexer, 34 …… Clock generation circuit, 101-198 …… AND
Gate, 201-272 …… OR gate, 301-341 …… Inversion gate, 401 …… EXOR gate, 501 …… NOR gate, 601-622
...... T-type flip-flop, 701 to 704 …… D-type flip-flop, X _{0 to} X ₃ …… Block 1 unit, Y _{0 to} Y ₃ …
… Unit of block 2, MU ₀ , MU ₁ …… Multiplexer unit, DU ₀ , DU ₁ …… Demultiplexer unit, S ₀
~ S ₃ ... Switching circuit unit of multiplex switching device, SU _{0 to} SU ₃
...... Switching circuit unit of multiplex automatic switching device, P, Q ……
Switching control signal, ▲ P ⁰ ₀ ▼, ▲ P ¹ ₀ ▼, ▲ P ² ₀ ▼,
▲ P ¹ ₁ ▼, ▲ P ² ₁ ▼, ▲ P ³ ₁ ▼, ▲ P ² ₂ ▼, ▲
P ³ ₂ ▼, ▲ P ⁰ ₂ ▼, ▲ P ³ ₃ ▼, ▲ P ⁰ ₃ ▼, ▲ P
¹ ₃ ▼ …… Elements of switching control signal P, A, B …… decoder input, G _{0 to} G ₃ …… decoder output, C …… decoder inspection output, MS …… duplication selection detection signal, GEK …… threshold judgment Signal, G
P …… Normal unit pair detection signal, GP _{0 to} GP ₃ …… Normal unit pair detection signal GP element, INIT …… Initial setting signal,
CLOCK, CLOCK1, CLOCK2 …… Clock signal, CTR _{0 to} CTR ₃ …
… Ternary counter, D _{0 to} D ₃ …… Ternary counter output, CIN
…… Clock input, COUT …… Clock output, T ₁ CK …… Clock input, CLR …… Reset input, PR …… Preset input, D …… Data input, Q, …… Data output, THC ₀ ~
THC ₃ ...... threshold circuit, E _{0 to} E ₃ ...... threshold circuit input, F ...... threshold circuit output, R _{0 to} R ₃ ...... stores integer sequence [b ₀ , b ₁ , b ₂ , b ₃ ]. register, CLK1~CLK3 ...... clock signal, M ₂ ~M ₄ ...
… Crawling mode signal, CTR… Quaternary counter.

Claims (3)

[Claims] 1. n (n ≧ 2) units X ₀ , X having the same structure
_With respect to the block 2 composed of n units Y ₀ , Y ₁ , ..., Yn ₋₁ having the same configuration as the block 1 composed of ₁ , ..., Xn ₋₁ , normal k (1 ≦ k < n) n-units are selected and automatically connected one to one k-out-of-n
In the constituent electronic device, an inspection circuit which is given to each unit and determines its normality, and a data output DXi of an arbitrary unit Xi and an output CXi of the inspection circuit are paired, and (n−k + 1) sets of pairs (DXi , CX
i), (DXi ₊₁ , CXi ₊₁ ), ..., (DXi ₊ j, CXi ₊ j), ...
., (DXi ₊ n _- k, CXi ₊ n _- k) One pair (DXS
i, CXSi) output n switching circuit units SUi (however,
i = 0,1, ..., n-1. j = 0, 1, ..., N−k. i + j
Is the sum of mod n) and the outputs CXS ₀ , CXS ₁ , ..., CXSn _{-1 of the} switching circuit unit.
And a switching control circuit for controlling the switching circuit unit so that the normal units of the block 1 and the block 2 are connected one-to-one from the outputs of the inspection circuits of the units Y ₀ , Y ₁ , ..., Yn _-1. Multiplexing automatic switching device characterized by being performed. 2. As the switching control circuit, n is continuously connected.
Based on the contents ai of the (n−k + 1) -ary counter CTRi,
Switching circuit that controls the switching circuit unit so that the unit Xi ₊ ai and the unit Yi are connected (however, i = 0, 1, ...
,, n-1. ai = 0,1, ..., n−k. i + ai is the sum of mod n), and a normal unit pair detection circuit that indicates that the unit pair consisting of these two connected units is normal from the inspection output, and normal output from the normal unit pair detection circuit. From the normal unit pair threshold circuit that indicates that there are k or more unit pairs, and the output of the switching destination determination circuit and the inspection output of the unit of block 1, the same unit of block 1 becomes multiple normal units of block 2. It is judged from the outputs of the duplication selection detection circuit that indicates not to be connected and the normal unit pair threshold circuit and the duplication selection detection circuit that k or more normal units are connected one to one, and at this time, the switching decision is made. A switching control circuit comprising a clock control circuit for stopping the clock of the circuit counter is used. The multiplexing automatic switching device according to item (1). 3. Each of the switching control circuits is an integer 0.
... Registers that can display n-1 R ₀ , R ₁ , ..., Rn _-1 , transfer bus from R ₀ to R ₁ , R ₁ to R ₂ , ..., Rn _-2 to Rn _-1 , R ₂ to R ₀ , R ₃ to R ₀ , ..., Rn _-1 to R ₀ are provided, and the contents of these registers are circulated each time a clock is applied, so that the integer {0, 1, ..., n−
1} is the number of sorts that can be rearranged, and the contents of register Ri are bi
It is displayed as the alignment number [b ₀ , b ₁ , ..., bn _-1 ] and the permutation generation circuit that connects the unit Xbi and the unit Yi, and the permutation generation that a normal unit pair exists is generated. A normal unit pair detection circuit displayed from the output of the circuit and the output of the inspection circuit, a normal unit pair threshold circuit indicating that there are k or more normal unit pairs from the output of the normal unit pair detection circuit, and a normal unit pair threshold circuit. A switching control circuit comprising a clock control circuit for stopping the clock to the permutation generation circuit when there are k or more unit pairs, and the switching control circuit is used. Multiplexing automatic switching device.