JPH0731882B2 - Digital audio circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital audio circuit, and more particularly to a digital audio circuit which converts 2-channel audio serial data into an analog signal and outputs it as a 2-channel analog audio signal of an arbitrary combination. .

2. Description of the Related Art An ordinary video disc is one in which a video signal and an audio signal are each frequency (FM) modulated and recorded, but in recent years, an audio signal is digitized by a predetermined digital modulation method to form a pulse train signal, which is called a video signal. A video disc, a so-called video disc with digital audio, has been developed and commercialized by a system (see Japanese Patent Laid-Open No. 59-171011) in which a signal and an audio signal are superimposed on each FM modulation signal and recorded. According to this video disc with digital audio, in addition to high-quality images, 2-channel Hi-Fi sound can be obtained.

In such a reproducing apparatus for a video disk with digital audio, when the demodulated digital audio output is, for example, audio multiplex, L (left) is Japanese and R (right) is a foreign language. As shown, the demodulated digital output demodulated by the RCM decoder 1
Analog (hereinafter abbreviated as D / A) converters 2L and 2R are analogized in synchronization with the bit clock and data latch signals generated from the PCM decoder 1 and separated into L and R channel analog audio signals. Then, these analog audio signals are supplied via LPFs (low-pass filters) 3L, 3R and buffer amplifiers 4L, 4R to mode changeover switches 5L, 5R operating independently of each other, and select signals are supplied to these switches 5L, 5R. Depending on the Lch and Rch select signals output from the generation circuit 6, the sound output from the L and R channel output terminals 7L and 7R is one of three output modes: Japanese and foreign language, Japanese only and foreign language only. And the operation of selecting is performed.
59-194439 gazette).

However, in the above-mentioned conventional device, the mode changeover switch
The audio signal itself is switched by 5L, 5R. Since a relay or an analog switch is used as the switch 5L, 5R, the sound quality increases as the number of contacts through which the audio signal passes increases. It has the drawback that it deteriorates and the SN ratio tends to deteriorate.

If relays are used as the mode changeover switches 5L and 5R, two relay drive circuits are required in addition to the two relays, which requires a large space for arranging parts and consumes a lot of power. There is a drawback that the electric power also becomes large.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the related art, and an object of the present invention is to provide a digital audio circuit capable of mode switching with a small amount of power without deteriorating the SN ratio and the sound quality. And

The digital audio circuit according to the present invention takes in a multiplexed digital audio signal in which L and R channel audio data are time-division multiplexed in response to a first bit clock and converts it into an analog signal in response to a data latch signal. An L channel D / A converter for converting to an L channel audio output signal, and the multiplexed digital audio signal is taken in according to a second bit clock and converted into an analog signal in accordance with the data latch signal to output an R channel audio output. An R channel D / A converter as a signal, and in the monaural mode, each of the first and second bit clocks is generated at each supply timing of the L and R channel audio data in the multiplexed digital audio signal, while a stereo signal is generated. In the mode, the first bit clock A clock for each L and R channel audio data supply timing and a second bit clock for each L and R channel audio data supply timing; The data latch signal generating means generates the data latch signal at each supply timing of either the L or R channel audio data.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
In the figure, the same parts as in FIG. 9 are designated by the same reference numerals.
A read RF (high frequency) signal read from a recording medium (not shown) is demodulated by the PCM decoder 1 and output as L, R serial data. The L and R serial data are converted into L and R 2 channel analog signals in the D / A converters 2L and 2R. These analog signals are supplied to the output terminals 7L and 7R via the LPFs 3L and 3R and the buffer amplifiers 4L and 4R and become L and R channel audio outputs. From the PCM decoder 1, as a timing signal for D / A conversion in the D / A converters 2L and 2R, as shown in FIG. 2, a bit clock (b) synchronized with the L and R serial data (a). And a data latch signal (c) is output. The timing control circuit 8A controls the supply timing of the bit clock and data latch signals to the D / A converters 2L and 2R based on the Lch and Rch select signals as the predetermined control signals output from the select signal generating circuit 6. It The Lch and Rch select signals are both low level (hereinafter,
"L"), and Rch in Rch monaural output mode
Only the select signal is high level (hereinafter referred to as "H"), Lc
h Only Lch select signal is "H" in monaural output mode
Becomes

In the timing control circuit 8A, the bit clock is NAND
Each of the circuit 80 and the EX-OR circuit 81 has one input, and the data latch signal has one of the NAND circuit 82 and the EX-OR circuit 83 each input. The NAND circuit 80 receives the output of the NAND circuit 82 as another input, and its output becomes the bit clock input of the D / A converter 2L via the inverter 84. The EX-OR circuit 81 uses the ground level as another input, and its output becomes the bit clock input of the D / A converter 2R. The EX-OR circuit 83 receives the Lch select signal output from the select signal generating circuit 6 as another input, and its output serves as each latch input of the D / A converters 2L and 2R. Lch and Rch select signals
2 inputs of EX-OR circuit 85, and its output is inverter 86
It becomes the other input of the NAND circuit 82 via.

With this configuration, in stereo output mode, Lch,
Since the Rch select signals both become “L”, the data latch signal is directly passed through the EX-OR circuit 83 and the D / A converter 2L,
It becomes each latch input of 2R, while the bit clock is directly supplied to the D / A converter 2R via the EX-OR circuit 81, but to the D / A converter 2L the other input of the NAND circuit 82. Becomes “H”, Rch is generated by the data latch signal.
The supply is stopped during the period when the data is input. Also,
In the Rch, Lch monaural output mode, since the other inputs of the NAND circuit 82 are set to "L" because the levels of the Lch, Rch select signals are different, the bit clock supply period is not controlled by the data latch signal, and the bit clock is not controlled. Is always
It is supplied to D / A converters 2L and 2R, while the data latch signal is Lc.
Only in the Lch monaural output mode in which the h select signal is "H", the phase is inverted, that is, shifted by one sample time and used as the latch input of the D / A converters 2L and 2R.

As a result, in the stereo output mode, the bit clock (b) supplied to the D / A converter 2L is R in FIG.
Stopped in ch data section, Rch1st data is not read and L stored in shift register in D / A converter 2L
Since ch1st data will be output, when the data latch signal (d) falls, the D / A converter 2L to Lch1t
The analog audio signal according to the h data is output and D
The analog audio signal according to the Rch 1st data will be output from the / A converter 2R.

In Rch monaural output mode, the bit clock is always D
It is supplied to the A / A converters 2L and 2R, and in FIG. 4, when the data latch signal (d) falls, the D / A converters 2L and 2R
Since Rch 1st data is read into the shift register for both 2R, analog audio signals conforming to the Rch 1st data will be output from both D / A converters 2L and 2R. On the other hand, in the Lch monaural output mode, the data latch signal (d) is shifted by 1 sample time,
In FIG. 5, at the falling edge of the data latch signal (d), the Lch1st data is read into the shift register in both D / A converters 2L and 2R, so both D / A converters 2L and 2R are read. An analog audio signal based on the Lch 1st data will be output.

In addition, in FIGS. 3 to 5 showing each timing chart in the above-mentioned three-output mode, (a) is a D / A converter 2R.
Is supplied to the D / A converter 2L, (b) is supplied to the D / A converter 2L, (c) is supplied to the L / R serial data, and (d) is supplied to the D / A converters 2L and 2R. Data latch signals are shown respectively.

In this way, when the demodulated digital audio output is voice multiplexed, for example, the output mode of the voice output from the output terminals 7L, 7R (Japanese and foreign language, Japanese only and foreign language only 3 modes) can be switched. By performing the processing at the stage of digital data, there is no adverse effect on the sound quality, so that it is possible to reproduce an audio signal with high sound quality and excellent SN ratio. In the above embodiment, the case where the pair of D / A converters 2L and 2R is used as the D / A converting means has been described. However, the present invention is not limited to the D / A converting means as shown in FIG. It is also applicable when using one D / A converter 2.

In FIG. 6, L / R serial data output from the PCM decoder 1 is converted into an analog signal in the D / A converter 2. From the D / A converter 2, the analog voltages V _L and V _R of the L and R channels are time-divisionally output and supplied to the sample hold circuits 9L and 9R. The sample hold circuit 9L
Resistance R _L , analog switch SW _L , hold capacitor C _L
And a buffer amplifier A _L. The sample hold circuit 9R has the same configuration. Analog switches SW _L and SW _R in this sample and hold circuit 9L and 9R
Is L generated from the PCM decoder 1 in synchronization with the output timing of the analog voltages V _L and V _R output from the D / A converter 2.
On / off control is performed by the ch and Rch sampling pulses. It is needless to say that a deglitcher circuit may be used instead of the analog switches SW _L and SW _R.

From the PCM decoder 1, as a timing signal for D / A conversion in the D / A converter 2, as shown in FIG.
A bit clock (b) synchronized with the R serial data (a), a data latch signal (c) and an L, R clock (d) are output. The bit clock is output from the select signal generation circuit 6 in the timing control circuit 8B.
The supply timing to the D / A converter 2 is controlled based on the Lch and Rch select signals and the L and R clocks. As in the previous embodiment, the Lch and Rch select signals are both "L" in stereo output mode, only Rch select signal is "H" in Rch monaural output mode, and Lch select signal is only in Lch monaural output mode. Becomes “H”.

In the timing control circuit 8B, the bit clock becomes the a input of the 3-input 1-output switch 88 via the inverter 87, and also becomes the direct inputs of the NAND circuits 89 and 90, respectively. On the other hand, the L and R clocks become the other input of the NAND circuit 89 via the inverter 91 and directly become the other input of the NAND circuit 90.
The outputs of the NAND circuits 89 and 90 become the b and c inputs of the switch 88.
The switch 88 selects the a input in the stereo output mode, the b input in the Lch monaural output mode, and the c input in the Rch monaural output mode based on the Lch and Rch select signals from the select signal generation circuit 6.

In such a configuration, in the stereo output mode, the eighth
As shown in FIG. 7A, the bit clock (b) is always supplied to the D / A converter 2 without being restricted by the supply period, so that the L / R serial data is output at the falling edge of the data latch signal (c). (A) is alternately read into the shift register of the D / A converter 2, and the two-channel analog voltages V _L and V _R are output alternately. Further, in the Lch monaural output mode, the NAND circuit 89 becomes “L” in the Lch data section.
Since the bit lock (b) is stopped in the Rch data section as shown in FIG. 8 (B) by being opened only in the Lch data section by the L and R clocks, only the Lch data is D / It is read into the shift register of the A converter 2 and only the Lch analog voltage V _L is continuously output. On the other hand, in the Rch monaural output mode, the NAND circuit 90 is opened only in the Rch data section by the L and R clocks, so that the bit clock (b) is supplied in the Lch data section as shown in FIG. 8 (C). Therefore, only the Rch data is read into the shift register of the D / A converter 2, and only the Rch analog voltage V _R is continuously output.

As a result, in the stereo output mode, the analog voltages V _L and V _R of the two channels are separated by the sample hold circuits 9L and 9R and become the Lch and Rch audio outputs, respectively, and in the Lch monaural output mode, the D / A converter 2 From
Since only the Lch analog voltage V _L is continuously output, the analog voltage V _L becomes the audio output of both channels,
In the Rch monaural output mode, the Rch from the D / A converter 2
Since only the analog voltage V _R is continuously output, the analog voltage V _R becomes the audio output of both channels.

As described above, also in the present embodiment, since the switching of the output mode is performed at the digital data stage, the same effect as in the case of the previous embodiment can be obtained.

As described above, according to the present invention, by switching the output mode at the digital data stage, the mode switching can be performed without inserting a relay or an analog switch that adversely affects sound quality or the like in the audio signal line. Since it can be performed, it is possible to reproduce an audio signal with high sound quality and an excellent SN ratio.

Also, logic circuits will be used instead of relays and analog switches for two channels.
It is easy to reduce the power consumption, and since only one IC is required to be added to the logic circuit, it is possible to reduce the power consumption and the space.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention when a pair of D / A converters is used, and FIG. 2 is the L, R serial data (a), bit clock (b) and Timing chart of data latch signal (c), Fig. 3 is timing chart in stereo output mode, Fig. 4 is Rch
Timing chart in monaural output mode, Fig. 5
Timing chart for Lch monaural output mode, No. 6
FIG. 7 is a block diagram showing another embodiment of the present invention when a single D / A converter is used, and FIG. 7 is L, R serial data (a), bit clock (b), Data latch signal (c) and L, R clock timing chart,
8 is a timing chart in stereo output mode (A), Lch monaural output mode (B), and Rch monaural output mode (C), and FIG. 9 is a timing chart when a pair of D / A converters is used. It is a block diagram which shows a prior art example. Explanation of main part code 1 …… PCM decoder 2,2L, 2R …… D / A converter 8A, 8B …… Timing control circuit 9L, 9R …… Sample hold circuit

Claims (1)

[Claims] 1. A multiplexed digital audio signal obtained by time-division-multiplexing L and R channel audio data is taken in according to a first bit clock, and this is converted into an analog signal in accordance with a data latch signal to obtain an L channel audio. An L channel D / A converter as an output signal, and the multiplexed digital audio signal is taken in according to a second bit clock and converted into an analog signal in accordance with the data latch signal to be an R channel audio output signal. An R channel D / A converter, which generates the first and second bit clocks at each supply timing of the L and R channel audio data in the multiplexed digital audio signal in the monaural mode, while in the stereo mode The first and second bit clocks are the L and R channels. Bit clock generating means for generating the second bit clock at each supply timing of the L and R channel audio data, and generating the second bit clock at each supply timing of the L and R channel audio data. A digital audio circuit, comprising: a data latch signal generating means for generating the data latch signal at each one of the supply timings.