JPH0731914B2 - EEPROM device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an EEPROM (Electrical Erasable
The present invention relates to a programmable read only memory) device, for example, the peripheral circuit thereof is CMOS (complementary MO
S) The present invention relates to a technology effectively used for the one configured by the circuit.

[Conventional technology]

A semiconductor nonvolatile memory element capable of electrically writing and erasing data, such as MNOS (Metal Nitride Oxide Semiconductor), is a relatively thin silicon oxide film and a relatively thick silicon nitride film formed on it ( It is an insulated gate field effect transistor (hereinafter referred to as an MNOS transistor at the end) having a two-layered gate insulating film with a nitride, and can electrically erase not only writing of stored information. MNOS technology is disclosed in
56-156370.

In the erased state or the state in which the stored information is not written, the threshold voltage of the N-channel type MNOS transistor is a negative voltage. For writing or erasing stored information, a high electric field is applied to the gate insulating film so that carriers are injected by a tunnel phenomenon.

According to the above publication, the MNOS transistor is formed in the P-type well region formed in the N-type semiconductor substrate. In addition, the MOSFETs forming the peripheral circuit are formed in the well region independent of the well region for the MNOS transistor.

In the write operation, in the well region as the body gate of the MNOS transistor, for example, the ground potential of 0 V
Is applied, and a high voltage for writing is applied to the gate. A low voltage of about 0 V or a high voltage of the write level is applied to the source region and the drain region depending on the information to be written. At this time, a channel is induced in the channel forming region of the MNOS transistor, that is, in the surface of the silicon region between the source region and the drain region, according to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source region and the drain region.
When the voltage of 0 V is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film by the tunnel phenomenon. As a result, the threshold voltage of MNOS changes from a negative voltage to a positive voltage, for example.

When a write level high voltage is applied to the source region and the drain region, the potential difference between the gate and the channel is set to a small value. Such a small voltage difference is insufficient to cause injection of electrons due to the tunnel phenomenon. Therefore, the threshold voltage of MNOS does not change.

When erasing, 0V is applied to the gate of the MNOS transistor.
While applying a positive high voltage to the well region as the substrate gate, causing a reverse tunneling phenomenon,
This is done by returning electrons as carriers to the substrate gate.

[Problems to be solved by the invention]

In order to reduce the power consumption of the EEPROM device, the present inventors have
We considered using the CMOS (complementary MOS) circuit as the circuit that constitutes the EEPROM device. However, as described above, when a high voltage is applied to the substrate gate for erasing, good operation of the CMOS circuit cannot be expected. That is,
The P-channel MOSFET forming the CMOS circuit is formed on the N-type semiconductor substrate, for example.
The MNOS transistor is formed in the P-type well region formed on the N-type semiconductor substrate. In this case, if a positive high potential is applied to the well region for erasing as in the conventional EEPROM, the PN junction between the well region and the semiconductor substrate is forward-biased according to the high potential. It will be. That is, by setting the well potential to a positive high potential, the semiconductor substrate as the base gate of the P-channel MOSFET is set to a high potential.

In response to this, the P-channel MOSFET does not perform the desired operation at the normal signal level because the effective threshold voltage of the P-channel MOSFET increases due to the substrate effect caused by the high voltage. The forward biased state of the PN junction also activates the parasitic bipolar transistor structure part in the CMOS structure, causing a risk of latch-up operation.

Therefore, prior to the present invention, the inventors of the present invention have made the P-type well region in which the MNOS is formed and the gate electrode and the source / drain regions of the MNOS relatively high negative voltage and relatively low positive power source. It was considered to realize the above write and erase operations by switching to a voltage. By doing so, a positive and relatively low power supply voltage can always be supplied to the N-type semiconductor cutting board, so that the P-channel MOSFET constituting the CMOS circuit can be operated. In this case, in the write operation state, the potential of the selected (bit to be written) data line is set to a negative high voltage. Therefore, the MOSFETs that make up the column switch are
Inevitably, a P-channel MOSFET will be used.
This is because when an N-channel MOSFET is used, the semiconductor region (source or drain) coupled to the data line and the P-type well region in which the column switch MOSFET is formed are set to the ground potential of the circuit, so that the PN junction thereof is formed. Is forward biased. When the column switch circuit is configured by the P-channel MOSFET as described above,
In the read operation, the signal transmission speed becomes slow.

An object of the present invention is to provide an EEPROM device in which the read operation is speeded up while realizing the CMOS circuit as the peripheral circuit.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a well region in which a memory cell including an electrically writable and erasable semiconductor nonvolatile memory element is formed, a well region in which an N-channel MOSFET forming a CMOS circuit is formed, and a P-channel forming a CMOS circuit A MOSFET is formed and is composed of a semiconductor substrate to which a predetermined voltage is constantly supplied, and is inserted in series to the data line of the well region in which the semiconductor nonvolatile memory element is formed. N channel that is supplied with voltage
A MOSFET and an N-channel type column switch MOSFET for selecting the data line are provided in series with the MOSFET.

[Work]

According to the above-mentioned means, the read signal obtained on the data line coupled with the nonvolatile memory element is transferred to the N-channel MOSFET.
Since it can be output through the output, the operation speed can be increased.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of the present invention.

The EEPROM device of this embodiment has an address selection circuit including an address buffer (not shown), an X decoder X-DCR and a Y decoder Y-DCR, and a write / erase operation in response to an output signal or a control signal from the address selection circuit. For forming voltage for control, and control circuit for forming the control signal
Includes CONT.

The EEPROM device is operated by a relatively low power supply voltage Vcc supplied from the outside, such as + 5V, and a negative high voltage −Vpp such as −12V, though not particularly limited thereto. The X address decoder X-DCR and the like which compose the selection circuit are composed of CMOS circuits. The CMOS circuit operates by being supplied with a relatively low power supply voltage Vcc such as + 5V. Therefore, the address decoders X-DCR and Y
-The level of the selection / non-selection signal formed by DCR is
It is set to about +5 V, and the low level is the ground potential of the about circuit.
It is set to 0V.

The element structure itself which constitutes the illustrated EEPROM device is not shown because it is not directly related to the present invention, but its outline is as follows.

That is, the entire illustrated device is formed on a semiconductor substrate made of N-type single crystal silicon. The MNOS transistor is of N-channel type and is formed on a P-type well region or a P-type semiconductor region formed on the surface of the semiconductor substrate. The N-channel MOSFET is similarly formed on the P-type semiconductor region.

The P-channel MOSFET is formed on the semiconductor substrate.

One memory cell is not particularly limited, but one MNOS
It consists of a transistor and two MOSFETs connected in series. One MN in one memory cell
The OS transistor and the two MOSFETs have a so-called stacked gate structure in which, for example, the gate electrodes of the MNOS transistor partially overlap with the gate electrodes of the two MOSFETs. As a result, the size of the memory cell is reduced because the one MNOS transistor and the two MOSFETs forming the memory cell are substantially integrated.

Although not particularly limited, each memory cell is formed in a common well region. CMOS such as X decoder, Y decoder
The N-channel MOSFET for forming the circuit is formed in a P-type well region independent of the common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed on it, and is set to the power supply voltage Vcc level of the circuit. CMOS
The well region as the base gate of the N-channel MOSFET for forming the circuit is maintained at the ground potential of the circuit of 0 volt.

In FIG. 1, the memory array M-ARY includes a plurality of memory cells arranged in a matrix. One memory cell includes an MNOS transistor Q2, an address selection MOSFET Q1 provided between the drain of the MNOS transistor Q2 and a data line (bit line or digit line) D1, and the source of the MNOS transistor Q2, which is not particularly limited. It is composed of an isolation MOSFET Q3 provided between the source line and the source line. In addition, when the stacked gate structure as described above is adopted, the MOSFET is formed in the channel formation region of the MNOS transistor Q2.
The channel forming regions of Q1 and Q3 are directly adjacent to each other. Therefore, the drain of MNOS Transinsta Q2,
Source is to be understood as a term of convenience.

The gates of the address selecting MOSFETs Q1 and the like of the memory cells arranged in the same row are commonly connected to the first word line W11, and the gates of the corresponding MNOS transistors Q2 and the like are common to the second word line W12. It is connected. Similarly, the gates of the memory cell address selecting MOSFET and the MNOS transistor arranged in the same row are commonly connected to the first word lines W21 and W22, respectively.

MOSF for address selection of memory cells arranged in the same column
The drains of the ETQ1 and the like are commonly connected to the data line D1. Similarly, the drains of the address selection MOSFETs of the memory cells arranged in the same column are connected to the data line D2.
Commonly connected to.

The sources of the separation MOSFET Q3 in each memory cell are made common to form a common source line CS.

The memory array M-ARY of this embodiment is operated by the following potentials.

First, in the read operation, the potential Vw of the well region WELL
Is brought to a low level equal to the ground potential of the circuit of 0 volt. The common source line CS is set to a low level that is substantially equal to the ground potential. The control line coupled to the gate of isolation MOSFET Q3 is brought to a high level which is approximately equal to the power supply voltage Vcc so as to turn on these MOSFETs Q3. The second word lines W12 to W22, each of which is coupled to the gate electrode of the MNOS transistor, have a potential approximately equal to the ground potential, that is, a voltage between the high threshold voltage and the low threshold voltage of the MNOS transistor. To be done. The word line to be selected among the first word lines W11 to W21 is
The selected level or high level is set to be approximately equal to the power supply voltage Vcc, and the remaining word lines, that is, unselected word lines are set to the non-selected level or low level, which is approximately equal to the ground potential. A sense current is supplied to the data line to be selected among the data lines D1 and D2. MNOS in the memory cell selected by the first word line
If the transistor has a low threshold voltage, the memory cell forms a current path for the data line to which it is coupled. If the MNOS transistor in the selected memory cell has a high threshold voltage, that memory cell will form substantially no current path. Therefore, the data read from the memory cell is performed by detecting the sense current.

In the write operation, the well area WELL is almost Vpp
The control line coupled to the gate electrode of isolation MOSFET Q3 is brought to a negative high potential to turn off those MOSFETs Q3. The first word lines W11 to W21 are set to the non-selection level or the low level which is almost equal to the ground potential. Second word line W12
One of W22 to W22 has a power supply voltage Vcc.
And the remaining second word line is brought to a negative high voltage near the voltage -Vpp. The data line is set to a high level almost equal to the power supply voltage Vcc or a low level having a negative high voltage close to the negative voltage −Vpp, depending on the data to be written in the memory cell.

In the erase operation, the well region WELL and the common source line CS
Is set to an erase level or a high level that is approximately equal to the power supply voltage Vcc. The first word lines W11 to W21 and the second word lines W12 to W22 are basically set to a level substantially equal to the power supply voltage Vcc of the circuit and a voltage substantially equal to the voltage -Vpp, respectively, for erasing. . However, according to this embodiment, although not particularly limited, the levels of the first and second word lines are determined so that the memory cells in each memory row can be erased. First word line
The first word line corresponding to the memory row of W11 to W21 that needs to be erased is set to an erase level approximately equal to the power supply voltage Vcc, and the first word line corresponding to the memory row that does not need to be erased. One word line is brought to a non-erased level such as the ground potential of a circuit. Second word line W12 or W22
The second word line corresponding to the first word line set to the erase level among the first word line and the first word line set to the non-erase level are set to an erase level substantially equal to the negative voltage −Vpp. The second word line is set to a non-erasing level which is approximately equal to the power supply voltage Vcc.

According to this embodiment, as described above, the stored information in each MNOS transistor is erased by applying the power supply voltage Vcc to the well region, that is, the substrate gate of the MNOS transistor. On the other hand, the body gate of the N-channel MOSFET that constitutes the CMOS circuit needs to be set at a potential such as 0 volt independently of the body gate of the MNOS transistor. Therefore, as described above, the body gate of each memory cell, that is, the semiconductor region WELL in which the memory array M-ARY is formed is a semiconductor in which N-channel MOSFETs forming peripheral circuits such as an X decoder and a Y decoder are formed. It is electrically separated from the region (well region).

If it is desired to partially erase the memory array M-ARY, each memory cell is formed in an independent well region, or memory cells arranged in the same row or column are formed in a common well region. You can In this embodiment, as described above, the entire memory cell, that is, the memory array M-ARY, has one common well region W.
Formed in ELL.

The first and second word lines W11 to W21 and W21 to W22
Are respectively driven by the X decoder X-DCR.
Although not particularly limited, the X decoder X-DCR is composed of a plurality of unit decoder circuits which correspond one-to-one to the memory rows of the memory array M-ARY. One unit decoder circuit is a NOR (NOR) that receives an address signal as shown in the figure.
Gate circuit NOR1, gate circuit G and level conversion circuit LVC
Composed of.

The gate circuit G, at least during the read operation,
The output of the NOR gate circuit corresponding to the
It is configured to be transmitted to the word line and to set the first word line to a level substantially equal to the ground potential of the circuit in the write operation regardless of the power of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G outputs the output of the corresponding NOR gate circuit to the corresponding first word line not only during the read operation but also during the erase operation. Configured to communicate. A concrete circuit example of the gate circuit G will be described later with reference to FIG. 2 together with that of the level return circuit LVC.

When the output of the NOR gate circuit corresponding to the level conversion circuit LVC is at the high selection level during the write operation, the level conversion circuit LVC supplies the second word line with the power supply voltage Vc correspondingly.
If the output of the NOR gate circuit is the low level non-selection level, the second word line is correspondingly brought to the non-selection level substantially equal to the negative voltage -Vpp.
When the output of the NOR gate circuit corresponding to the level conversion circuit LVC is at the high level selection level during the erase operation, the level conversion circuit LVC causes the second word line to respond to the negative voltage -Vp.
When the output of the NOR gate circuit is the low level non-selection level, the second word line is set to the erase non-selection level almost equal to the power supply voltage Vcc.

The gate of the isolation MOSFET Q3 etc. is connected to the control voltage generator Vig−
It is commonly coupled to a control line supplied with a control voltage Vig formed by G. The sources of the separation MOSFET Q3 and the like are made common to form a common source line CS.

The control voltage Vig supplied to the isolation MOSFET Q3 is MNOS.
In the writing operation as described below to the transistor,
Of the second word lines W21 to W22, the word line to which the memory cell to be selected is coupled is set to the high level (5V), the well region WELL as the substrate gate is set to about -12V, and the data line, for example, When D1 is brought to about −10V, it is brought to a low potential such as about −10V so as to turn off the MOSFET Q3. This allows data line D2
Is set to a high level such as + 5V, the data line D2
Therefore, the current is prevented from flowing into the side of the memory cell to be written.

The common source line CS is coupled to the output terminal of the common source line drive circuit DVR.

The drive circuit DVR can basically drive the common source line CS to almost the power supply voltage Vcc level during the erase operation,
Further, it is only necessary that the common source line CS has an output characteristic capable of driving the common source line CS to the ground potential of the circuit during the read operation. Thus, in the erase operation, the well region WELL
Is set to the power supply voltage Vcc level, it is possible to prevent the junction between the electrode coupled to the common source line CS of the MOSFET Q3 and the well region WELL from being forward biased. In addition, the current path required for read operation is
It can be formed between the common source line CS and the ground point of the circuit.

The drive circuit DVR is not particularly limited, but as shown in FIG. 1, a MOSFET Q6 provided between the power supply terminal Vcc of the circuit and the common source line CS, a common source line CS, and a ground point of the circuit. MOSFETs Q7 and Q8 in parallel between, and CMOS
It consists of an inverter circuit IV.

The control signal er is supplied to the gates of the MOSFETs Q7 and Q8, and the control signal er is inverted by the inverter circuit IV and supplied to the gate of the MOSFET Q6. This allows
The MOSFETs Q7, Q8 and Q6 are complementarily turned on / off according to the level of the control signal er. The control signal er is
Basically, it is set to a high level almost equal to the power supply voltage Vcc so as to turn on the MOSFET Q6 during the erase operation and turn on the MOSFETs Q7 and Q8 during the read and write operations. It is brought to a low level equal to 0 volts. According to this embodiment, the control signal er corresponds to the potential change timing of the well region so as to prevent the PN junction formed by the MOSFET and the like formed in the well region WELL from being in the forward bias state. Then, the output timing is controlled.

According to this embodiment, MOSFETs Q4 and Q5 are provided between the second word lines W12 and W22 and the common source line CS, respectively. These MOSFETs Q4 and Q5 have control signals ▲ ▼
Switch controlled by. Although not particularly limited, the control signal ▲ ▼ has its high level set to a level approximately equal to the power supply voltage Vcc and its low level set to a level approximately equal to the ground potential. MOSFET Q4, Q5 is the second
The P-channel type is formed so that the word lines W12 and W22 are favorably turned off even when a negative potential is applied. During the read operation, the switch MOSFETs Q4, Q5, etc. are turned on so that the gates of the MNOS transistor Q2, etc. and the common source line CS are short-circuited to bring them to the same potential. These switch MOSFETs Q4 and Q5 are provided between each second word line and the common source line CS for the following reason.

That is, the MOSFETs Q7 and Q8 in the drive circuit DVR are turned on by setting the control signal er to a low level equal to about 0 volt during the read operation. In this case, the MOSFETs Q7 and Q8 have an on-resistance that cannot be ignored even though they are connected in parallel as shown. As a result, the potential of the common source line CS rises due to the current flowing through it during reading. Especially when the MOSFETs Q7, Q8 are of P-channel type, these MOSFETs Q7, Q8
Does not have the driving ability to change the common source line CS to the ground potential of the circuit, the floating amount of the potential of the common source line CS becomes large. That is, MOSFETs Q7, Q8
Means that the current transfer electrode coupled to the common source line CS therein acts as a source electrode with respect to the positive potential given via the memory array M-ARY and the common source line CS. When CS becomes a potential lower than the respective threshold voltage, it is practically turned off.
Such a rise in the potential of the common source line CS causes an increase in the effective threshold voltage due to the substrate effect of the MNOS transistor, and reduces the conductance of the MNOS transistor that should have a low threshold voltage. In other words, the read current flowing through the MNOS transistor having a low threshold voltage is reduced. The short-circuit MOSFETs Q4 and Q5 make the potentials of the second word lines W12 and W22 substantially equal to the potential of the common source line CS during the read operation, thereby preventing the effective threshold voltage of the MNOS transistor from increasing.

Well region WELL in which the memory array M-ARY is formed
Is supplied with the control voltage Vw-G formed by the control voltage generation circuit Vw-G. This voltage Vw is set to a negative high voltage such as about -12V during the write operation, is set to a potential of about + 5V during the erase operation, and is set to about 0V in other cases.

In this embodiment, in order to speed up the read operation,
Each data line D1, D2 of the memory array M-ARY has a data line
N-channel MOSFETs Q11, Q12 are provided to electrically isolate D1, D2 from the column switch MOSFETs Q9, Q10. That is, the MOSFETs Q11 and Q12 and the N-channel MOSFETs QQ9 and Q10 as the Y gate (column switch) circuit C-SW are connected in series between the data lines D1 and D2 and the common data line CD. It is provided in. The MOSFETs Q11 and Q12 for separating the data line have the same P as the MNOS transistor.
The well region WELL of the mold is formed. These MOSFET Q11,
The control voltage Vc formed by the control voltage generation circuit Vc-G is supplied to the gate of Q12. The control voltage Vc is set to a negative high voltage such as -12V only in the write operation state, and is set to a high level like the power supply voltage Vcc in the other read and erase operation states. As a result, the MOSFETs Q11 and Q12 are turned off in the write operation state. The MOSFETs Q11 and Q12 are
In the erase operation state, the well region WELL is at the power supply voltage Vcc.
It is turned off by setting it to a high level such as. Therefore, the MOSFETs Q11 and Q12 are turned on only in the read operation state. As a result, during the write operation, the MOSFETs Q11, Q12, etc. are turned off, so that the connection point with the column switch MOSFETs Q9, Q10, which will be described later, becomes floating even if the potential of the data line is set to a negative high voltage. It As a result, it is possible to prevent the sources and drains of the switch MOSFETs Q9 and Q10 coupled to the interconnection point and the well region in which they are formed from being forward biased.

MOSFETs Q9 and Q10 that form the column switch circuit C-SW
The output signal of the Y decoder Y-DCR is supplied to the gate of the. Each output of the Y-decoder Y-DCR is set to a selection level which is approximately equal to the power supply voltage Vcc or a non-selection level which is approximately equal to 0 volt during a read operation.

The common data line CD is coupled to the output terminal of the data input circuit DIB forming the input / output circuit IOB and the input terminal of the data output circuit DOB including the sense amplifier SA and the output buffer circuit OBC. The output terminal of the data input circuit and the output terminal of the data output circuit forming the input output circuit IOB are coupled to the external terminal I / O.

Although not particularly limited, according to this embodiment, each data line is
D1 and D2 are provided with a latch circuit FF for holding the previous storage information prior to erasing / writing, and at the time of the write operation, the potential of the data line is selectively made negative according to the storage information of the latch circuit FF. A level conversion circuit LVC for setting the high voltage to Vpp is provided. These enable simultaneous writing of data to a plurality of memory cells coupled to one selected word line.

The control circuit CONT has external terminals ▲ ▼, ▲ ▼, ▲
Chip enable signal, write enable signal, output enable signal and external terminal Vpp supplied to ▼
By receiving the write voltage supplied to the gate circuit G, the gate circuit G and the level conversion circuit
It outputs various control signals for controlling the operation of circuits such as LVC, control voltage generation circuit Vig-G, drive circuit DVR, data input circuit DIB, and data output circuit DOB.

The read operation mode is not particularly limited, but the signals of the external terminals ▲ ▼, ▲ ▼, and ▲ ▼ (hereinafter, signal ▲
(Notated as ▼, ▲ ▼, ▲ ▼), low level, and high level, and the standby operation mode is instructed by the high level of the signal CE. The first write operation mode for writing data in the latch circuit FF of FIG.
The second write operation mode instructed by the low level, low level, high level, and low level of ▼, ▲ ▼, and Vpp is the low level, low level of signals ▲ ▼, ▲ ▼, ▲ ▼, and Vpp. , High level and high level. The erase operation mode is instructed only for a predetermined period when the second write operation mode is instructed.

Various control signals output from the control circuit CONT are output in time series according to this embodiment. The oscillator circuit OSC of FIG. 1 is operated by a power supply voltage Vcc such as +5 volts applied between the external terminal Vcc of the EEPROM device and GND. The oscillator circuit OSC may be controlled to operate only when a write voltage is applied to the terminal Vpp, if necessary for low power consumption of the circuit.

FIG. 2 shows a circuit diagram of an embodiment of the gate circuit G and the level conversion circuit LVC which form a unit circuit of the X decoder X-DCR.

The gate circuit G receives an N-channel MOSFET Q11 for transmitting the output signal of the NOR gate circuit NOR1 to the first word line W11 in accordance with the control signal {circle around (1)}, and a control signal we 'which has an opposite phase to the control signal we'. The first word line W1
It is composed of an N-channel MOSFET Q12 which gives the circuit ground potential to 1. Control signal in the second write operation ▲
▼ 'and we' are respectively a low level of the ground potential and a high level of the power supply voltage Vcc level. At this time, in the first word line W11, the transmission gate MOSFET Q11 is turned off by the low level of the control signal ▲ ▼ ′, and the MOSFET Q12 is turned by the high level of the control signal we ′.
Is turned on so that it is set to the ground potential of the circuit. During erase or read operation, the first word line W11
Control signal ▲ ▼ 'is set to high level,
When we 'is set to low level, transmission gate MOSF
Since the ETQ11 and Q12 are turned on and off, respectively, they are set to a high level or a low level according to the output signal of the NOR gate circuit NOR1. That is, the word line
W11 is high level (5V) if it is in the selected state,
In the non-selected state, it is set to low level (0V).

The level conversion circuit LVC includes P-channel type transmission gate MOSFETs Q13 and Q14, a P-channel type MOSFET Q19, an inverter circuit IV1 and a negative voltage supply circuit VSC as shown in the figure. The output terminal of the NOR gate circuit NOR1 is a P-channel type transmission gate MOSF which receives a control signal ▲ ▼ at its gate.
It is coupled to the second word line W12 through ETQ13. The output terminal of the inverter circuit IV1 receiving the output signal of the NOR gate circuit NOR1 receives the second signal via the P-channel type transmission gate MOSFET Q14 which receives the control signal ert at its gate.
Coupled to word line W12. Negative voltage supply circuit VSC provided between the second word line W12 and the negative voltage terminal −Vpp
Is not particularly limited, but the second word line W1
In order to be able to give a favorable level of negative voltage to 2, the bootstrap capacitor C and the MOSFET
It consists of Q15 to Q18. That is, a diode type P-channel MOSFET Q15 connected between them so as to apply the negative voltage of the negative voltage terminal −Vpp to the word line W12.
Is provided. A P-channel MOSFET Q16 having its gate coupled to the second word line W12 is provided between the negative voltage terminal -Vpp and one electrode of the capacitor C. Between one electrode of the capacitor C and the second word line W12, a diode-type P-channel MOSF oriented so that a current flows from the word line W12 side.
ETQ17 is provided. A P-channel MOSFET Q whose gate is coupled to the second word line W12 is provided between the other electrode of the capacitor C and a terminal φosc to which an oscillation pulse formed by the oscillation circuit OSC of FIG. 1 is applied.
18 are provided. Between the word line W12 and the ground point of the circuit, the control signal ▲ ▼ is received at its gate.
A channel MOSFET Q19 is provided. This word line W
The ground potential of the circuit 12 is applied to the circuit 12 before the level conversion circuit starts the level conversion operation.

The control signal ▲ ▼ applied to the circuit shown in the drawing is temporarily changed from a level of about 5V to a level of about -4V at the start of the erase operation and at the time of writing data to the memory cell. The control signal ▲ ▼ is changed from a level of about 5V to a level of about 0V in the erase operation. The control signal ▲ ▼ changes from the level of about 5V to the timing of the write operation timing to the memory cell.
The level is set to 0V.

The level conversion operation of this embodiment is as follows.

For example, in the erase operation, first the control signal ▲ ▼
Is temporarily set to low level, MOSFETQ1
Since 9 is turned on, the second word line W12 is reset to the ground potential of the circuit. In the erase operation, the control signal ▲ ▼ is set to a high level of about 5V and the MOSFET Q13
Correspondingly remains off. Control signal ▲
▼ indicates a control signal at the start of the erase operation ▲ ▼
In synchronism with the timing when is returned to the high level, the ground potential is set to the low level. At this time, MOSFET Q14
The ON / OFF state of the inverter is determined by the output level of the inverter circuit IV1. For example, NOR gate circuit NOR1
If the selection signal output from the inverter circuit IV1 is set to the low level of the ground potential in response to the selection level being the high level, the corresponding MOSF
ETQ14 is turned off because its gate and source will be at the same potential. In this case, the second word line
W12 maintains the low level in the floating state because the MOSFET Q19 is turned off by the high level of the control signal {circle around ()} and the MOSFET Q14 is turned off.

The second word line in the floating state is a negative voltage supply circuit
It is brought to a negative potential by the operation of VSC. That is, when the second word line W12 is in the floating low level, the oscillation pulse is almost equal to the power supply voltage Vcc.
When it goes to a high level equal to
SFET Q18 is turned on. The MOSFET Q16 provided between the capacitor C and the terminal Vpp is turned on by applying a positive potential to its one electrode via the capacitor C. As a result, the capacitor C is precharged. Next, when the oscillation pulse is brought to the ground potential of the circuit, the capacitor C gives a negative potential to the MOSFETs Q16 and Q17 by the charge pump action. This negative potential turns on MOSFET Q17,
The potential of the second word line is made negative. Next, when the oscillation pulse is set to the high level, the charge amplification is performed on the capacitor C again. In this case, since the gate potential of the MOSFET Q16 is set to a negative potential according to the negative potential of the word line W12, the on state is maintained until one electrode of the capacitor C substantially drops to the level of the word line W12. To do.
In response, capacitor C is precharged with a level greater than the initial precharge level. By repeating the same operation, the negative voltage −Vpp above is about 12V.
If it is a negative high voltage such as, the potential of the second word line W12 is lowered to a low potential of about −10V. In addition, in response to the voltage loss corresponding to the threshold voltage of the diode type MOSFETs Q17 and Q16, the negative voltage Vpp
Is -12V, the potential of the word line W12 is -10V. On the other hand, if a low level non-selection level signal is sent from the NOR gate circuit NOR1, the MOSFET Q1
4 is turned on in response to a high level signal supplied from the inverter circuit IV1. In response to this, the high level signal of the inverter circuit IV1 is transmitted to the word line W12 via the MOSFET Q14. Here, in the circuit of FIG. 2, the driving capability of the second word line W12 by the MOSFET Q14 is
It is made stronger than that of the voltage supply circuit VSC. Therefore, M
If the OSFET Q14 is turned on as described above, the potential of the second word line W12 is set to a high level such as about 5V.

Further, in the operation of writing data to the memory cell, the control signal {circle over ()} is temporarily set to low level, and in response to this, the second word line W12 is reset to the ground potential of the circuit. The control signal ▲ ▼ is the control signal ▲ ▼
Is switched from a high level of about 5V to a low level equal to about 0V substantially in synchronism with the timing when is returned to a high level. At this time, if the output of the NOR gate circuit NOR1 is at the high level selection level, the MOSFET Q13 is accordingly turned on. In this way, when the high-level selection signal is sent from the NOR gate circuit NOR1, the potential of the second word line W12 is set to a high level such as about 5V, contrary to the erase operation. On the other hand, if the NOR gate circuit NOR1 sends a rowberel non-selection signal, the MOSF
ETQ13 remains off. In this case, the potential of the second word line W12 is set to -10V by the same operation as that of the voltage level conversion circuit described above.

FIG. 3 shows a circuit diagram of an embodiment of the control voltage generating circuit Vc-G for the data line separating MOSFETs Q11 and Q12.

The control voltage generator Vc-G has its source,
A drain is coupled to the power supply terminal Vcc and the output terminal, and a P-channel MOSFEQ20 having its gate receiving the control signal we ', its drain and source being coupled to the output terminal and the ground point of the circuit and receiving the control signal ▲ ▼ at its gate It is composed of a channel MOSFET Q21, a negative voltage supply circuit VSC and a P channel MOSFEQ22 which receives a control signal we 'at its gate.

The control signal we ′ is used when the MOSFET Q20
Is brought to a low level of approximately 0V to turn on. As a result, the control voltage Vc is maintained at a high level almost equal to the power supply voltage Vcc except in the write operation.

Control signal ▲ ▼ indicates that MOSFET Q21
Is set to a low level that temporarily turns on. The MOSFET Q20 is turned off by setting the control signal we 'to a high level during the write operation. Therefore, at the start of writing, the control voltage Vc is set to the floating low level. In this state, the control voltage Vc is the negative voltage supply circuit VSC.
Determines its level. Control voltage generator Vc
The negative voltage supply circuit VSC at -G has a configuration similar to that of FIG. The oscillation pulse OSC required for the operation of the negative voltage supply circuit VSC is the write control signal ▲
▼ 'It is supplied to it via a P-channel type transmission gate MOSFET Q22 which is switch-controlled by a low level.

The control voltage generation circuit Vig-G that forms the control voltage Vig supplied to the gate of the separation MOSFET Q3 of the memory cell and the control voltage generation circuit Vw-G that forms the control voltage Vw supplied to the well region WELL are The circuit is similar to the circuit shown in FIG. 3 except that the control signals are different.

The outline of the operation of this embodiment circuit will be described below with reference to the main timing chart shown in FIG.

In this embodiment, when the write operation is instructed, the stored information of all the memory cells coupled to the word line by being addressed prior to the write operation is once read out to the latch circuits FF shown in FIG. Retained. That is, the potential of the well region WELL in which the MNOS transistor is formed is set to the ground potential 0V of the circuit, and the potential of the data line D1 and the like is set to the level according to the read signal. At this time, the control voltage Vc is set to a high level like the power supply voltage Vcc.
As a result, the MOSFETs Q11 and Q12 are turned on, and the data signal supplied from the external terminal is taken in by the latch circuit corresponding to the data line D1 or the like of the memory cell to be written. Although not shown, when rewriting all bits to the memory cells coupled to the word line, the Y address is sequentially switched to correspond to the write signals of a plurality of bits supplied from the external terminals. Latch circuits are sequentially loaded.

After this, MNOS connected to the above word line as described later.
The erase operation of the transistor is performed. That is, the potential of the well region WELL is set to a high level such as the power supply voltage Vcc, and the potential of the second word line to which the gate of the MNOS transistor is coupled is set to a negative high voltage such as -Vpp. At this time, the control voltage Vc is set to the high level as described above, but the MOSFETs Q11 and Q12 are turned off by the high level of the well region WELL in which it is formed.

Then, according to the information of the latch circuit FF, the write operation is simultaneously performed on the memory cells for one word line. At this time, the potential of the well region WELL and the potential of the data line D1 corresponding to the data to be written are set to a negative high voltage. In synchronization with this, the control voltage Vc is also set to a negative high voltage, so that the data line separation MOSFETs Q11, Q12
Etc. are all turned off. As a result, it is possible to prevent the PN junction between the semiconductor region on the data line side of the column switches MOSFTQ9, Q12 and the like and the well region in which it is formed from being forward biased by the negative high voltage. By the above time-series operation, the EEPROM of this embodiment can perform the same write operation as the static RAM from the outside.

(1) By providing an N-channel MOSFET for separating the data line from the column switch MOSFET in the well region where the MNOS transistor is formed, and supplying the same negative high voltage as the well potential to the gate during the write operation, Turn off the isolation MOSFET. As a result, the column switch MOSFET can be configured by the N-channel MOSFET, so that the read signal appearing on the data line at the time of the read operation is output through the N-channel MOSFET, whereby the operation speed can be increased.

(2) According to the above (1), the column switch MOSFET can be controlled by a low level such as the power supply voltage Vcc or the ground potential of the circuit, so that the Y decoder circuit can be simplified and the operation speed can be increased. To be

(3) The signal of the data line according to the on / off state of the MNOS transistor has a relatively large conductance N
Since the output can be performed through the channel MOSFET, there is an effect that the operation margin can be improved.

(4) By using a negative high voltage, the potential of the semiconductor substrate is fixed to a predetermined voltage such as a positive power supply voltage,
Writing and erasing of the MNOS transistor can be performed. Therefore, the P-channel MOSFET operated by the signal level such as the power supply voltage and the ground potential of the circuit can be formed on the semiconductor substrate, and the peripheral circuits such as the address decoder and the address buffer can be formed by the CMOS circuit. As a result, low power consumption and high speed operation can be achieved by the CMOS circuit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. The erase operation and the write operation may be continuously and automatically executed based on a control signal supplied from an external terminal by providing an appropriate sequence circuit in the control circuit CONT. Also, the MOSFET Q3 for separation of each memory cell is omitted,
The source of the MNOS transistor may be connected to the reference potential line. In this case, the reference potential line is set in a floating state during the write operation, and the ground potential of the circuit is applied during the read and erase operations.

Further, the X-decoder, the latch circuit, and the voltage supply circuit that selectively supplies the high negative voltage by the control signal may have any specific circuit configuration.

In this invention, the peripheral circuit is composed of a CMOS circuit.
It can be widely used for EEPROM devices.

〔The invention's effect〕

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, N-channel MOSFE for separation on the data line
The column switch MOSFET is provided with an N-channel MO by setting it and turning it off during the write operation.
It can be composed of SFET. As a result, the read signal of the memory cell can be output through the N-channel MOSFET, so that the read operation can be speeded up.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of an essential part of an EEPROM device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of its X decoder and level conversion circuit, and FIG. FIG. 4 is a circuit diagram showing an example of a control voltage generation circuit supplied to a power MOSFET, and FIG. 4 is a timing diagram showing an example of the operation of the EEPROM device. M-ARY ... Memory array, X-DCR ... X decoder, Y
-DCR: Y decoder, LVC: Level conversion circuit, G:
… Gate circuit, DRV …… Drive circuit, FF …… Latch circuit, V
c-G, Vig-G, Vw-G ... Control voltage generator, VSC ... Negative voltage supply circuit, SA ... Sense amplifier, C-SW ... Column switch circuit, OSC ... Oscillation circuit, DIB ... Data input circuit, DOB ... Data output circuit, OBC ... Output buffer, WE
LL ... well area, CONT ... control circuit,

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuyuki Sato 1448, Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hitachi Ultra ESI Engineering Co., Ltd. 1448 Hitachi Ultra EPS Engineering Co., Ltd. (72) Inventor Yasunori Ikeda 1448 Kamimizuhonmachi, Kodaira-shi, Tokyo (48) Hitachi Ultra EPS Engineering Co., Ltd. (72) Kazunori Furusawa Tokyo 1450, Josuihonmachi, Kodaira-shi, Tokyo Inside the Hitachi, Ltd. Musashi factory

Claims (2)

[Claims] 1. A well region in which a memory cell including an electrically writable and erasable semiconductor nonvolatile memory element is formed, a P-type well region in which an N-channel MOSFET forming a CMOS circuit is formed, and A P-channel MOSFET forming a well region and a CMOS circuit is formed, and a semiconductor substrate to which a predetermined voltage is constantly supplied and a well region in which the semiconductor nonvolatile memory element is formed are formed, and the memory element is coupled. And an N-channel MOSFET that is inserted in series with the data line and is supplied with substantially the same voltage as the well region during the write operation, and an N-channel type MOSFET that is connected in series to this MOSFET and performs the data line selecting operation. An EEPROM including a column switch MOSFET and capable of writing and erasing data to and from a memory cell by the predetermined voltage and a high voltage having a polarity opposite to the predetermined voltage. Location. 2. The semiconductor non-volatile memory element comprises an MNOS transistor, and a memory cell shows a relationship between a gate electrode of the MNOS transistor supplied for writing / erasing operation of the MNOS transistor, a substrate gate and a drain voltage thereof. A patent is characterized in that a PN junction between a formed well region and a semiconductor region to which a data line to which a memory cell in the well region is coupled is changed with a time lag so as to maintain a reverse bias state. The EEPROM device according to claim 1.