JPH0799634B2 - EEPROM device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an EEPROM (Electrical Erasable
The present invention relates to a programmable read only eye) device, for example, a technique effective when it is used for a peripheral circuit of which is composed of a CMOS (complementary MOS) circuit.

[Background technology]

A semiconductor nonvolatile memory element capable of electrically writing and erasing data, for example, MNOS (Metal Nitride Oyside Semiconductor), is a relatively thin silicon oxide film and a relatively thick silicon nitride film formed on it ( It is an insulated gate field effect transistor (hereinafter, simply referred to as MNOS transistor) having a two-layered gate insulating film with a nitride, and can electrically erase not only writing of stored information. MNOS technology is disclosed in
56-156370.

In the erased state or the state in which the stored information is not written, the threshold voltage of the N-channel type MNOS transistor is a negative voltage. For writing or erasing stored information, a high electric field is applied to the gate insulating film so that carriers are injected by a tunnel phenomenon.

According to the above publication, the MNOS transistor is formed in the P-type well region formed in the N-type semiconductor substrate. Further, the MOSFETs forming the peripheral circuit are formed in the well region independent of the well region for the MNOS transistor.

In the write operation, in the well region as the body gate of the MNOS transistor, for example, the ground potential of 0 V
Is applied, and a high voltage for writing is applied to the gate. A low voltage of about 0 V or a high voltage of the write level is applied to the source region and the drain region depending on the information to be written. At this time, a channel is induced in the channel forming region of the MNOS transistor, that is, in the surface of the silicon region between the source region and the drain region, according to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source region and the drain region.
When the voltage of 0 V is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film by the tunnel phenomenon. As a result, the threshold voltage of MNOS changes from a negative voltage to a positive voltage, for example.

When a write level high voltage is applied to the source region and the drain region, the potential difference between the gate and the channel is set to a small value. Such a small voltage difference is insufficient to cause injection of electrons due to the tunnel phenomenon. Therefore, the threshold voltage of MNOS does not change.

When erasing, 0V is applied to the gate of the MNOS transistor.
By applying a positive high electric field to the well region serving as the substrate gate while giving an electric field, and causing a tunneling phenomenon in the opposite direction to return electrons as carriers to the substrate gate.

In order to reduce the power consumption of the EEPROM device, the present inventors have
We considered using the CMOS (complementary MOS) circuit as the circuit that constitutes the EEPROM device. However, as described above, when a high voltage is applied to the substrate gate for erasing, good operation of the CMOS circuit cannot be expected. That is,
The P-channel MOSFET forming the CMOS circuit is formed on the N-type semiconductor substrate, for example.
The MNOS transistor is formed in the P-type well region formed on the N-type semiconductor substrate. In this case, if a positive high potential is applied to the well region for erasing as described above, the PN junction between the well region and the semiconductor substrate is set in the forward bias state according to the high potential. Become. That is, by setting the well potential to a positive high potential,
The semiconductor substrate as the base gate of the P-channel MOSFET is set to a high potential. In response to this, the effective threshold voltage of the P-channel MOSFET increases due to the substrate effect caused by the high voltage.
At the normal signal level, the desired behavior is lost. The forward biased state of the PN junction also activates the parasitic bipolar transistor structure part in the CMOS structure, causing a risk of latch-up operation.

[Object of the Invention]

One object of the present invention is to realize an EEPROM having a CMOS circuit.
To provide a device.

Another object of the present invention is to provide an EEPROM device which facilitates control of its write operation.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

It is composed of an address selection MOSFET and an isolation MOSFET which are connected by a stacked gate structure in which a part of each gate electrode is overlapped with an electrically writable and erasable semiconductor nonvolatile memory element sandwiched therebetween. A plurality of memory cells are formed in the first P-type well region to form a second N-channel MOSFET forming a CMOS circuit.
P-channel type MOSFET which is formed in the P-type well region and constitutes the first and second P-type well regions and the CMOS circuit.
Power supply voltage is steadily supplied to the N-type semiconductor substrate and the gates of the address selection MOSFETs of the memory cells arranged in the same row are connected to the first word line and arranged in the same row. Address selection MOSFETs of the memory cells arranged in the same column, the control gates of the non-volatile memory elements of the memory cells being connected to the second word line and arranged so as to be orthogonal to the first word line and the second word line. A data line is connected to the drain of the isolation MOSFET, a control line is connected to the gate of the isolation MOSFET, and the source of the isolation MOSFET is connected to a common source line to form a memory array. A negative voltage supply circuit is provided for extracting the first P-type well region to a negative high voltage stepwise by a charge pump circuit according to each operation mode, and a second word line is provided during a write operation. When A power supply voltage and a negative high voltage are applied to the first P-type well region, and a negative high voltage and a power are applied between the second word line and the first P-type well region during the erase operation. A voltage is applied to generate a tunnel current between the non-volatile memory element and its channel region so that writing and erasing can be performed, and the first P Potential of the data line connected to the drain of the address selection MOSFET and the common source line connected to the source of the isolation MOSFET formed in the well region and the potential of the control line to turn off the isolation MOSFET. Of the potential change at each node in these operation modes, the first P-type well region is changed from the circuit ground potential to the power supply voltage, and the power supply voltage is changed to the circuit ground potential. To perform from the first.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of the present invention.

The EEPROM device of this embodiment has an address selection circuit including an address buffer (not shown), an X decoder X-DCR and a Y decoder Y-DCR, and a write / erase operation in response to an output signal or a control signal from the address selection circuit. For forming voltage for control, and control circuit for forming the control signal
Includes CONT.

The EEPROM device is operated by a relatively low power supply voltage Vcc supplied from the outside, such as + 5V, and a negative high voltage −Vpp such as −12V, though not particularly limited thereto. The X address decoder X-DCR and the like which compose the selection circuit are composed of CMOS circuits. The CMOS circuit operates by being supplied with a relatively low power supply voltage Vcc such as + 5V. Therefore, the address decoders X-DCR and Y
-The level of the selection / non-selection signal formed by DCR is
It is set to about +5 V, and the low level is the ground potential of the about circuit.
It is set to 0V.

The element structure itself which constitutes the illustrated EEPROM device is not shown because it is not directly related to the present invention, but its outline is as follows.

That is, the entire illustrated device is formed on a semiconductor substrate made of N-type single crystal silicon. The MNOS transistor is of N-channel type and is formed on a P-type well region or a P-type semiconductor region formed on the surface of the semiconductor substrate. The N-channel MOSFET is similarly formed on the P-type semiconductor region.

The P-channel MOSFET is formed on the semiconductor substrate.

One memory cell is not particularly limited, but one MNOS
It consists of a transistor and two MOSFETs connected in series. One MN in one memory cell
The OS transistor and the two MOSFETs have a so-called stacked gate structure in which, for example, the gate electrodes of the MNOS transistor partially overlap with the gate electrodes of the two MOSFETs. As a result, the size of the memory cell is reduced because the one MNOS transistor and the two MOSFETs forming the memory cell are substantially integrated.

Although not particularly limited, each memory cell is formed in a common well region. CMOS such as X decoder, Y decoder
The N-channel MOSFET for forming the circuit is formed in a P-type well region independent of the common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed on it, and is set to the power supply voltage Vcc level of the circuit. CMOS
The well region as the base gate of the N-channel MOSFET for forming the circuit is maintained at the ground potential of the circuit of 0 volt.

In FIG. 1, the memory array M-ARY includes a plurality of memory cells arranged in a matrix. One memory cell includes an MNOS transistor Q2, an address selection MOSFET Q1 provided between the drain of the MNOS transistor Q2 and a data line (bit line or digit line) D1, and the source of the MNOS transistor Q2, which is not particularly limited. It is composed of an isolation MOSFET Q3 provided between the source line and the source line. In addition, when the stacked gate structure as described above is adopted, the MOSFET is formed in the channel formation region of the MNOS transistor Q2.
The channel forming regions of Q1 and Q3 are directly adjacent to each other. Therefore, the drain and source of the MNOS transistor Q2 should be understood as terms for convenience.

The gates of the address selecting MOSFETs Q1 and the like of the memory cells arranged in the same row are commonly connected to the first word line W11, and the gates of the corresponding MNOS transistors Q2 and the like are common to the second word line W12. It is connected. Similarly for selecting memory cell addresses arranged in the same row
The gates of the MOSFET and the MNOS transistor are commonly connected to the first word lines W21 and W22, respectively.

MOSF for address selection of memory cells arranged in the same column
The drains of ETQ1 and the like are commonly connected to the data line D1. Similarly, the drains of the address selecting MOSFETs of the memory cells arranged in the same column are commonly connected to the data line D2.

The sources of the separation MOSFET Q3 in each memory cell are made common to form a common source line CS.

The memory array M-ARY of this embodiment will be operated by the following potentials, as will be apparent from the description below.

First, in the read operation, the potential Vw of the well region WELL
Is brought to a low level equal to the ground potential of the circuit of 0 volt. The common source line CS is set to a low level that is substantially equal to the ground potential. The control line coupled to the gate of isolation MOSFET Q3 is brought to a high level which is approximately equal to the power supply voltage Vcc so as to turn on these MOSFETs Q3. The second word lines W12 to W22, each of which is coupled to the gate electrode of the MNOS transistor, have a potential approximately equal to the ground potential, that is, a voltage between the high threshold voltage and the low threshold voltage of the MNOS transistor. To be done. The word line to be selected among the first word lines W11 to W21 is
The selected level or high level is set to be approximately equal to the power supply voltage Vcc, and the remaining word lines, that is, unselected word lines are set to the non-selected level or low level, which is approximately equal to the ground potential. A sense current is supplied to the data line to be selected among the data lines D1 and D2. MNOS in the memory cell selected by the first word line
If the transistor has a low threshold voltage, the memory cell forms a current path for the data line to which it is coupled. If the MNOS transistor in the selected memory cell has a high threshold voltage, that memory cell will form substantially no current path. Therefore, the data read from the memory cell is performed by detecting the sense current.

In the write operation, the well area WELL is almost Vpp
The control line coupled to the gate electrode of isolation MOSFET Q3 is brought to a negative high potential to turn off those MOSFETs Q3. The first word lines W11 to W21 are set to the non-selection level or the low level which is almost equal to the ground potential. Second word line W12
One of W22 to W22 has a power supply voltage Vcc.
And the remaining second word line is brought to a negative high voltage near the voltage -Vpp. The data line is set to a high level almost equal to the power supply voltage Vcc or a low level having a negative high voltage close to the negative voltage −Vpp, depending on the data to be written in the memory cell.

In the erase operation, the well region WELL and the common source line CS
Is set to an erase level or a high level that is approximately equal to the power supply voltage Vcc. The first word lines W11 to W21 and the second word lines W12 to W22 are basically set to a level substantially equal to the power supply voltage Vcc of the circuit and a voltage substantially equal to the voltage -Vpp, respectively, for erasing. It However, according to this embodiment, although not particularly limited, the levels of the first and second word lines are determined so that the memory cells in each memory row can be erased. First word line
The first word line corresponding to the memory row of W11 to W21 that needs to be erased is set to an erase level approximately equal to the power supply voltage Vcc, and the first word line corresponding to the memory row that does not need to be erased. One word line is brought to a non-erased level such as the ground potential of a circuit. Second word line W12 or W22
The second word line corresponding to the first word line set to the erase level among the first word line and the first word line set to the non-erase level are set to an erase level substantially equal to the negative voltage −Vpp. The second word line is set to a non-erasing level which is approximately equal to the power supply voltage Vcc.

According to this embodiment, as described above, the stored information in each MNOS transistor is erased by applying the power supply voltage Vcc to the well region, that is, the substrate gate of the MNOS transistor. On the other hand, the body gate of the N-channel MOSFET that constitutes the CMOS circuit needs to be set at a potential such as 0 volt independently of the body gate of the MNOS transistor. Therefore, as described above, the substrate gate of each memory cell, that is, the semiconductor region WELL in which the memory array M-ARY is formed is a semiconductor region in which N-channel MOSFETs forming peripheral circuits such as an X decoder and a Y decoder are formed. It is electrically separated from the (well region).

If it is desired to partially erase the memory array M-ARY, each memory cell is formed in an independent well region, or memory cells arranged in the same row or column are formed in a common well region. You can In this embodiment, as described above, the entire memory cell, that is, the memory array M-ARY, has one common well region W.
Formed in ELL.

The first and second word lines W11 to W21 and W12 to W22
Are respectively driven by the X decoder X-DCR.
Although not particularly limited, the X decoder X-DCR is composed of a plurality of unit decoder circuits which correspond one-to-one to the memory rows of the memory array M-ARY. One unit decoder circuit is a NOR (NOR) that receives an address signal as shown in the figure.
Gate circuit NOR1, gate circuit G and level conversion circuit LVC
Composed of.

The gate circuit G, at least during the read operation,
The output of the NOR gate circuit corresponding to the
The first word line is transmitted to the word line, and the first word line is set to a level substantially equal to the ground potential of the circuit in the write operation regardless of the output of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G outputs the output of the corresponding NOR gate circuit to the corresponding first word line not only during the read operation but also during the erase operation. Configured to communicate. A concrete circuit example of the gate circuit G will be described later with reference to FIG. 2 together with that of the level conversion circuit LVC.

When the output of the NOR gate circuit corresponding to the level conversion circuit LVC is at the high selection level during the write operation, the level conversion circuit LVC supplies the second word line with the power supply voltage Vc correspondingly.
If the output of the NOR gate circuit is the low level non-selection level, the second word line is correspondingly brought to the non-selection level substantially equal to the negative voltage -Vpp.
When the output of the NOR gate circuit corresponding to the level conversion circuit LVC is at the high level selection level during the erase operation, the level conversion circuit LVC causes the second word line to respond to the negative voltage -Vp.
When the output of the NOR gate circuit is the low level non-selection level, the second word line is set to the erase non-selection level almost equal to the power supply voltage Vcc.

The gate of the isolation MOSFET Q3 etc. is connected to the control voltage generator Vig−
It is commonly coupled to a control line supplied with a control voltage Vig formed by G. The sources of the separation MOSFET Q3 and the like are made common to form a common source line CS.
The control voltage Vig supplied to the isolation MOSFET Q3 is MNOS.
In the writing operation as described below to the transistor,
Of the second word lines W21 to W22, the word line to which the memory cell to be selected is coupled is set to the high level (5V), the well region WELL as the substrate gate is set to about -12V, and the data line, for example, When D1 is brought to about −10V, it is brought to a low potential such as about −10V so as to turn off the MOSFET Q3. This allows data line D2
Is set to a high level such as + 5V, the data line D2
Therefore, the current is prevented from flowing into the side of the memory cell to be written.

The common source line CS is coupled to the output terminal of the common source line drive circuit DVR.

The drive circuit DVR can basically drive the common source line CS to almost the power supply voltage Vcc level during the erase operation,
Further, it is only necessary that the common source line CS has an output characteristic capable of driving the common source line CS to the ground potential of the circuit during the read operation. Thus, in the erase operation, the well region WELL
Is set to the power supply voltage Vcc level, it is possible to prevent the junction between the electrode coupled to the common source line CS of the MOSFET Q3 and the well region WELL from being forward biased. In addition, the current path required for read operation is
It can be formed between the common source line CS and the ground point of the circuit.

The drive circuit DVR is not particularly limited, but as shown in FIG. 1, a MOSFET Q6 provided between the power supply terminal Vcc of the circuit and the common source line CS, a common source line CS, and a ground point of the circuit. MOSFETs Q7 and Q8 in parallel between, and CMOS
It consists of an inverter circuit 1V.

The control signal er is supplied to the gates of the MOSFETs Q7 and Q8, and the control signal er is inverted by the inverter circuit IV and supplied to the gate of the MOSFET Q6. This allows
The MOSFETs Q7, Q8 and Q6 are complementarily turned on / off according to the level of the control signal er. The control signal er is
Basically, it is set to a high level almost equal to the power supply voltage Vcc so as to turn on the MOSFET Q6 during the erase operation and turn off the MOSFETs Q7 and Q8, and during the read and write operations, it is almost at a high level. It is brought to a low level equal to 0 volts. According to this embodiment, the control signal er corresponds to the potential change timing of the well region so as to prevent the PN junction formed by the MOSFET and the like formed in the well region WELL from being in the forward bias state. Then, the output timing is controlled. The timing chart of the control signal er will be described in detail later with reference to FIG.

According to this embodiment, MOSFETs Q4 and Q5 are provided between the second word lines W12 and W22 and the common source line CS, respectively. These MOSFETs Q4 and Q5 have control signals ▲ ▼
Switch controlled by. Although not particularly limited, the control signal ▲ ▼ has its high level set to a level approximately equal to the power supply voltage Vcc and its low level set to a level approximately equal to the ground potential. MOSFET Q4, Q5 is the second
The P-channel type is formed so that the word lines W12 and W22 are favorably turned off even when a negative potential is applied. The switch MOSFETs Q4, Q5, etc.
The gates of the transistors Q2 and the like and the common source line CS are short-circuited to turn them on so that they have the same potential. These switch MOSFETs Q4 and Q5 are provided between each second word line and the common source line CS for the following reason.

That is, the MOSFETs Q7 and Q8 in the drive circuit DVR are turned on by setting the control signal er to a low level equal to about 0 volt during the read operation. In this case, the MOSFETs Q7 and Q8 have an on-resistance that cannot be ignored even though they are connected in parallel as shown. As a result, the potential of the common source line CS rises due to the current flowing through it during reading. Especially when the MOSFETs Q7, Q8 are of P-channel type, these MOSFETs Q7, Q8
Does not have the driving ability to change the common source line CS to the ground potential of the circuit, the floating amount of the potential of the common source line CS becomes large. That is, MOSFETs Q7, Q8
Means that the current transfer electrode coupled to the common source line CS therein acts as a source electrode with respect to the positive potential given via the memory array M-ARY and the common source line CS. When CS becomes a potential lower than the respective threshold voltage, it is practically turned off.
Such a rise in the potential of the common source line CS causes an increase in the effective threshold voltage due to the substrate effect of the MNOS transistor, and reduces the conductance of the MNOS transistor that should have a low threshold voltage. In other words, the read current flowing through the MNOS transistor having a low threshold voltage is reduced. The short-circuit MOSFETs Q4 and Q5 make the potentials of the second word lines W12 and W22 substantially equal to the potential of the common source line CS during the read operation, thereby preventing the effective threshold voltage of the MNOS transistor from increasing.

Well region WELL in which the memory array M-ARY is formed
Is supplied with the control voltage Vw-G formed by the control voltage generation circuit Vw-G. This voltage Vw is set to a negative high voltage such as about -12V during the write operation, is set to a potential of about + 5V during the erase operation, and is set to about 0V in other cases.

Common data line with each data line D1, D2 of memory array M-ARY
Switch MOSFETs Q9 and Q1 as Y gate circuit between CD
0 etc. are provided. The output signals of the Y decoder Y-DCR are supplied to the gates of these MOSFETs Q9 and Q10. Y
Each output of the decoder Y-DCR has a selection level which is approximately equal to the power supply voltage Vcc or approximately 0 during a read operation.
Unselected level equal to Volts. Each output of the Y decoder Y-DCR is a switch MOSFET when a negative voltage is applied to each data line according to write data.
The data line is brought to a level substantially equal to the negative voltage −Vpp in synchronization with the timing of bringing the data line to a negative potential so as to turn off Q9 to Q10.

The common data line CD is coupled to the output terminal of the data input circuit DIB forming the input / output circuit IOB and the input terminal of the data output circuit DOB including the sense amplifier SA and the output buffer circuit OBC. The input terminal of the data input circuit and the output terminal of the data output circuit forming the input output circuit IOB are coupled to the external terminal I / O.

Although not particularly limited, according to this embodiment, each data line is
D1 and D2 are provided with a latch circuit FF for holding the previous storage information prior to erasing / writing, and at the time of the write operation, the potential of the data line is selectively made negative according to the storage information of the latch circuit FF. A level conversion circuit LVC for setting the high voltage to Vpp is provided. These enable simultaneous writing of data to a plurality of memory cells coupled to one selected word line.

The control circuit CONT has external terminals ▲ ▼, ▲ ▼, ▲
Chip enable signal, write enable signal, output enable signal and external terminal -Vp supplied to ▲
By receiving the write voltage supplied to p, various operation modes are discriminated, and the gate circuit G, the level conversion circuit LVC, the control voltage generation circuit Vig-G, the drive circuit DVR, the data input circuit DIB, the data signal circuit DOB. It outputs various control signals for controlling the operation of the circuit such as.

The read operation mode is not particularly limited, but the signals of the external terminals ▲ ▼, ▲ ▼, and ▲ ▼ (hereinafter, signal ▲
(Notated as ▼, ▲ ▼, ▲ ▼), low level, and high level, and the standby operation mode is instructed by the high level of the signal ▲ ▼. The first write operation mode for writing data in the latch circuit FF of FIG.
Instructed by ▼, ▲ ▼, ▲ ▼ and Vpp low level, low level, high level and low level,
The second write operation mode for writing the data in the memory cell includes signals ▲ ▼, ▲ ▼, ▲ ▼ and
Instructed by Vpp low level, low level, high level, and high level. The erase operation mode is instructed only for a predetermined period when the second write operation mode is instructed.

Various control signals output from the control circuit CONT are output in time series according to this embodiment. The details will be clarified later by the operation description using the timing chart of FIG.

The oscillator circuit OSC in Fig. 1 is the external terminal Vcc and GN of the EEPROM device.
It is operated by a power supply voltage Vcc such as +5 volts applied to D. The oscillator circuit OSC may be controlled to operate only when a write voltage is applied to the terminal Vpp, if necessary for low power consumption of the circuit.

FIG. 2 shows a circuit diagram of an embodiment of the gate circuit G and the level conversion circuit LVC which form a unit circuit of the X decoder X-DCR.

The gate circuit G receives an N-channel MOSFET Q11 which transmits the output signal of the NOR gate circuit NOR1 to the first word line W11 in accordance with the control signal ▲ ▼, and a control signal we 'which is in anti-phase with the control signal ▲ ▼'. N-channel MOSFET Q12 that applies the ground potential of the circuit to the first word line W11
It is composed of In the second write operation, the control signals {circle around ()} and we` are approximately low level of ground potential and high level of approximately power supply voltage Vcc, respectively. At this time, the first word line W11 receives the control signal ▲ ▼ '
The transmission gate MOSFET Q11 is turned off by the low level of, and the MOSFET is turned on by the high level of the control signal we ′.
Since Q12 is turned on, it is set to the circuit ground potential. First word line during erase or read operation
In W11, the control signal ▲ ▼ 'is set to high level,
In addition, by setting we ′ to the low level, the transmission gate
Since the MOSFETs Q11 and Q12 are turned on and off, respectively, they are set to a high level or a low level according to the output signal of the NOR gate circuit NOR1. That is, the word line W11 is set to the high level (5V) when it is in the selected state, and is set to the low level (0V) when it is in the non-selected state.

The level conversion circuit LVC includes P-channel type transmission gate MOSFETs Q13 and Q14, a P-channel type MOSFET Q19, an inverter circuit IV1 and a negative voltage supply circuit VSC as shown in the figure. The output terminal of the NOR gate circuit NOR1 is a P-channel type transmission gate MOSF which receives a control signal ▲ ▼ at its gate.
It is coupled to the second word line W12 through ETQ13. Further, the output terminal of the inverter circuit IV1 which receives the output signal of the NOR gate circuit NOR1 has a control signal ▲ ▼ at its gate.
It is coupled to the second word line W12 through a P-channel type transmission gate MOSFET Q14 which receives it. The negative voltage supply circuit VSC provided between the second word line W12 and the negative voltage terminal −Vpp is not particularly limited, but it is possible to give the second word line W12 a negative voltage of a good level. So that the bootstrap capacitor C
And MOSFETs Q15 to Q18. That is,
A diode-type P-channel MOSFET Q15 is provided between which the negative voltage of the negative voltage terminal -Vpp is connected to the word line W12. Above negative voltage terminal -Vpp and capacitor C
A P-channel MOSFET Q16 having its gate coupled to the second word line W12 is provided between the second word line W12 and the first electrode. Between the one electrode of the capacitor C and the second word line W12, a diode-type P-channel MOSFET oriented so that current flows from the word line W12 side.
Q17 is provided. A P-channel MOSFET Q18 having its gate coupled to the second word line W12 is provided between the other electrode of the capacitor C and a terminal φosc to which an oscillation pulse formed by the oscillation circuit OSC of FIG. 1 is applied.
Is provided. Between the word line W12 and the ground point of the circuit is provided a P-channel MOSFET Q19 whose gate receives the control signal ▲. This word line W12
Is supplied with the ground potential of the circuit before the level conversion circuit starts the level conversion operation.

The control signal ▲▲ applied to the circuit shown in the drawing is temporarily changed from a level of about 5V to a level of about -4V at the start of the erase operation and at the time of writing data to the memory cell. The control signal ▲ ▼ is changed from a level of about 5V to a level of about 0V in the erase operation. The control signal ▲ ▼ changes from the level of about 5V to the timing of the write operation timing to the memory cell.
The level is set to 0V.

The level conversion operation of this embodiment is as follows.

For example, in the erase operation, first the control signal ▲▲
Is temporarily set to low level, MOSFETQ1
Since 9 is turned on, the second word line W12 is reset to the ground potential of the circuit. In the erase operation, the control signal ▲ ▼ is set to a high level of about 5V and the MOSFET Q13
Correspondingly remains off. Control signal ▲
▼ indicates a control signal at the start of the erase operation ▲▲
In synchronism with the timing when is returned to the high level, the ground potential is set to the low level. At this time, MOSFET Q14
The ON / OFF state of the inverter is determined by the output level of the inverter circuit IV1. For example, NOR gate circuit NOR1
If the selection signal output from the inverter circuit IV1 is set to the low level of the ground potential in response to the selection level being the high level, the corresponding MOSF
ETQ14 is turned off because its gate and source will be at the same potential. In this case, the second word line
The MOSFET W19 maintains the low level in the floating state because the MOSFET Q19 is turned off by the high level of the control signal ▲ and the MOSFET Q14 is turned off.

The second word line in the floating state is a negative voltage supply circuit
It is brought to a negative potential by the operation of VSC. That is, when the second word line W12 is in the floating low level, the oscillation pulse is almost equal to the power supply voltage Vcc.
When it goes to a high level equal to
SFET Q18 is turned on. Capacitor C and terminal-Vpp
MOSFET Q16 provided between and is turned on by applying a positive potential to its one electrode via capacitor C. As a result, the capacitor C is precharged. Next, when the oscillation pulse is brought to the ground potential of the circuit, the capacitor C gives a negative potential to the MOSFETs Q16 and Q17 by the charge pump action. This negative potential turns on MOSFET Q17,
The potential of the second word line is made negative. Next, when the oscillation pulse is set to the high level, the capacitor C is charged up again. In this case, since the gate potential of the MOSFET Q16 is set to a negative potential according to the negative potential of the word line W12, the on state is maintained until one electrode of the capacitor C substantially drops to the level of the word line W12. To do.
In response, capacitor C is precharged with a level greater than the initial precharge level. By repeating the same operation, the negative voltage −Vpp above is about 12V.
If it is a negative high voltage such as, the potential of the second word line W12 is lowered to a low potential such as about -10V. In addition, in response to the voltage loss corresponding to the threshold voltage of the diode type MOSFETs Q17 and Q16, the negative voltage Vpp
Is -12V, the potential of the word line 12 is -10V. On the other hand, if a low level non-selection level signal is sent from the NOR gate circuit NOR1, the MOSFET Q14
Is turned on in response to a high level signal supplied from the inverter circuit IV1. In response to this, the high level signal of the inverter circuit IV1 is transmitted to the word line W12 via the MOSFET Q14. Here, in the circuit of FIG. 2, the driving capability of the second word line W12 by the MOSFET Q14 is
It is also made stronger by that of the voltage supply circuit VSC. Therefore, if the MOSFET Q14 is turned on as described above, the potential of the second word line W12 is set to a high level such as about 5V.

Further, in the data writing operation to the memory cell, the control signal ▲▲ is temporarily set to the low level, and in response to this, the second word line W12 is reset to the ground potential of the circuit. The control signal ▲ ▼ is the control signal ▲▲
Is switched from a high level of about 5V to a low level equal to about 0V substantially in synchronism with the timing when is returned to a high level. At this time, if the output of the NOR gate circuit NOR1 is at the high level selection level, the MOSFET Q13 is accordingly turned on. In this way, when the high-level selection signal is sent from the NOR gate circuit NOR1, the potential of the second word line W12 is set to a high level such as about 5V, contrary to the erase operation. Conversely, if a low-level non-selection signal is sent from the NOR gate circuit NOR1, the MOSF
ETQ13 remains off. In this case, the potential of the second word line W12 is set to -10V by the same operation as that of the voltage level conversion circuit described above.

FIG. 3 shows a control voltage generation circuit for the well region WELL.
A circuit diagram of one embodiment of Vw-G is shown.

The control voltage generator Vw-G has its source,
The drain is coupled to the power supply terminal Vcc and the well region WELL,
A P-channel MOSFET Q20 whose gate receives a control signal ▲ ▼, its drain and source are coupled to the WELL and the ground point of the circuit, and a P-channel MOSFET Q21 which receives a control signal ▲▲ at its gate, a negative voltage supply circuit VSC and its gate P channel receiving control signal ▲ ▼ '
It consists of MOSFET Q22.

Control signal ▲ ▼ indicates that MOSFET Q2
It is changed from a high level of about 5V to a low level of about 0V so that 0 is turned on.

The control signal ▲▲ is changed from a low level of about 0V to a high level of about 5V so as to turn off the MOSFET Q21 during the erase operation and the second write operation.

As a result, the MOSFET Q20 sets the output voltage Vw supplied to the well region WELL to a level such as 5V during the erase operation.

The MOSFET Q21 is turned on during the read operation to bring the output voltage Vw to the low level.

Both MOSFETs Q20 and Q21 are turned off when writing data to the memory cell. In this state, the level of the output voltage Vw is determined by the negative voltage supply circuit VSC.

Negative voltage supply circuit VSC in control voltage generator Vw-G
Has a configuration similar to that of FIG. The oscillation pulse OSC required for the operation of the negative voltage supply circuit VSC is supplied to it via a P-channel type transmission gate MOSFET Q22 which is switch-controlled by the write control signal ∇ '.

The control voltage generation circuit Vig-G that forms the control voltage Vig supplied to the gate of the separation MOSFET Q3 is configured by a circuit similar to the circuit shown in FIG. 2 except that the control signal is different. .

FIG. 4 is a circuit diagram of the latch circuit FF. Latch circuit FF
Is a P-channel MOSFET Q23, Q25, N-channel MOSFET
A flip-flop circuit composed of Q24 and Q26, and a P-channel transmission gate whose source and drain are coupled between an input / output node of the flip-flop circuit and the data line D1 and whose gate is supplied with a control signal ▲ ▼.
MOSFET Q29 and P-channel MOSFET Q2 which is switch-controlled by the input / output node of such flip-flop circuit
8 and a P-channel MOSFET Q27 whose gate is supplied with a control signal ▲ ▼.

The control signal ▲ ▼ is the MOSF during the first write operation.
It is set to a low level equal to the ground potential of the circuit so that the ETQ29 is turned on.

As a result, the data signal of the high level which is almost equal to the power supply voltage or the low level which is almost equal to the ground potential generated from the data input circuit DIB of FIG. 1 at the time of the first write operation is applied to the Y switch circuit C-SW and the data line. D1 and transmission gate
It is supplied to the flip-flop circuit through the MOSFET Q29. As a result, the input / output node of the flip-flop circuit is set to the high level or the low level corresponding to the output of the data input circuit DIB.

When writing data to the memory cell, control signal ▲
▼ is set to a high level almost equal to the power supply voltage to turn off the MOSFET Q29, and the control signal ▲ ▼▼
It is brought to a low level almost equal to the ground potential so as to turn on the MOSFET Q27. The on / off state of MOSFET Q28 is controlled by a flip-flop circuit. If the input / output node of the flip-flop circuit is at the high level according to the previously written data, the MOSF
ETQ28 is turned off. In this case, the level of the data line D1 is set to the negative write level by the negative voltage supply circuit VSC. When the input / output node of the flip-flop circuit is at the low level of the ground potential of the circuit, the MOSFET Q28 is turned on. In this case, the data line D1 is almost
Brought to a level equal to Vcc.

Next, an example of the operation of this embodiment circuit will be described with reference to the timing chart shown in FIG.

In this embodiment, in the write operation, the stored information of all the memory cells addressed to the word line and coupled to the word line is read out once and held in each latch circuit FF shown in FIG. 1 in the write operation. . Then, the data signal supplied from the external terminal is taken in by the latch circuit corresponding to the data line of the memory cell to be written. For example, when all bits are rewritten to a memory cell coupled to a word line, the Y address is sequentially switched, so that a write signal composed of a plurality of bits supplied from an external terminal is latched in correspondence with each other. Sequentially taken into the circuit.

After that, as is apparent from the operation description below, the erasing operation of the MNOS transistor coupled to the word line is performed, and thereafter, the memory cells for one word line are simultaneously broadcasted according to the information of the latch circuit FF. A write operation is performed. With the above operation, static RA from the outside
The same write operation as M can be performed.

In the write operation mode, when the read operation is taken into the latch circuit FF and the rewrite operation ends, in other words, when the first write operation ends, the control signal EW for instructing the next second write operation is issued. Fifth
As shown in FIG. A, the low level is changed to the high level. Each internal signal ▲ ▼, ▲ with a predetermined time difference
▼ and ▲ ▼ are changed from the high level to the low level as shown in FIGS. 5B to 5C, respectively.

Low level of internal signal ▲ ▼ (high level of er)
As a result, the MOSFET Q6 in the drive circuit DVR of FIG. 1 is turned on, so that the common source line CS of the memory array M-ARY is set to a high level such as + 5V. Due to the time difference between the internal signals ▲ ▼ and ▲ ▼, the reset signal ▲▲ is temporarily set to a low level such as + 5V to -4V. As a result, the output terminals (word line W12, etc.) of the level conversion circuit LVC in FIG. 2 are reset to the ground potential and then set to the low level (0 V) in the floating state. Also, due to the time difference between the internal signals ▲ ▼ and ▲ ▼, the reset signal ▲▲ temporarily changes from + 5V to-
It is set to a low level such as 4V. This allows the well WELL
A reset operation similar to the above is carried out for a load having a relatively large parasitic capacitance such as an isolation MOSFET or the like.

The low level of the internal signal {circle over (3)} causes the X decoder X-DCR to start its level changing operation. For example, the gate potential of the selected second word line, in other words, the MNOS transistor to be erased is lowered to a negative high voltage such as about -10V as described above. The word line to be unselected, in other words, the gate voltage of the MNOS transistor in which the erase operation is prohibited is set to a high level such as + 5V, although not shown, as is apparent from the above description of the operation.

After this, a control voltage generation circuit Vw that forms a drive voltage for the body gate of the memory array M-ARY, in other words, the well region WELL, according to the low level of the internal signal ▲ ▼.
-G brings its voltage Vw to a high level such as + 5V.

As a result, a high negative voltage is supplied between the gate of the MNOS transistor coupled to the selected word line and the body gate, and as a result, the information charges taken in the floating gate are tunneled by the high electric field. Returned to the substrate gate. Since the gate of the MNOS transistor coupled to the unselected word line and the body gate have the same potential, their erasing is not performed.

In addition, each internal signal ▲
Like ▼, ▲ ▼, and the like, the respective levels are changed from the low level to the high level with a time lag in the reverse order of the erase start. In response to this, the well region WELL, the second word line, and the data line are restored to their original states in this order. In addition, each reset signal ▲ ▲, ▲
▼ and ▲ ▼ are formed. In the above operation timing, the P-type well region WELL is started at the start of erasing.
Is finally raised to a high level such as the power supply voltage Vcc, and is lowered first at the end, so that the N-type of the address selecting MOSFET and the isolation MOSFET formed in the well region WELL is formed. The PN junction between the drain and source and the well region WELL can be maintained in a reverse bias state.

After the erase operation, the write operation is performed subsequently.

The internal signals ▲ ▼ ′ and ▲ ▼ are sequentially changed from the high level to the low level with a time difference.

By the low level of the internal signal {circle around (1)}, the control voltage generation circuit Vw-G makes the voltage Vw a negative high voltage -Vpp such as -12V. As a result, the well region WELL in which the memory array M-ARY is formed has a negative high voltage -Vpp.
Be lowered to. In synchronization with this, the control voltage generation circuit Vig
-G also causes its voltage Vig to be a negative high voltage, such as about -10V. As a result, each isolation MOSFET of the memory cell is turned off. Further, the low level of the internal signal ∇ 'opens the gate circuit G of the X decoder X-DCR, the first word line of the selected memory cell is set to the high level (+ 5V), and the non-selected word line is It is brought to the circuit ground potential (0 V) (not shown).

Next, in synchronization with the low level of the internal signal ▲ ▼,
The X decoder X-DCR sets the selected second word line to the high level (+ 5V) and the non-selected ones to the low level.
Upon receiving this high level and low level, the level conversion circuit
In the case of the LVC, the second word line is set to a high level such as + 5V if it is a high level selection signal, and if it is a low level non-selection signal, the second word line is set to a negative high voltage such as −10V. To do. Further, the level conversion circuit LVC coupled to each data line is put into an operating state, and, for example, the one that writes the logic "1" according to the stored information of the corresponding latch circuit FF has a negative high voltage such as about -10V. The one that writes logic "0" (write-inhibited) is set to a high level such as about + 5V. Therefore, since the gate voltage of the MNOS transistor to which the logic "1" is written is about + 5V, the voltage of the substrate gate (well region WELL) is about -12V, and the drain (data line) voltage is about -10V, the substrate is About 15 between the gate channel and the gate electrode
A high electric field such as V acts to inject electrons by the tunnel effect. On the other hand, since the drain voltage of the MNOS transistor in which the logic “0” is written is set to about + 5V, the high voltage is not applied between the gate and the channel, so that the injection of electrons is not performed.

At the end of the write operation, each internal signal ▲
Like ▼ and ▲ ▼ ′, the respective levels are changed from the low level to the high level with a time lag in the order opposite to that at the start. Accordingly, the data line, the second word line, and the well region are restored to their original states in this order. Further, each reset signal ▲▲, ▲ ▼ and ▲ based on the above internal signal
▼ is formed. In the above operation timing, the P-type well region WELL is first lowered to a negative high voltage at the start thereof, and is finally restored at the end thereof, so that it is formed in the well region WELL. It is possible to maintain the PN junction between the N-type drain and source of the selected address selection MOSFET and the isolation MOSFET and the well region WELL in the reverse bias state.

〔effect〕

(1) By using a negative high voltage, the potential of the semiconductor substrate is fixed to a predetermined voltage such as a positive power supply voltage,
Writing and erasing of the MNOS transistor can be performed. Therefore, the P-channel MOSFET operated by the signal level such as the power supply voltage and the ground potential of the circuit can be formed on the semiconductor substrate, and the peripheral circuits such as the address decoder and the address buffer can be formed by the CMOS circuit. As a result, low power consumption and high speed operation can be achieved by the CMOS circuit.

(2) In the write / erase operation of the MNOS transistor, by controlling the potential change based on the well region in which the memory array is formed, the PN junction between the drain and source of the MOSFET formed therein is reverse biased. Can be maintained. As a result, it is possible to reliably prevent the occurrence of latch-up in the CMOS circuit.

(3) In the write operation mode, the read operation is performed and the stored information before writing is held in the latch circuit, and the rewrite information is set in the latch circuit. Then 1
While erasing MNOS transistors for word lines,
MNOS for one word line according to the information stored in the latch circuit
By writing to the transistor, an effect that the writing operation can be performed from the outside by the same control as that of the RAM is obtained.

(4) By the above (3), a plurality of bits can be continuously rewritten in the write information to the latch circuit in synchronization with the change of the Y address, and a plurality of bits can be simultaneously written according to the held information. Therefore, it is possible to obtain the effect that the high-speed multi-bit write operation can be realized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. The erase operation and the write operation may be continuously and automatically executed based on a control signal supplied from an external terminal by providing an appropriate sequence circuit in the control circuit CONT.
Also, the MOSFET Q3 for separation of each memory cell is omitted and the MNOS
The source of the transistor may be connected to the reference potential line. In this case, the reference potential line is set in a floating state during the write operation, and the ground potential of the circuit is applied during the read and erase operations.

Further, the X-decoder, the latch circuit, and the voltage supply circuit that selectively supplies the high negative voltage by the control signal may have any specific circuit configuration.

Further, the latch circuit provided in each data line may be omitted. In this case, each data line may be provided with a level conversion circuit so that only the one selected by the address selection signal is selectively set to a negative high voltage in response to the write signal. Therefore,
The level conversion circuit provided in the non-selected data line forms the write blocking voltage according to the address selection signal of the non-selected level.

[Field of application]

The present invention can be widely used as an EEPROM device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of an essential part of an EEPROM device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of an X decoder and level conversion circuit thereof, and FIG. 3 is a well region. FIG. 4 is a circuit diagram showing an embodiment of the supplied control voltage generating circuit, FIG. 4 is a circuit diagram of a latch circuit, and FIG. 5 is a timing diagram showing an example of the operation of the EEPROM device. M-ARY ... Memory array, X-DCR ... X decoder, LVC ...
Level conversion circuit, FF ... Latch circuit, Vig-G, Vw-G ... Control voltage generation circuit, IOB ... Input / output circuit, WELL ... Well area

Claims (1)

[Claims] 1. An address selection MOSFET, which is coupled by a stacked gate structure in which a part of each gate electrode is overlapped with an electrically writable and erasable semiconductor nonvolatile memory element sandwiched therebetween, and For separation
The first P in which a plurality of memory cells composed of MOSFETs are formed
The well region and the N-channel MOSFET that constitutes the CMOS circuit are formed,
The second P-type well region to which the ground potential of the circuit is constantly applied, the first and second P-type well regions and the P-channel type MOSFET forming the CMOS circuit are formed, and the power supply voltage is constantly N-type semiconductor substrate supplied and MOSF for address selection of memory cells arranged in the same row
A plurality of first word lines connected to the ET gate and a plurality of second word lines connected to the control gates of the nonvolatile memory elements of the memory cells arranged in the same row.
A word line, a plurality of data lines arranged so as to be orthogonal to the first word line and the second word line, and connected to the drains of the address selection MOSFETs of the memory cells arranged in the same column; A control line to which the gates of the MOSFETs are commonly connected and a common source line to which the sources of the isolation MOSFETs are commonly connected are provided, and the second word line and the first P-type well region are provided in respective operation modes. A negative voltage supply circuit that extracts a negative high voltage stepwise by a charge pump circuit in response to the power supply voltage and the negative voltage between the second word line and the first P-type well region during the write operation. Positive high voltage is applied, and a high negative voltage and power supply voltage are applied between the second word line and the first P-type well region during the erase operation, and the nonvolatile memory element and its channel region are Between tunnels Was allowed to occur with to perform the programming and erasing, the first P-type is formed in the well region address selection MOSFET respectively corresponding to the erase operation as described above write operation
Potential of the common source line connected to the data line connected to the drain and the source of the separation MOSFET and the separation MOSF
The potential of the control line is set to turn off ET, and the first of the potential changes at each node in these operation modes is set.
EE is characterized in that the P-type well region is changed last from the circuit ground potential to the power supply voltage, and first changed from the power supply voltage to the circuit ground potential.
PROM device.