JPH0732161B2 - Bipolar transistor manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for manufacturing a bipolar LSI that operates at high speed, and for that reason, it is necessary to reduce the parasitic capacitance between the base and the collector. Therefore, the manufacturing process of the present invention is performed. In conventional, a bipolar LSI with a small base width without performing burying, diffusion or epitaxial growth as in the past
The manufacturing method of the above, wherein the base is also drawn out using a single crystal.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar LSI that operates at high speed.

Recently, a high-speed operation of a vanpolar LSI is required, and the demand is particularly strong in a semiconductor device used for information equipment.

The present invention provides a method of manufacturing a bipolar LSI that can improve high-frequency characteristics by reducing parasitic capacitance between the base and collector, which is a drawback of the related art, and can cope with high speed.

[Prior Art] FIGS. 2A to 2D show a conventional bipolar LSI.
FIG. 6 is a cross-sectional view for explaining the manufacturing process of.

In FIG. 2 (a), there is a (111) silicon substrate 1, and a high concentration N ⁺ b region 2 is formed at a predetermined position on the surface thereof by arsenic ion implantation. The resistance of this region is 20Ω / □. It is a degree.

FIG. 2 (b) shows that the silicon film 3 is epitaxially grown by the low pressure CVD method and further the collector contact (Ncc) is formed.
4 is formed.

In FIG. 2C, the base region 5 is formed by ion implantation, and the surface of the base region 5 is further formed by ion implantation of the emitter 6.

In FIG. 2D, an insulating film 7 is formed of a silicon dioxide film on the surface, and patterning is performed to form aluminum wiring 8.

Since the bipolar LSI manufactured by such a manufacturing process has a structurally large area compared to the region between the base and the collector which actually operates (a in the figure), the electric capacitance of that part is extremely large. However, there is a drawback that the epitaxial layer of the silicon film 3 cannot be thinned due to the parasitic capacitance that limits the operation speed and diffusion from the N ⁺ b region 2.

[Problems to be Solved by the Invention] In the conventional bipolar LSI described above, the parasitic capacitance between the base and the collector is large, and the speed cannot be increased, and the epitaxial layer cannot be thinned. Difficulties are a problem.

[Means for Solving Problems] FIG. 1 is a sectional view of a bipolar LSI formed by the manufacturing method of the present invention which solves the above problems.
The first region above has a first height, the second region has a step difference consisting of the first and second heights, and the second height is greater than the first height. A convex portion is formed to be low, and a first silicon nitride film (12), a silicon dioxide film (13) and a second silicon nitride film are formed on the surface of the substrate (11) including the first and second regions. A film (14) is sequentially formed, a polysilicon film (15) is formed on the surface of the film, and the film is planarized. Then, the LOCOS method (LOCal Oxidation of Silico) is formed on the polysilicon film (15).
n) forms a silicon oxide (16), and then a second silicon nitride film (14) and a silicon dioxide film (13).
And the first silicon nitride film (14) are removed, a metal silicide (17) is formed on their surface, and patterning is performed so as to connect the convex portions of the first and second regions, and further the surface thereof. After forming polysilicon to be the support (18) on the substrate, the back surface of the substrate (11) is polished to planarize the surface of the first nitride film (12), and impurities are introduced into the substrate to Form the collector contact part (19) in one region,
An external base portion (23), a base portion (22), and an emitter portion (20) are formed in a region having the second height of the second region, and the first height of the second region is The bipolar LSI of the present invention can be achieved by forming the collector portion (21) on the convex portion.

[Operation] The present invention is completely different from the conventional bipolar LSI structure in order to improve the drawback that it is not suitable for high-speed operation because the parasitic capacitance becomes large due to the large junction area between the base and the collector. By adopting a manufacturing method without burying, diffusion, or epitaxial growth, the junction area between the base and the collector can be remarkably reduced, and parasitic capacitance can be reduced to enable high speed operation.

[Embodiment] FIGS. 1 (a) to 1 (h) are sectional views for explaining a manufacturing method according to an embodiment of the present invention.

In FIG. 1 (a), an uneven portion required for forming a collector is formed at a predetermined position on the surface of the N-type substrate 11 by anisotropic etching.

In FIG. 1 (b), etching for further forming a step is performed, and the surface thereof is subjected to a CVD method to form silicon nitride (Si
N) film 12, silicon dioxide (SiO ₂ ) film 13, and silicon nitride film 14 are laminated.

In Fig. 1 (c), the polysilicon 15 is normally pressured on the irregularities on the surface.
The surface of the buried surface is flattened by the CVD method.

FIG. 1 (d) shows that the polysilicon 16 is oxidized by the LOCOS method, and the oxide 16 is formed by oxidizing the exposed portion of the silicon nitride (SiN) film 14 as a mask material.

FIG. 1 (e) shows that metal silicide 17 is formed on the surface of the metal silicide 17.
For example, tungsten silicide is deposited, but this metal silicide may be any material as long as it has a melting point of 1200 ° C. or higher.

This metal silicide corresponds to N ⁺ b of the conventional bipolar LSI, and the conductivity is further improved by using metal silicide.

In FIG. 1 (f), polysilicon or the like is further formed as a support 18 on the surface by atmospheric pressure CVD method with a thickness of about 500 μm,
The back surface of the substrate is polished to the position of the portion b by caustic potash and polishing.

In FIG. 1 (g), a collector contact (N ⁺ cc) portion 19 and an emitter 20 are formed by adjoining ion implantation, the collector portion 21 and the collector contact portion 19 are connected, and the base portion 22 and the external base are connected. The portions 23 are formed by implanting boron ions, respectively.

In FIG. 1 (h), a predetermined insulating film 24 is finally formed of an oxide film, and then a wiring 25 is made of aluminum or the like to complete a bipolar LSI.

Bipolar LSI formed by such a manufacturing method
The base formed in the gap between the emitter and the collector is the width of the emitter and the collector, and the conventional width is 5 μm.
The width of the base according to the present invention is 2 as compared with the degree of
Since it is about μm, the parasitic capacitance is significantly reduced.

[Effects of the Invention] As described in detail above, the bipolar LSI manufactured by the manufacturing method of the present invention can operate at high speed because the parasitic capacitance of the base portion and the collector portion is small, and a high-quality semiconductor device can be provided. There are some great effects.

[Brief description of drawings]

1 (a) to 1 (h) are cross-sectional views for explaining a manufacturing method which is an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are conventional bipolar circuits. LSI
In the drawings, 11 is a substrate, 12 is a silicon nitride film, 13 is a silicon dioxide film, 14 is a silicon nitride film, 15 is a polysilicon film, 16 is a silicon oxide, and 17 is a silicon oxide film. Metal silicide, 18 is a support, 19 is a collector contact part, 20 is an emitter part, 21 is a collector part, 22 is a base part, 23 is an external base part, 24 is an insulating film, 25
Indicates wiring, respectively.

Claims (1)

[Claims] 1. A first area on a substrate (11) has a first height, and a second area has a step formed of a first height and a second height, and a second height. A step of forming a protrusion so that the height is lower than the first height, and a first silicon nitride film (12) and a dioxide on the surface of the substrate (11) including the first and second regions. Silicon film (1
3), and the step of sequentially forming the second silicon nitride film (14), forming a polysilicon film (15) on the second silicon nitride film (14), and then flattening the surface to form the poly silicon film. Embedding the silicon film (15) in a region other than the convex portion and exposing the surface of the second silicon nitride film (14) on the convex portion having the first height of the first and second regions. A step of selectively oxidizing the polysilicon film (15) to form a silicon oxide (16) by using the second silicon nitride film (14) exposed on the surface as a mask; Removing the silicon film (14), the silicon dioxide film (13), and the first silicon nitride film (14) to expose the substrate surface of the convex portions in the first and second regions; Substrate (11) containing a polysilicon film (15)
Forming a metal silicide (17) on the surface of, and patterning so as to connect the convex portions having the first height of the first and second regions, and a substrate including the metal silicide (17) ( 11) a step of forming polysilicon to be a support (18) on the surface, a step of polishing the back surface of the substrate (11) to planarize the surface of the first nitride film (12), and Impurities are introduced to form a collector contact part (19) in the first region, and an external base part (23) and a base part (2) are formed in a region having the second height of the second region.
2) and a step of forming an emitter part (20) and forming a collector part (21) on a convex part having the first height of the second region. Method.