JPH0732224B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0732224B2 JPH0732224B2 JP63261921A JP26192188A JPH0732224B2 JP H0732224 B2 JPH0732224 B2 JP H0732224B2 JP 63261921 A JP63261921 A JP 63261921A JP 26192188 A JP26192188 A JP 26192188A JP H0732224 B2 JPH0732224 B2 JP H0732224B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- external lead
- solder
- present
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を封止樹脂によりパツケージングし
てなる表面実装タイプの半導体装置に関するものであ
る。The present invention relates to a surface mount type semiconductor device in which a semiconductor element is packaged with a sealing resin.
従来の表面実装タイプの半導体装置は第３図に示すよう
に構成されていた。図において、（１）は半導体素子が
収納された半導体パツケージ、（２）は半導体パツケー
ジ（１）から露出した外部リードで、（2a）は外部リー
ドに施された外装めつき（たとえばはんだめつき・錫め
つき等）である。A conventional surface mount type semiconductor device is constructed as shown in FIG. In the figure, (1) is a semiconductor package in which a semiconductor element is housed, (2) is an external lead exposed from the semiconductor package (1), and (2a) is an external lead (for example, soldering) applied to the external lead. Tsuki, tinned, etc.).
このように構成された半導体装置の組立ては半導体パツ
ケージ（１）に収納されている半導体素子（図示せず）
の接合及び接続等の組立ておよび封止樹脂によるパツケ
ージングが行なわれる。A semiconductor device (not shown) housed in the semiconductor package (1) is assembled into the semiconductor device having the above-described structure.
Assembling such as joining and connection and packaging with the sealing resin are performed.
次いで、外部リード（２）の外装めつき（2a）が施こさ
れる。しかる後、外部リード（２）のリード成形加工が
行なわれる。Then, the outer lead (2) is provided with the outer plating (2a). Thereafter, lead forming processing of the external lead (2) is performed.
従来の半導体装置は以上のように構成されていたので、
第４図に示すように半導体装置を基板（４）（ガラエポ
基板、厚膜基板等）にはんだ（６）を介して実装する場
合に、リフロー（赤外線リフロー、VPSリフロー等）時
にはんだ（６）が外部リード（２）に施こされた外装め
つき（2a）に沿つて這い上がり、半導体パツケージ
（１）と外部リード（２）の界面にクラツク等が生じる
などの問題点があつた。Since the conventional semiconductor device is configured as described above,
As shown in FIG. 4, when the semiconductor device is mounted on the substrate (4) (glass epoxy substrate, thick film substrate, etc.) via solder (6), solder (6) is used during reflow (infrared reflow, VPS reflow, etc.). Crawling up along the external plating (2a) applied to the external lead (2), and there is a problem that cracks or the like are generated at the interface between the semiconductor package (1) and the external lead (2).
本発明は上記のような問題点を解消するためになされた
もので、表面実装タイプの半導体装置のはんだの這い上
がりを防止することができる半導体装置を得ることを目
的とするものである。The present invention has been made in order to solve the above problems, and an object of the present invention is to obtain a semiconductor device capable of preventing the solder from creeping up in a surface mount type semiconductor device.
本発明に係る半導体装置は半導体パツケージから露出す
る外部リードの裏面側に溝加工を設けたものである。The semiconductor device according to the present invention has a groove formed on the back surface side of the external lead exposed from the semiconductor package.
本発明の半導体装置は半導体パツケージから露出する外
部リードの裏面側に溝加工を設けることにより、半導体
装置を基板にはんだを介して実装する場合に外部リード
へのはんだ這い上がりを防止することができる。In the semiconductor device of the present invention, by providing the groove processing on the back surface side of the external lead exposed from the semiconductor package, when the semiconductor device is mounted on the substrate via the solder, it is possible to prevent the creeping up of the solder to the external lead. .
以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による半導体装置の部分断面図、
第２図は第１図の半導体装置を使つた場合の実装状態の
断面図を示す。図において、前記従来のものと同一符号
は同一のものを示す。図中（３）は外部リード（２）の
裏面側に設けられた溝加工である。また本実施例の半導
体装置の組立ては外部リード（２）の外装めつき（2a）
を施こすまでは従来と同様の方法によつて行うことがで
きる。外部リード（２）への溝加工（３）はリード成形
加工と同時又は加工前に金型で加工する。このように構
成された半導体装置は半導体装置を基板（４）にはんだ
（６）を介して実装する場合に、外部リード（２）への
はんだ（６）這い上がりを防止することができる。An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a partial sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 2 shows a sectional view of a mounted state when the semiconductor device of FIG. 1 is used. In the figure, the same reference numerals as those used in the prior art indicate the same components. In the figure, (3) is a groove processing provided on the back surface side of the external lead (2). Further, the semiconductor device of this embodiment is assembled by attaching the outer lead (2) to the outer cover (2a).
It can be carried out by a method similar to the conventional method until it is applied. Grooving (3) on the external lead (2) is performed with a mold at the same time as or before the lead forming process. The semiconductor device thus configured can prevent the solder (6) from creeping to the external lead (2) when the semiconductor device is mounted on the substrate (4) via the solder (6).
以上のように本発明にかかる半導体装置によれば、表面
実装基板の製造において、基板にはんだを介して実装す
る場合に外部リードへのはんだ這い上がりを防止するこ
とができ、半導体装置の信頼性の向上に効果がある。As described above, according to the semiconductor device of the present invention, in the manufacture of the surface mount board, when the board is mounted via solder, it is possible to prevent the solder wicking to the external lead, and to improve the reliability of the semiconductor device. Is effective in improving.
第１図は本発明の一実施例による半導体装置の構成を示
す部分断面図、第２図は第１図の半導体装置を用いた時
の実装状態の断面図、第３図は従来の半導体装置の構成
を示す部分断面図、第４図は従来の第３図の半導体装置
を用いた時の実装状態の断面図である。 図において、（１）は半導体パツケージ、（２）は外部
リード、（2a）は外装めつき、（３）は溝加工、（４）
は基板、（５）はランド、（６）ははんだを示す。 なお、図中、同一符号は同一、又は相当部分を示す。1 is a partial cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a mounted state when the semiconductor device of FIG. 1 is used, and FIG. 3 is a conventional semiconductor device. 4 is a partial cross-sectional view showing the structure of FIG. 4, and FIG. 4 is a cross-sectional view of a mounted state when the conventional semiconductor device of FIG. 3 is used. In the figure, (1) is a semiconductor package, (2) is an external lead, (2a) is an external package, (3) is groove processing, (4).
Is a substrate, (5) is a land, and (6) is a solder. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
の裏面側に溝加工を設け、外部リードに施こされためつ
きを分離さしたことを特徴とする半導体装置。1. A semiconductor device characterized in that a groove is formed on a back surface side of an external lead exposed from a semiconductor package to separate a sticking applied to the external lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63261921A JPH0732224B2 (en) | 1988-10-18 | 1988-10-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63261921A JPH0732224B2 (en) | 1988-10-18 | 1988-10-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02109356A JPH02109356A (en) | 1990-04-23 |
| JPH0732224B2 true JPH0732224B2 (en) | 1995-04-10 |
Family
ID=17368576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63261921A Expired - Lifetime JPH0732224B2 (en) | 1988-10-18 | 1988-10-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732224B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100280086B1 (en) * | 1995-10-19 | 2001-02-01 | 마이클 디. 오브라이언 | Lead Frame Structure of Semiconductor Package |
| US7737546B2 (en) * | 2007-09-05 | 2010-06-15 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | Surface mountable semiconductor package with solder bonding features |
| JP7647722B2 (en) * | 2022-10-27 | 2025-03-18 | 株式会社村田製作所 | Manufacturing method of electrolytic capacitor |
-
1988
- 1988-10-18 JP JP63261921A patent/JPH0732224B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02109356A (en) | 1990-04-23 |
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