JPH0732359B2 - Logic circuit - Google Patents

Description

The present invention relates to a logic circuit having a differential amplifier as a basic configuration.

B. Summary of the Invention The present invention is a logic circuit in which a transistor does not operate in a saturation operation, and in a logic circuit which is the basis of a configuration such as an EX-OR gate and a flip-flop, a pair of differential pairs forming a current switch circuit is formed. Amplitude (logical amplitude) between high level and low level is equalized to the base of the transistor,
Moreover, the reference voltage is made unnecessary by supplying two inputs having a level difference of 1/2 of this amplitude.

C. Prior Art As shown in, for example, US Pat. No. 3,259,761, there is known a logic circuit having a differential amplifier in which emitters of transistors are commonly connected as a basic configuration. This logic circuit
It is called ECL (Emitter Coupled Logic).

FIG. 11 shows such a logic circuit, and 51, 53, and 61 show transistors whose emitters are commonly connected to each other and whose emitter common connection point is connected to a constant current source 55. The input terminal 52 is connected to the base of the transistor 51,
The input terminal 54 is connected to the base of 53, and the input terminal 62 of the reference voltage Vr1 is connected to the base of the transistor 61.

The collectors of the transistors 51 and 53 are connected to each other, and this common connection point is connected to the power supply terminal 67 via the resistor 56 and is also led out as the output terminal 57. The collector of the transistor 61 is connected to the power supply terminal 67 via the resistor 65 and is led out as the output terminal 66.

Assuming that the inputs supplied to the input terminals 52 and 54 are A and B, and the outputs obtained at the output terminals 57 and 66 are X and X, respectively, the above-mentioned logic circuit will have an OR gate and a NOR gate as shown in FIG. It has a gate function.

In the conventional ECL circuit, as shown in FIG. 13, the center of the logical amplitude VL between the low level (denoted as L in the following description) and the high level (denoted as H in the following description) of the inputs A and B. The level and the reference voltage Vr1 match each other. For example, when one of the inputs A and B is H, a current flows through one of the transistors 51 and 53, and X = H and = L.

Further, as shown in FIG. 14, as an ECL circuit, a configuration is known in which differential pairs are vertically connected in two stages. That is, the differential pair including the transistors 51 and 61 and the differential pair including the transistors 53 and 63 are connected in parallel, and the differential pair including the transistors 71 and 73 is connected to the lower side of the differential pair. It is a thing.

The input A is supplied to the terminal 52 derived from the base of the one transistor 51, and the reference voltage Vr1 is supplied to the terminal 62 derived from the other transistor 61. Further, the input B is supplied to the terminal 54 derived from the base of the one transistor 53, and the terminal 64 derived from the other transistor 63.
Is supplied with the reference voltage Vr1. The collector of the transistor 51 and the collector of the transistor 53 are commonly connected,
The collector of the transistor 61 and the collector of the transistor 63 are commonly connected. This collector common connection point is derived as output terminals 57 and 66.

The collector of the transistor 71 and the collector of the transistor 73 are connected to the emitter common connection point of the transistors 51 and 61 and the emitter common connection point of the transistors 53 and 63, respectively. Transistor 71 emitter and transistor
The constant current source 75 is connected to the emitter connection point of 73.

As shown in FIG. 15, the configuration shown in FIG.
Also, it operates as a selector that selects and outputs the input B and the input C.

The reference voltage Vr1 is set to a higher level than the reference voltage Vr2. As shown in FIG. 16, inputs A and B are connected to the reference voltage Vr.
A logic amplitude VL having a high level of Hu and a low level of Lu centered around 1 is provided, and an input C has a logic amplitude VL of Hd at a high level and Ld at a low level centered on a reference voltage Vr2. . The difference between the reference voltages Vr1 and Vr2 is a voltage for providing the collector-emitter voltage required for the transistor to operate in the active region.

In the configuration shown in FIG. 14, the bases of the transistor 61 and the transistor 53 are commonly connected, and the reference voltage is applied to the terminal 62.
Vr1 is supplied, and transistor 63 and transistor 5
A configuration in which the bases of 1 are commonly connected, the input A is supplied to the terminal 52, and the input B is further supplied to the base of the terminal 72 (Fig. 17).
Form an EX-OR gate.

For example, when the input A is Hu and the input B is Hd, a current flows through the transistor 51 and the transistor 71, and the output X of the output terminal 57 becomes Ld.

D. Problems to be Solved by the Invention Since the conventional ECL logic circuit does not operate the transistor in a saturation operation, it can operate at high speed. However, conventional ECL
The logic circuit requires a reference voltage generation circuit in order to compare the reference voltage Vr1 or Vr2 with the input signal. In a high-speed logic circuit, a large amount of current is passed through each logic circuit. Therefore, in order to absorb an excessive current during switching, a number of reference voltage generating circuits according to the circuit scale are required.

Therefore, the conventional logic circuit has a drawback that the number of elements increases. Further, a wiring pattern for supplying the reference voltage to each logic circuit is required, and the wiring pattern occupies a large proportion on the substrate, resulting in a large chip size.

Therefore, it is an object of the present invention to provide a logic circuit that does not require a reference voltage. According to the present invention, the number of elements such as transistors and resistors can be significantly reduced, and power consumption and delay time can be reduced.

According to the present invention, the value of the constant current source of the differential amplifier can be made small when the operation speed comparable to that of the conventional ECL logic circuit is realized, so that the power consumption is extremely reduced in cooperation with the reduction of the number of elements. be able to.

Further, according to the present invention, since it is not necessary to supply the reference voltage to each gate circuit, a wiring pattern for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced.

E. Means for Solving Problems The present invention is directed to a first current switch circuit (1, 2) composed of a differential pair and a second power switch circuit (3,
4), a load impedance (9, 10) commonly connected to each differential pair of the first current switch circuit (1, 2) and the second current switch circuit (3, 4), The first input (A) and the second input (B *) supplied to the differential pair of the first current switch circuit (1, 2) and the differential of the second current switch circuit (3, 4) The third input (C) and the fourth input (D *) supplied to the pair are connected to the first current switch circuit (1,2) and the second current switch circuit (3,4), A third current switch circuit (5,6) consisting of a differential pair that selectively supplies current to the first current switch circuit (1,2) and the second current switch circuit (3,4); A fifth input (e) and a sixth input (f *) supplied to the differential pair of the third current switch circuit (5, 6), a first input (A) and a second input ( B *) low level and high level Amplitude between Le (VL) is equal and the first
Amplitude (VL) between the input (A) and the second input (B *)
Is provided, the amplitude (VL) between the low level and the high level of the third input (C) and the fourth input (D *) is made equal, and
Between input (C) and fourth input (D *) of amplitude (VL)
Is provided with a level difference of 1/2 of the first input (A) and the second input (B *) or the third input (C) and the fourth input (D *). A level difference (Vs) necessary for operating the differential pair of the first or second current switch circuit is provided between the fifth input (e) and the sixth input (f *). Is a logic circuit.

F. Action The first current switch circuit composed of the differential pair and the second current switch circuit composed of the differential pair can operate without requiring a reference voltage. These two current switch circuits have the same logical amplitude VL and 1 / 2VL
Two inputs with different levels of are provided. A logic circuit having a gate function is configured by the two inputs supplied to each current switch circuit.

G. Embodiment G.1 Configuration of One Embodiment One embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1 and 2 denote transistors that form a differential pair by mutually connecting their emitters. Similarly, 3 and 4 indicate transistors that form a differential pair by mutually connecting the emitters of each other.

The collectors of the transistor 1 and the transistor 3 are connected to each other, the collector connection point is connected to the power supply terminal 17 via the resistor 9, and the output is derived as the output terminal 7 from which the output is taken out. The collectors of the transistor 2 and the transistor 4 are connected to each other, the collector connection point is connected to the power supply terminal 17 via the resistor 10, and the output X is led out as the output terminal 8. These transistors 1, 2, 3, 4 form an upper power switch circuit.

The input A is supplied to the input terminal 11 derived from the base of the transistor 1. The input B * is supplied to the input terminal 12 derived from the base of the transistor 2. The input C is supplied to the input terminal 13 derived from the base of the transistor 3. Input terminal derived from the base of transistor 4
Input D * is supplied to 14.

The emitter connection points of the transistors 1 and 2 are connected to the collector of the transistor 5. The emitter connection points of the transistors 3 and 4 are connected to the collector of the transistor 6. A differential pair is formed by connecting the emitters of the transistor 5 and the transistor 6 to each other. This common emitter connection point is the constant current source 18
Grounded through.

The base of the transistor 5 is connected to the input terminal 15, and the base of the transistor 6 is connected to the input terminal 16. The input e is supplied to the input terminal 15 and the input f * is supplied to the input terminal 16. The transistors 5 and 6 form a lower current switch circuit.

G2. Logical Function of One Embodiment As shown in FIG.
R gates 21 and 23, OR gates 22, 24, 25, and AND gate 26
And can be represented as a configuration of a logic circuit whose output is taken out from the AND gate 26. Generally, a NOR gate whose two input terminals are inverting input terminals is an AND gate.
It becomes a logic circuit equivalent to a gate. Therefore, FIG. 2 is equivalent to the logic circuit shown in FIG.

That is, in one embodiment of the present invention, the output of the OR gate 31 and the OR
The output of the gate 33 is supplied to one input terminal of each of the AND gate 34 and the AND gate 35, the input of the OR gate 32 is supplied to the other input terminal of the AND gate 34, and
It is inverted at 37 and supplied to the other input terminal of AND gate 35, and the outputs of AND gate 34 and AND gate 35 are NOR gate 36.
Is taken out as an output through the. Therefore, one embodiment of the present invention operates as a gated selector.

G3. Input / output level relationship When the power supply voltage is Vcc, the input A and the input C are high level Hu and low level Lu expressed by the following equations.
However, Vcc is a power supply voltage, VL is a logic amplitude, and VBE is a base-emitter voltage of a transistor in the preceding stage, which is not shown.

Hu = Vcc-VBE Lu = Vcc-VBE-VL On the other hand, the inputs B * and D * supplied to the base of the transistor 2 and the base of the transistor 4 are at the high level ▲ H ^* _u ▼ shown in FIG. And a low level ▲ L ^* _u ▼. That is, ▲ H ^* _u ▼ = Hu−1 / 2 VL ▲ L ^* _u ▼ = Lu−1 / 2VL At the base of one transistor 5 of the lower differential pair, as shown in FIG. An input e having a high level Hd and a low level Ld lower than Vs is supplied to each of the high level Hu and the low level Lu. At the base of the other transistor 6 of the lower differential pair, as shown in FIG.
An input f * having a high level ▲ H ^* _d ▼ and a low level ▲ L ^* _d ▼ lower than Vs is supplied to each of the high level ▲ H ^* _u ▼ and the low level ▲ L ^* _u ▼. This voltage difference
Vs is a voltage required for operating the transistors 1 and 2 of the upper current switch circuit.

G4. Logical Operation of One Embodiment In one embodiment of the present invention, the level relationship between the input e and the input f * determines which of the two differential pairs of the upper current switch circuit operates. Input e and input f
When * is both high level or both low level, the differential pair composed of the transistors 1 and 2 operates, and outputs X and X are generated according to the level relationship between the inputs A and B *.
This means that the output of the OR gate 32 in FIG. 3 is at high level. For example, when the input A is low level and the input B * is high level, a current flows through the transistor 2 and the transistor 5, and the output becomes high level.

On the other hand, when the input e is low level and the input f * is high level, the differential pair including the transistor 3 and the transistor 4 operates. This means that the output of the OR gate 32 in FIG. 3 is at low level. For example, when the input C and the input D * are both high level or low level,
A current flows through the transistors 3 and 6, and the output X becomes high level.

G5. Configuration of Other Embodiments Another embodiment of the present invention will be described with reference to FIG. The differential pair including the transistor 1 and the transistor 2 constitutes an upper current switch circuit, and the transistor 5 and the transistor 6 constitute a lower current switch circuit. Load resistors 9 and 10 are inserted between the collector of the transistor 1 and the respective collectors of the transistor 2 and the power supply terminal 17.

The common connection point of the emitters of the transistors 1 and 2 is connected to the collector of the transistor 5, and the collector of the transistor 2 and the collector of the transistor 6 are connected. The constant current source 18 is inserted between the emitter common connection point of the transistors 5 and 6 and the ground.

Inputs A and B * are supplied to the bases of the transistors 1 and 2 from the input terminals 11 and 12, respectively.
Inputs and f * are supplied to the bases of the transistors 5 and 6 from the input terminals 15 and 16, respectively.

G6. Logic Function and Operation of Other Embodiment In this other embodiment, as shown in FIG. 6, a NOR gate 21 to which an input A and an inverted signal of the input B * are supplied, an input e and an input. The logic circuit is composed of a NOR gate 22 to which a signal obtained by inverting f * is supplied, and an OR gate 24 to which the outputs of the NOR gates 21 and 22 are supplied.

Similar to the above-described embodiment, by replacing the NOR gate 24 supplied by inverting the two inputs with the AND gate 34, the configuration of the logic circuit shown in FIG. 7 is realized. That is, the other embodiment has a configuration of a gated AND gate.

As an example, when the input e is low level and the input f * is high level, a current flows through the resistor 10 and the transistor 6, and the output X becomes low level. This corresponds to the output of the OR gate 32 in FIG. 7 becoming low level.

As another example of the operation, when both the input e and the input f * are at the high level or the low level, the current can flow through the transistor 5. This is the OR in Figure 7.
This corresponds to the output of the game 32 going high.
In this state, if the input A is high level, for example, a current flows through the transistor 1 and the output X becomes high level.

G7. Configuration of still another embodiment FIG. 8 shows still another embodiment of the present invention. Similar to the embodiment of the invention shown in FIG. 1, the transistors 1, 2, 3,
The upper current switch circuit is composed of 4, and the lower current switch circuit is composed of the transformers 5 and 6.

The bases of transistors 1 and 4 are input terminals
11 and the bases of the transistors 2 and 3 are connected to the input terminal 12. The input A is supplied to the input terminal 11, and the input B * is supplied to the input terminal 12. The input terminal 15 connected to the base of the transistor 5 is supplied with the input e, and the input terminal 16 connected to the base of the transistor 6 is supplied with the input f *.

G8. Logic Function and Operation of Still Another Embodiment In still another embodiment of the present invention, when taking out as an output, as shown in FIG. 9, NOR gates 21 and 23 are provided.
Can be represented as a configuration of a logic circuit including the OR gates 22, 24, 25 and the OR gate 27. Further, the NOR gate whose two input terminals are inverting force terminals becomes a logic circuit equivalent to an AND gate. Therefore, FIG. 9 is equivalent to the logic circuit shown in FIG.

That is, in yet another embodiment, the output of the OR gate 31 and the output of the OR gate 32 are supplied to the EX-OR gate 37.
Therefore, this further embodiment operates as a gated EX-OR gate.

In this further embodiment, the level relationship between the input e and the input f * determines which of the two differential pairs of the upper current switch circuit operates. When the input e is high level or both the input e and the input f * are low level,
The differential pair consisting of the transistors 1 and 2 operates and the input A
Outputs X and are generated according to the level relationship between B and B *. This means that the output of the OR gate 32 becomes high level.

Also, in the upper current switch circuit, transistors 1 and 2
When the differential pair consisting of is operated, a current flows through the transistor 1 when the input A is at high level or when the inputs A and B * are both at low level. This is shown in Figure 10.
This corresponds to the output of the OR gate 31 becoming high level.
The flow of current through the transistor 1 means that the output from the output terminal 7 becomes low level. That is, OR
When both outputs of gates 31 and 32 are low level, EX-
The output of the OR gate 37 becomes low level.

When the differential pair including the transistor 1 and the transistor 2 is operating, for example, the input A is at the low level,
When the input B * is at high level, a current flows through the transistor 2 and the transistor 5, and the output becomes high level.

On the other hand, when the input e is low level and the input f * is high level, the differential pair including the transistor 3 and the transistor 4 operates. For example, when both the input A and the input B * are high level or low level, a current flows through the transistor 4 and the transistor 6, and the output becomes high level.

H. Effect of the Invention According to the present invention, it is possible to configure a logic circuit in which a transistor does not operate in a saturated manner, like the ECL circuit. The present invention does not require a reference voltage, unlike the conventional ECL circuit. Therefore, it is not necessary to provide a reference voltage generation circuit,
Wiring for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced. Further, when realizing an operating speed similar to that of the conventional ECL, the value of the constant current source of the differential pair can be reduced, so that the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a connection diagram of one embodiment of the present invention, FIG. 2 and FIG.
Each of the figures is a logic circuit diagram of one embodiment of the present invention, and FIG. 4 is a schematic diagram showing the level relationship in one embodiment of the present invention.
FIG. 5 is a connection diagram of another embodiment of the present invention, FIGS. 6 and 7 are logic circuit diagrams of another embodiment of the present invention, and FIG.
FIG. 9 is a connection diagram of another embodiment of the present invention, FIG. 9 and FIG.
10 is a logic circuit diagram of another embodiment of the present invention,
FIG. 11 is a connection diagram of a conventional ECL circuit, FIG. 12 is a logic circuit diagram of the conventional ECL circuit, FIG. 13 is a schematic diagram showing the level relationship in the conventional ECL circuit, and FIG. 14 and FIG. Each is a connection diagram and a logic circuit diagram of another example of the conventional ECL circuit, FIG. 16 is a schematic diagram showing the level relationship in another example of the conventional ECL circuit, and FIG. 17 is a conventional ECL circuit.
It is a connection diagram of another example of a circuit. Description of main symbols in the drawings 1,2,3,4,5,6: Transistors forming differential pair, 7,8: Output terminal, 9,10: Load resistance, 11,12,13,14,15 , 16: Input terminal, 1
8: constant current source.

Claims (1)

[Claims] 1. A first current switch circuit (1, 2) composed of a differential pair, and a second power switch circuit (3, 3) composed of a differential pair.
4), a load impedance (9, 10) commonly connected to the differential pair of each of the first current switch circuit (1, 2) and the second current switch circuit (3, 4), A first input (A) and a second input (B *) supplied to the differential pair of the first current switch circuit (1,2), and the second current switch circuit (3,4) A third input (C) and a fourth input (D *) supplied to the differential pair, the first current switch circuit (1, 2) and the second current switch circuit (3, 4). ), The first current switch circuit (1, 2) and the second current switch circuit (3, 4)
And a third current switch circuit (5, 6) consisting of a differential pair for selectively supplying a current, and a fifth current switch circuit (5, 6) for supplying a differential pair to the differential pair. The amplitude (VL) between the low level and the high level of the input (e) and the sixth input (f *) and the first input (A) and the second input (B *) are made equal, and A level difference of 1/2 of the amplitude (VL) is provided between the first input (A) and the second input (B *), and the third input (C) and the fourth input (D *). ), The amplitude (VL) between the low level and the high level is equalized, and the level difference of 1/2 of the amplitude (VL) is generated between the third input (C) and the fourth input (D *). A set of the first input (A) and the second input (B *) or a set of the third input (C) and the fourth input (D *), and a fifth input ( e) and the sixth entry (F *) logic level difference necessary for the operation of the differential pair of first and second current switch circuit (Vs) is characterized in that provided between the.