JPH0732354B2 - Flip Flop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a flip-flop formed by combining logic circuits having a differential amplifier configuration as a basic configuration.

B. Summary of the Invention The present invention is a flip-flop that uses a logic circuit in which transistors do not operate in a saturated manner. Two differential pairs are connected in the vertical direction, and two differential pairs are supplied to the transistors of the upper differential pair. 1/2 VL between inputs (however, V
L is provided with a level difference in logic amplitude between high level and low level, and similarly, 1 / 2VL (however, VL is provided between two inputs supplied to the transistors of the lower differential pair). Is a logic amplitude difference between a high level and a low level, commonly connects the collector of the second transistor and the collector of the fourth transistor, and collects the collector of one transistor of the upper differential pair. To provide a feedback path to the base of one transistor of the lower differential pair, or a feedback path from the collector of one transistor of the upper differential pair to the base of the other transistor, thereby eliminating the need for a reference voltage. This is a flip-flop.

C. Prior Art As shown in, for example, US Pat. No. 3,259,761, there is known a logic circuit having a differential amplifier in which emitters of transistors are commonly connected as a basic configuration. This logic circuit
It is called ECL (Emitter Coupled Logic).

FIG. 31 shows such a conventional logic circuit.
Reference numerals 3 and 41 denote transistors whose emitters are commonly connected to each other and whose common emitter connection point is connected to the constant current source 35. The input terminal 32 is connected to the base of the transistor 31,
The input terminal 34 is connected to the base of the transistor 33, and the input terminal 42 of the reference voltage Vr1 is connected to the base of the transistor 41.

The collectors of the transistors 31 and 33 are connected to each other, the common connection point is connected to the power supply terminal 47 via the resistor 36, and the output terminal 37 is derived. The collector of the transistor 41 is connected to the power supply terminal 47 via the resistor 45, and is led out as the output terminal 46.

Assuming that the inputs supplied to the input terminals 32 and 34 are A and B, and the outputs obtained at the output terminals 37 and 46 are X and X, respectively, the above-mentioned logic circuit will have an OR gate and a NOR gate as shown in FIG. It has a gate function.

In the conventional ECL circuit, as shown in FIG. 33, the center of the logical amplitude VL between the low level (denoted as L in the following description) and the high level (denoted as H in the following description) of the inputs A and B. The level and the reference voltage Vrl are in agreement. For example, if one input of A and B is H, a current flows through one of the transistors 31 and 33, and X = H and = L.

Using two NOR gates of this ECL circuit, as shown in FIG. 34, set input S is applied to one input terminal of one NOR gate.
And the reset input R is supplied to one input terminal of the other NOR gate, and the output of each NOR gate is supplied to the other N gate.
An RS flip-flop can be formed by supplying the other input terminal of the OR gate.

FIG. 35 shows the connection of a conventional RS flip-flop, which includes transistors 31, 33, 41, a constant current source 35, and a resistor 36.
One ECL circuit is configured, and the transistors 51, 53, 61, the constant current source 55, and the resistor 56 configure the other ECL circuit. 47
Reference numerals 57 and 57 are power supply terminals.

The collector connection points of the transistors 31 and 33 are connected to the power supply terminal 47 via the resistor 36, and also serve as the output terminal 50 of the output via the emitter follower transistor 48. The emitter of the transistor 48 is connected to the power supply terminal 57 via the resistor 49 and the base of the transistor 51.

The collector connection points of the transistors 51 and 53 are connected to the power supply terminal 47 through the resistor 56, and also serve as the output terminal 70 of the output Q through the emitter follower transistor 68. The emitter of the transistor 68 is connected to the power supply terminal 57 via the resistor 69 and the base of the transistor 31.

The set input S is supplied to the base of the transistor 33, and the reset input R is supplied to the base of the transistor 53.
For example, in the reset state, when the set input S rises to H when the output Q is L and is H, a current flows through the transistor 33 and the level supplied to the base of the transistor 51 becomes L. Therefore, a current flows through the transistor 61, and the levels of the collectors of the transistors 51 and 53 become high. Therefore, the output Q rises to H and the set input S
The set state is maintained even after the switch becomes L.

D. Problems to be Solved by the Invention The RS flip-flop using the ECL circuit described above can operate at high speed because it does not cause the transistor to operate in saturation. However, the conventional ECL circuit requires the reference voltage generation circuit in order to compare the reference voltage with the input signal. In a high-speed operation logic circuit, a large amount of current is passed through each logic circuit. Therefore, in order to absorb a transient current at the time of switching, a number of reference voltage generating circuits according to the circuit scale are required.

Therefore, the conventional logic circuit has a drawback that the number of elements increases. Further, a wiring pattern for supplying the reference voltage to each logic circuit is required, and the wiring pattern occupies a large proportion on the substrate, resulting in a large chip size.

Therefore, an object of the present invention is to configure a flip-flop with a logic circuit that does not require a reference voltage, and to significantly reduce the number of elements such as transistors and resistors, thereby reducing power consumption and delay time. It is to provide a flip-flop that can be realized.

According to the present invention, the value of the constant current source of the differential amplifier can be made small when realizing the same operation speed as that of the flip-flop using the conventional ECL logic circuit. Power consumption can be extremely reduced.

Further, according to the present invention, since it is not necessary to supply the reference voltage to each gate circuit, a wiring pattern for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced.

E. Means for Solving the Problems The first invention of the present invention is the first transistor 1 and the second transistor 2 in which the respective emitters are commonly connected and the output is taken out from the collector of at least one of the transistors. A third transistor 3 having a collector connected to a common emitter connection point of the first transistor 1 and the second transistor 2, and a fourth transistor having a common connection to the second transistor 2 and a collector.
Transistor 4 and a constant current source 5 inserted between the emitter common connection point of the third transistor 3 and the fourth transistor 4 and the reference potential point.
And a third shifter via a level shift means for generating a voltage required for operating the first to fourth transistors from the collectors of the first transistor 1 and the second transistor 2 in the non-saturation region. A feedback path leading to one of the bases of the transistor 3 and the fourth transistor 4, and an input supplied to each of the base of the first transistor 1 and the base of the second transistor 2 is between a high level and a low level. Amplitudes VL are equal to each other and
The input of each of the base of the third transistor 3 and the base of the fourth transistor 4 has the same amplitude VL between the high level and the low level, VL
It is a flip-flop characterized by having a level difference of 1/2.

The second invention of the present invention is different from the above-mentioned first invention in connection of the return path. That is, the first collector 1 and the second transistor 2 are provided with a first shifter for generating a voltage necessary for operating the first and second transistors in the non-saturation region from the first collector. A feedback path to the other base of the transistor 1 or the second transistor 2 is provided.

F. Action In the first aspect of the present invention, when the state of the transistor of the upper differential pair is inverted by the trigger input, the lower differential is generated from the collector of the first transistor 1 or the collector of the second transistor 2. The feedback path to the bases of the pair of transistors inverts the state of the lower differential pair, and the state is retained even if the trigger input disappears. The inversion of this state changes the state of the lower differential pair. It is done by reversing.

In the second aspect of the present invention, when the state of the transistor of the upper differential pair is inverted by the trigger input, the feedback path from the collector of one transistor of the upper differential pair to the base of the other transistor causes: Even if there is no trigger input, the state is retained, and the reversal of this state is
This is done by reversing the state of the lower differential pair.

G. Embodiment Hereinafter, one embodiment of the present invention will be described with reference to the drawings. This one embodiment is described in G1. Configuration of the first example G2. Input and output level relationships G3. First basic connection G4. Logical connection of the first example G5. Operation of the first example G6. Second example of the present invention G7. Third example of the present invention G8. Fourth example of the present invention G9. Second basic connection and third basic connection capable of forming a flip-flop G10. RS with inhibit input Flip-flop G11. Master-slave type JI flip-flops are performed in this order.

G1. Configuration of First Example In FIG. 1, reference numerals 1 and 2 denote a pair of transistors forming an upper differential pair. Reference numerals 3 and 4 denote a pair of transistors forming the lower differential pair. The common emitter connection point of the transistors 1 and 2 is connected to the collector of the transistor 3. The common emitter connection point of the transistors 3 and 4 is connected to the power supply terminal 7 via the constant current source 5. The collector of the transistor 2 and the collector of the transistor 4 are commonly connected. The common connection point of the collector is connected to the power supply terminal 6 via the resistor 9. The sizes of the resistors 8 and 9 are equal to each other. The voltage of the power supply terminal 6 is set to be higher than the voltage of the power supply terminal 7.

The collector of the transistor 1 is connected to the power supply terminal 6 via the resistor 8.
And to the base of the transistor 10. The collector of the transistor 10 is connected to the power supply terminal 6, and the emitter of the transistor 10 is connected to the power supply terminal 7 via the diode-connected transistor 16, the resistor 17, and the constant current source 18.
Connected to. The emitter of the transistor 10 is led out as the output terminal 15 of the output Q. The connection point between the resistor 17 and the constant current source 18 is connected to the base of the transistor 4.

Input terminals 11 and 12 are derived from the base of the transistor 1 and the base of the transistor 2, respectively. Similarly,
An input terminal 13 is derived from the base of the transistor 3.

G2. Input and output level relationship The input signal supplied to the base of the transistor 1 is A, the input supplied to the base of the transistor 2 is B *, and the input supplied to the base of the transistor 3 is a. The input supplied to the base of 4 is designated b *.

When the power supply voltage is Vcc, the logic amplitude is VL, and the base-emitter voltage of the transistor is VBE, the high level Hu and the low level Lu of the input A supplied to the base of the transistor 1 are as follows. Becomes

Hu = Vcc-VBE Lu = Vcc-VBE-VL Meanwhile, the input B * supplied to the base of the transistor 2
Is the high level ▲ H ^* _u ▼ and the low level ▲ L shown by the following equations.
^{* has} _u ▼.

▲ H ^* _u ▼ = Hu−1 / 2VL ▲ L ^* _u ▼ = Lu−1 / 2VL At the base of the lower differential pair transistor 4, the collector output of transistor 1 is transistor 10, transistor 1
The input b * is provided via 6 and resistor 17. Assuming that the voltage Vs required for operating the transistors of the upper differential pair is Vs, the transistor 16 generates this voltage Vs (= VBE). Further, the resistor 17 generates a voltage drop of 1/2 VL due to the current I _{2 from the} constant current source 18. Therefore, the input signal b * applied to the base of the transistor 4 changes the value of the resistor 17 to R
Then, the following equation is obtained.

▲ H ^* _d ▼ = Vcc-VBE-Vs-I ₂ · R = Hu-Vs-1 / 2VL ▲ L ^* _d ▼ = Vcc-VBE-Vs-I ₂ · R-VL = Lu-Vs-1 / 2VL On the other hand, the input a applied to the base of the transistor 3 has a level higher by 1/2 VL than each of the high level ▲ H ^* _d ▼ and the low level ▲ L ^* _d ▼ described above. That is, Hd = ▲ H ^* _d ▼ + 1 / 2VL = Hu-Vs Ld = ▲ L ^* _d ▼ + 1 / 2VL = Lu-Vs Further, the output Q has a high level Hu and a low level Lu.

The relationship between the input level and the output level in this embodiment described above is shown in FIG. That is, the upper differential pair has an input having a logical amplitude of VL and a level difference of 1 / 2VL between the high level Hu and ▲ H ^* _u ▼ (between the low level Lu and ▲ L ^* _u ▼). A and B * are provided. The lower differential pair has an input a having a logical amplitude of VL and a level difference of 1 / 2VL between the high level Hd and ▲ H ^* _d ▼ (between the low level Ld and ▲ L ^* _d ▼). And b * are provided.

G3. First Basic Connection The first example shown in FIG. 1 is configured with the logic circuit shown in FIG. 3 as a basic connection. When the input terminal 14 is derived from the base of the transistor 4 except the feedback path from the collector of the transistor 1 to the base of the transistor 4 and the constant current source 18 in FIG. 1, the configuration of FIG. 3 is obtained.

The basic connection shown in FIG. 3 can be represented by the logical connection shown in FIG. It has a configuration of NOR gates 21 and 22 corresponding to the upper differential pair and the lower differential pair, and an OR and NOR gate 23 to which outputs of both are supplied. The output is the collector output of the transistor 1 and the output X is the collector output of the transistor 2.

G4. Logical Connection of the First Example The first example of the present invention shown in FIG. 1 has a configuration in which the collector of the transistor 1 is fed back to the base of the transistor 4. Therefore, the first example of the present invention has a configuration in which the output in FIG. 4 is supplied to the terminal of the NOR gate 22 to which b * is supplied, that is, the logical connection shown in FIG.

The logical connection shown in FIG. 5 can be rewritten into the logical connection shown in FIG. The configuration in which the respective outputs of the two NOR gates 22 and 23 are fed back to the input of the other side is nothing but the configuration of the RS flip-flop. OR via OR gate 21
The signal supplied to the gate 23 serves as a set input, and the input a supplied to the NOR gate 22 serves as a reset input.

G5. Operation of First Example The operation of the first example of the present invention will be described with reference to FIG. The input A supplied from the input terminal 11 to the base of the transistor 1 is always at low level. Therefore, the collector output of the transistor 1 becomes high level, and the set input occurs when the input B * becomes high level.

As shown in FIG. 7, when the input B * becomes high level,
High output (Vcc) of collector output of transistor 1
Becomes Therefore, the output Q becomes high level (Hu).

Along with this, the base input b * of the transistor 4 rises. When the base input b * becomes higher than the base input a (Ld) of the transistor 3, a constant current I ₁ flows through the resistor 9 and the transistor 4, and even after the set input B * falls to the low level ▲ L ^* _u ▼, The set state in which the output Q is at high level is held.

Next, as shown in FIG. 7, when the set input B * falls to the low level ▲ L ^* _u ▼ and the base input a (reset input) of the transistor 3 rises to the high level Hd, the transistors 1 and 3 are turned on. A constant current I ₁ flows through, and the output Q of the flip-flop becomes low level Lu.
At the same time, the input signal b * to the transistor 4 is ▲ L ^* _d
Therefore, even if the set input falls to the low level Ld, this state is held.

G6. Second Example of the Present Invention FIG. 8 shows a second example of the present invention. Similar to the first example, the transistor 1 and the transistor 2 form an upper differential pair, and the transistor 3 and the transistor 4
The lower differential pair is configured by. The inputs A, B *, a, and b * similar to those in the above-described first example are supplied to the bases of the transistors 1, 2, 3, and 4, respectively.

The collector of transistor 2 is the base of transistor 10.
It is connected to the base of the transistor 3 between the emitter and the diode-connected transistor 16.

The voltage drop caused by the constant current I _{1 in} each of the resistors 8 and 9 is VL and is (Vs = VBE). The emitter of the transistor 10 is taken out as the output terminal 15 of the output.

The connection shown in FIG. 8 is a logical connection for supplying the output X of the NOR gate 23 as the input of a of the NOR gate 22 as shown in FIG. Therefore, the configuration of FIG.
Converted to the logical connection shown.

In the configuration of FIG. 10, the output of the NOR gate 21 becomes the set input and the input b * becomes the reset input. The output of the NOR gate 22 is Q and the output of the NOR gate 23 is.

The operation of the second example of the present invention described above will be described with reference to FIG. Input terminal 11 on the base of transistor 1
The input A supplied from is always low level.
Therefore, the collector output of the transistor 1 becomes high level, and the set input occurs when the input B * becomes high level.

As shown in FIG. 11, when the input B * becomes high level,
The collector output X of the transistor 2 is low level (Vcc-V
L). Therefore, the output becomes low level (Lu).

At the same time, the base input a of the transistor 3 drops. When the base input a becomes lower than the base input b * (▲ H ^* _d ▼) of the transistor 4, the resistance 9 and the transistor 4
A constant current I ₁ flows through the set input B * to a low level ▲ L ^* _u
Even after falling to ▼, the set state where the output is low level is held.

Next, as shown in FIG. 11, when the set input B * falls to the low level ▲ L ^* _u ▼ and the base input b * (reset input) of the transistor 4 falls to the low level ▲ L ^* _d ▼. , A constant current I ₁ flows through the transistor 1 and the transistor 3, and the output of the flip-flop is high level Hu.
Becomes At the same time, the input signal a to the transistor 3 is
Therefore, the reset state is held even if the reset input rises to the high level ▲ H ^* _d ▼.

G7. Third Example of the Invention FIG. 12 shows a third example of the invention. Transistor 1
And the transistor 2 constitutes an upper differential pair,
The transistors 3 and 4 form a lower differential pair. The bases of these transistors 1, 2, 3, 4 are connected to the inputs A, B *, a, b similar to those in the first example described above.
Each of * is supplied.

The collector of transistor 1 is the base of transistor 10
It is connected to the base of the transistor 2 between the emitters and via the resistor 17.

The voltage drop caused by the constant current I _{1 in} each of the resistors 8 and 9 is VL, and the voltage drop caused by the constant current I ₂ in the resistor 17 is 1 / 2V.
It is set to L and (Vs = VBE). Transistor 10
The emitter of is taken out as the output terminal 15 of the output.

As shown in FIG. 13, the connection shown in FIG. 12 level-shifts the output of the NOR gate 23 so that the NOR gate 21 has a B signal.
It is a logical connection supplied as the input of *. Therefore, the configuration shown in FIG. 13 is converted into the logical connection shown in FIG.

In the configuration of FIG. 14, the input A becomes the set input, and the output of the NOR gate 22 is reset. The output of NOR gate 23 is Q
Then, the output of the NOR gate 21 is.

The operation of the above-described third example of the present invention will be described with reference to FIG. When the input B * supplied to the base of the transistor 2 is at a high level and the input A (set input) is at a high level Hu, a constant current I ₁ flows through the transistor 1 and the transistor 3, and the collector output of the transistor 1 Becomes low level.

Therefore, the output becomes the low level Lu, and the input B * supplied to the base of the transistor 2 via the transistor 10 and the resistor 17 drops to the low level ▲ L ^* _u ▼. The input a supplied to the base of the transistor 3 is at high level
Input b, which is Hd and is supplied to the base of the transistor 4.
* Is a high level ▲ H ^* _d ▼. Therefore, when input A rises, transistor 1 and transistor 3
A constant current I ₁ flows through. Input B * is low level ▲ L
By falling to ^* _u ▼, even if the input A falls, the set state where the output is low level Lu is held.

Next, as shown in FIG. 15, when the reset input a falls to the low level Ld, the input b * is always at the high level ▲ H ^* _d.
Since ▼ is set, the constant current I ₁ flows through the transistor 4 and the resistor 9. Therefore, the output of the flip-flop becomes high level Hu. Along with this, transistor 2
The input signal B * to the signal rises to ▲ H ^* _u ▼, and therefore this reset state is held even when the reset input rises to the high level Hd.

G8. Fourth Example of the Invention FIG. 16 shows a fourth example of the invention. Transistor 1
And the transistor 2 constitutes an upper differential pair,
The transistors 3 and 4 form a lower differential pair. The bases of these transistors 1, 2, 3, 4 are connected to the inputs A, B *, a, b similar to those in the first example described above.
Each of * is supplied.

The collector of transistor 2 is the base of transistor 10.
It is connected to the base of the transistor 1 via the emitter. The voltage drop caused by the constant current I _{1 in} each of the resistors 8 and 9 is V
It is said to be L. The emitter of the transistor 10 is taken out as the output terminal 15 of the output Q.

The connection shown in FIG. 16 is a logical connection for supplying the output X of the NOR gate 23 as the input of A of the NOR gate 21 as shown in FIG. Therefore, the configuration of FIG.
Converted to the logical connection shown.

In the configuration of FIG. 18, the input B * serves as a set input and the output of the NOR gate 22 serves as a reset input. The output of the NOR gate 21 is and the output of the NOR gate 23 is Q.

The operation of the above-described fourth example of the present invention will be described with reference to FIG. When input A supplied to the base of transistor 1 is low level Lu, input B * (set input)
Is set to a low level (L ^* _u) , a constant current I ₁ flows through the transistors 1 and 3, so that the collector output of the transistor 1 becomes low level and the collector output X of the transistor 2 becomes high level.

Therefore, the output Q becomes the high level Hu and the input A supplied to the base of the transistor 1 via the transistor 10 rises to the high level Hu. The input a supplied to the base of the transistor 3 is at a low level Ld, and the input b * supplied to the base of the transistor 4 is at a low level ▲ L ^* _d ▼. Therefore, when the input A becomes high level, the constant current I ₁ flows through the transistors 1 and 3. Since the input A rises to the high level Hu, the set state where the output Q is the high level Hu is held even if the input B * rises.

Next, as shown in FIG. 19, when the reset input b * rises to the high level ▲ H ^* _d ▼, the input a is always at the low level.
Since it is Ld, the constant current I ₁ flows through the transistor 4 and the resistor 9. Therefore, the output Q of the flip-flop becomes the low level Lu. Along with this, transistor 1
The input signal A to L falls to Lu, and thus this reset state is held even when the reset input falls to Ld.

G9. Second basic connection and third basic connection capable of forming a flip-flop The RS flip-flop described above is composed of the first basic connection of the logic circuit shown in FIG. However, the present invention can also be configured from the second or third basic connection of the logic circuit described below.

FIG. 20 shows the second basic connection. As can be understood by comparing FIG. 3 and FIG. 20, the logic circuit of FIG. 20 has the inputs of the transistors 3 and 4 of the lower differential pair in the opposite relationship. That is, the input b * is added to the base of the transistor 3 and the input a is added to the base of the transistor 4.

FIG. 21 shows the third basic connection. As can be understood by comparing FIG. 3 with FIG. 21, the logic circuit of FIG. 21 has the inputs of the transistors 1 and 2 of the upper differential pair in the opposite relationship. That is, the input B * is added to the base of the transistor 1 and the input A is added to the base of the transistor 2.

G10. RS flip-flop with inhibit input FIG. 22 shows an example of an RS flip-flop with inhibit input constructed according to the present invention. The set input and reset input of the fourth example of the flip-flop shown in FIG. 16 are selectively supplied by the control input INH.

An RS flip-flop is formed by the transistors 1, 2, 3, 4, 10 and the constant current sources 5, 18 and the resistors 8, 9. Transistor 2
The set input (B *) is supplied from the terminal 12 to the base of
Reset input from terminal 14 to the base of transistor 4 (b
*) Is supplied. Output is taken from the collector of transistor 1 and output X from the collector of transistor 2.
Is taken out.

A transistor 19 is provided in which the transistor 2 and the emitter and the collector are commonly connected. Between the power supply terminals 6 and 7, the collector / emitter path of the transistor 25 and the resistor 2
6, the series connection of the resistor 27 and the constant current source 28 is inserted. Control input IN to terminal 29 connected to the base of transistor 25
H is supplied. The connection point of the resistors 26 and 27 is connected to the base of the transistor 19. The connection point between the resistor 27 and the constant current source 28 is connected to the base of the transistor 3.

The control input INH has a high level H and a low level L, and has Hu and Lu at the emitter of the transistor 25. The voltage drop of the resistor 26 is 1/2 VL, and the voltage drop of the resistor 27 is (Vs-1 / 2VL).

The connection shown in FIG. 22 has the logic connection shown in FIG. 23, where C * is the input supplied to the base of transistor 19. In FIG. 23, the NOR gates 21, 22, and 23 are connected as shown in FIG.
Similar to Figure 7. The transistor 2 whose collector and emitter are commonly connected constitutes a NOR gate 24 to which B * and C * which is a level-shifted control input INH are input, and the output of the NOR gate 24 is input A.
It is also supplied to the NOR gate 21.

The logical connection shown in FIG. 23 can be represented like the logical connection shown in FIG. Here, the input C * is a level-shifted version of the control input INH. Therefore, the 24th
As shown in the figure, input B * (set input) and input b *
(Reset input) and a flip-flop with a prohibition input are turned on / off according to the control input INH.

FIG. 26 is a waveform of each part showing the operation of the above-mentioned flip-flop with prohibition input. When the control input INH is at the low level, that is, when the input C * is at the low level ▲ L ^* _u ▼, this waveform diagram is similar to the above-mentioned waveform diagram of FIG. Control input
When INH becomes the high level H, the current I ₁ is fixed to the state where it flows through the transistor 19 and the transistor 3, and the set and reset inputs are prohibited.

G11. Master-Slave Type JK Flip-Flop A master-slave type JK flip-flop constructed according to the present invention will be described. FIG. 27 shows the logical connection of JK flip-flops. The NOR gates 71 and 72 form a master stage flip-flop, and a gate circuit including NOR gates 73 and 74 is provided for the master stage. Outputs Q ₁ and ₁ of the master stage are NOR gates
NOR gates 75 and 7 via a gate circuit consisting of 77 and 78
It is supplied to a flip-flop of 6 slave stages. Outputs Q ₂ and ₂ from the flip-flop in the slave stage
Is taken out.

The NOR gate 73 is supplied with the inputs of A, B and C * (inverted). Input A is output Q ₂ and input B is
Input C * is clock ▲ ▼ *.
The NOR gate 74 is supplied with a *, b *, and c * inputs.
The input a * is the clock CK, the input b * is the input, and the input c * is the output ₂ .

The NOR gate 77 is supplied with D * and E * inputs,
Gate 78 is supplied with the inputs of d and e * (inverted). The input D * is the clock ▲ ▼ *, the input e * is the clock CK *, the input d is the output Q ₁ of the master stage, and the input E * is the level ₁ of the output ₁ of the master stage. It is a thing.

The gate circuit added to the input side of the master and slave stages causes the clock CK to go low (clock
When the ▼ is high level, input or input is possible to the master stage, and when the clock ▲ ▼ is low level (clock CK is high level), the output of the master stage and slave stage can be input.

At (= L) (= H), when the clock ▲ ▼ rises to the high level, the flip-flop of the master stage is set and (Q ₁ = H) ( ₁ = L). Next, when the clock ▲ ▼ falls to the low level, the flip-flop of the slave stage is set, and (Q ₂ = H) ( ₂ =
L). Therefore, the reset state changes to the set state.

At (= L) (= H), when the clock ▲ ▼ rises to the high level, the flip-flop in the master stage is reset and becomes (Q ₁ = H) ( ₁ = L). Next, when the clock ▲ ▼ falls to the low level, the flip-flop of the slave stage is reset, and (Q ₂ = H) (
₂ = L). Therefore, the set state changes to the reset state.

The concrete connection of the master-slave type JK flip-flop described above is shown in FIG.

The flip-flop of the master stage and the gate circuit on the input side thereof are composed of transistors 81, 82, 83, 86, 87, 88, 89, 93, 97. An upper differential pair is configured by the transistors 81 and 82 and the transistor 83 whose collectors and emitters are commonly connected. An input (input B) is supplied to a terminal 84 derived from the base of the transistor 82. Transistors 86, 87, whose collector and emitter are connected together
The lower differential pair is composed of 88 and the transistor 89. The input is supplied to a terminal 85 derived from the base of the transistor 87. A constant current source 90 is connected to the lower differential pair, and resistors 91 and 92 are connected between the upper differential pair and the power supply terminal 6.

Inputs A, B and C * are supplied to the bases of the transistors 81, 82 and 83, respectively. The inputs a *, b *, and c * are supplied to the bases of the transistors 86, 87, and 88, and the input f is supplied to the base of the transistor 89. The input b * is an input and the input a * is a clock CK *. Clock CK * is an input terminal
The clock ▲ ▼ * is supplied from the input terminal 101.

The collector of the transistor 83 and the collector of the transistor 88 are connected. Transistor 93 produces the output of the master stage at its emitter. A series connection of resistors 94 and 95 and a constant current source 96 is inserted between the emitter of the transistor 93 and the power supply terminal 7. The voltage drop of the resistor 94 is 1 / 2VL, and the voltage drop of the resistor 95 is (Vs-1 / 2VL).
The input f supplied to the base of the transistor 89 is ₁
It is a level-shifted version of Vs.

The flip-flop in the slave stage and the gate circuit on the input side thereof are composed of transistors 102, 103, 104, 105, 106, 110, 112. With the transistors 102, 103 and the transistor 104 whose collectors and emitters are commonly connected,
The upper differential pair is constructed. A lower differential pair is configured by the transistors 106 and 105 whose collectors are commonly connected to the transistors 102 and 103. A constant current source 107 is connected to the lower differential pair, and resistors 108 and 109 are connected between the upper differential pair and the power supply terminal 6.

The base input E * of the transistor 102 is obtained by shifting the output ₁ of the master stage by 1 / 2VL level.
The base input D * of 03 is the clock ▲ ▼ *, and the base input F of the transistor 104 is the output Q _{2 of the} slave stage.
Is. The base input d of the transistor 105 is the output Q _{1 of the} master stage level-shifted by Vs. The base input e * of the transistor 106 is the clock CK *.

Output Q ₂ is generated at the emitter of transistor 110 to which constant current source 111 is connected, and output at the emitter of transistor 112
₂ occurs. The output Q ₂ is supplied to the base of the transistor 81 in the master stage, and the output ₂ is supplied to the resistor 113 and the constant current source 114.
Is level-shifted by (Vs + 1 / 2VL) and supplied to the base of the transistor 88 in the master stage.

The waveform of each part of the above JK flip-flop is shown in Fig. 29 and
Shown in Figure 30. FIG. 29 shows a set operation, and FIG. 30 shows a reset operation.

In the reset state, as shown in FIG. 29, outputs ₁ and
₂ is high level, and outputs Q ₁ and Q ₂ are low level. The input of the flip-flop of the master stage is the 29th
It has the level relationships shown on the left side of the figure. A current flows through the resistor 92, the transistor 82, and the transistor 89.

When the inputs are set to the high level and the inputs are set to the low level, and the clock ▲ ▼ * rises, a current flows through the resistor 91 and the transistor 83, and the output ₁ falls to the low level. This causes the input f of the transistor 89 to fall. Base input of transistor 87 b *
Since () is at a high level, a current flows through the transistor 87. This state is held even when C * (clock ▲ ▼ *) becomes high level and the input becomes high level.

Next, the operation of the slave stage will be described with reference to FIG.
Clock ▲ ▼ * (base input D of transistor 102
When *) falls, current does not flow through the transistor 103, and the output Q ₂ becomes high level. Therefore, the base input F of the transistor 104 rises and a current flows through the resistor 109, the transistor 104 and the transistor 105.
This set state does not change even after the clock ▲ ▼ * goes low.

The reset operation will be described with reference to FIG. In the set state, as shown in FIG. 30, the outputs Q ₁ and Q ₂ are at high level and the outputs ₁ and ₂ are at low level. The inputs of the flip-flops in the master stage have the level relationship shown on the left side of FIG. A current is flowing through the resistor 91, the transistors 86 and 87.

When the input and are at the high level, the input is set to the low level, and when the clock CK * falls, a current flows through the resistor 92, the transistors 81, 82 and the transistor 89,
Output Q ₁ falls to low level and output ₁ rises to high level. This causes the base input f of the transistor 89 to rise. Therefore, the current flows through the transistor 89. This state is held even when C * (clock ▲ ▼ *) becomes high level and the input becomes high level.

Next, the operation of the slave stage will be described with reference to FIG.
Clock ▲ ▼ * (base input D of transistor 102
When *) falls and the clock CK * (base input e * of the transistor 106) rises, a current flows through the resistor 108 and the transistor 106, and the output Q ₂ becomes low level. Therefore, the base input F of the transistor 104 goes down, and the output ₂ goes high. This reset state does not change even after the clock ▲ ▼ * becomes low level.

The master-slave type JK flip-flop described above has advantages that it does not require an extra gate, has a small number of elements, and can operate at high speed.

H. Effect of the Invention According to the present invention, it is possible to configure a flip-flop in which a transistor does not perform a saturation operation, like the ECL circuit. The present invention does not require a reference voltage, unlike the conventional ECL circuit. Therefore, it is not necessary to provide a reference voltage generation circuit, the number of elements is small, and wiring for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced. Further, when realizing an operating speed similar to that of the conventional ECL circuit, the value of the constant current source of the differential pair can be reduced, so that power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a connection diagram of a first example of the present invention, FIG. 2 is a schematic diagram showing an input level relationship in the present invention, and FIG. 3 is a connection diagram of a first basic connection of the present invention. FIG. 7 is a logic circuit diagram of a first basic connection of the present invention, FIGS. 5 and 6 are logic circuit diagrams showing a logic connection of the first example of the present invention, and FIG. 7 is a first example of the present invention. 8 is a waveform diagram of each part for explaining the operation of FIG. 8, FIG. 8 is a connection diagram of the second example of the present invention, FIGS. 9 and 10 are logic circuit diagrams of the second example of the present invention, and FIG. Waveform diagrams of respective parts for explaining the operation of the second example of the invention, FIG. 12 is a connection diagram of the third example of the invention, and FIGS. 13 and 14 are logic circuit diagrams of the third example of the invention. FIG. 15 is a waveform diagram of each part for explaining the operation of the third example of the present invention, FIG. 16 is a connection diagram of the fourth example of the present invention, and FIGS. 17 and 18 are the fourth diagram of the present invention.
FIG. 19 is a waveform diagram of each part for explaining the operation of the fourth example of the present invention, and FIGS. 20 and 21 are the second basic connection and the third example of the present invention, respectively. FIG. 22 is a connection diagram showing each basic connection, FIG. 22 is a connection diagram of a flip-flop with a prohibition input to which the present invention is applied, and FIGS. 23, 24 and 25 are for explaining a flip-flop with a prohibition input. FIG. 26 is a waveform diagram of each part for explaining the operation of a flip-flop with an inhibit input, FIG. 27 is a logic circuit diagram of a master-slave type JK flip-flop to which the present invention is applied,
FIG. 28 is a connection diagram of this JK flip-flop, FIGS. 29 and 30 are waveform diagrams for explaining the set operation and reset operation of the master-slave JK flip-flop, and FIG. 31 is a conventional ECL circuit. Fig. 32 shows the conventional E
Logic circuit diagram of CL circuit, Fig. 33 is a schematic diagram showing the input level relationship of the conventional ECL circuit, Fig. 34 is a logic circuit diagram of a conventional flip-flop, and Fig. 35 is a connection diagram of a conventional flip-flop. Is. Description of main symbols in the drawings 1: first transistor, 2: second transistor, 3: third
, 4th transistor, 5 and 18 are constant current sources, and 6 and 7 are power supply terminals.

Claims (2)

[Claims] 1. A first transistor (1) and a second transistor (2) whose emitters are commonly connected and whose output is taken out from the collector of at least one transistor, and said first transistor (1). And a third transistor (3) whose collector is connected to the common emitter connection point of the second transistor (2), and a fourth transistor (4) whose common collector is connected to the second transistor (2). ), A constant current source (5) inserted between a common emitter connection point of the third transistor (3) and the fourth transistor (4) and a reference potential point, and the first transistor (1) And the level shift means (1) from one collector of the second transistor (2).
A feedback path reaching one of the bases of the third transistor (3) and the fourth transistor (4) via 6), and the base of the first transistor (1) and the second transistor (1). The inputs (A) and (B *) supplied to the bases of the transistors (2) have the same amplitude (VL) between the high level and the low level and have a half of the above amplitude (VL). The input (a) and (b *) of the third transistor (3) and the base of the fourth transistor (4), respectively. The amplitudes (VL) between the high level and the low level are equal to each other, and they have a level difference (1 / 2VL) of 1/2 of the amplitude (VL) with each other, and the bases of the first and second transistors respectively. The inputs (A) and (B *) supplied are the third and fourth described above. A flip-flop having a voltage difference required for operating the first and second transistors in a non-saturation region with respect to inputs (a) and (b *) respectively supplied to the base of the transistor. Pu. 2. A first transistor (1) and a second transistor (2) whose emitters are commonly connected and whose output is taken out from the collector of at least one transistor, and said first transistor (1). And a third transistor (3) whose collector is connected to the common emitter connection point of the second transistor (2), and a fourth transistor (4) whose common collector is connected to the second transistor (2). ), A constant current source (5) inserted between a common emitter connection point of the third transistor (3) and the fourth transistor (4) and a reference potential point, and the first transistor (1) And the level shift means (1) from one collector of the second transistor (2).
0) via a feedback path to the other base of the first transistor (1) and the second transistor (2), and the base of the first transistor (1) and the second transistor (1). The inputs (A) and (B *) supplied to the bases of the transistors (2) have the same amplitude (VL) between the high level and the low level and have a half of the above amplitude (VL). The input (a) and (b *) of the third transistor (3) and the base of the fourth transistor (4), respectively. The amplitudes (VL) between the high level and the low level are equal to each other, and they have a level difference (1 / 2VL) of 1/2 of the amplitude (VL) with each other, and the bases of the first and second transistors respectively. The inputs (A) and (B *) supplied are the third and fourth described above. A flip-flop having a voltage difference required for operating the first and second transistors in a non-saturation region with respect to inputs (a) and (b *) respectively supplied to the base of the transistor. Pu.