JPH0732379B2 - Pseudo-sync prevention circuit - Google Patents

Description

The present invention relates to a pseudo-synchronization prevention circuit that establishes frame synchronization in a digital multiplex converter, and relates to a pseudo-synchronization prevention method that does not occur in pseudo-synchronization. For the purpose of ensuring synchronization at the bit position, the sub-bit is inserted on the transmitting side and extracted on the receiving side to confirm the establishment of frame synchronization.
A desired bit among the sub-bits is scrambled to generate a '10' alternating signal of '1' and '0' and '1100' of '11' and '00'.
The transmission side includes a 10 alternation / 1100 alternation generator that generates an alternation signal and a sub-bit superimposing unit that superimposes both the alternation signals of '10' and '1100' on the original position where the sub-bit existed. In the receiving side, further, the sub-bit separation unit for separating the '10' alternation number and '1100' alternation number from the sub-bit output from the sub-bit superimposing unit, and the '10' alternation signal and '. A 10-alternating / 1100-alternating decoding unit for decoding the 1100 'alternating signal into the specific bits is provided, and by using the scrambled specific bits when performing the data conversion process, it is configured so that pseudo synchronization is not generated.

[Industrial application field]

The present invention relates to a pseudo sync prevention circuit that establishes frame synchronization in a digital multiplex converter.

[Conventional technology]

FIG. 8 is a diagram showing a frame structure of a conventional example. FIG. 9 is a diagram showing a pseudo-synchronized state of the conventional example. In the frame phase synchronization method for backbone data transmission in a digital multiplexer, 12 subframes form one frame as shown in FIG. 8, and each subframe has 18 words of 6 bits. To be equipped with. In addition, SC, RMT, SVC, EX are added to the last bit of each word.
Each of the sub-bits of OW and SC is transmitted by superimposing one bit at the same interval. The synchronization bits F ₁ and F ₀ (F ₁
= '1' and F ₀ = '0') are also superimposed at the same position for frame synchronization. The sub-bits other than F ₁ and F _{0 have} a value of “1” or “0” as follows.

OW signal This bit is used for carrying communication for carrying voice, and is set to '1' when transmitting voice.

SC signal This bit is used as a switching control signal with the monitoring device, and may be fixed to '1' when the monitoring device is not connected or when switching control is not sent even if it is connected. If fixed to "1", pseudo synchronization may occur.

RMT signal Alternately, when there is no transmission from the opposite station = '0', and when transmitting = 1,0.

SVC signal No response signal from the monitoring device Normal =
'1', sending = '0'.

EXOW signal Normally, it is a spare bit and is used as "1" or "0" depending on the user, but if it is fixed to this "1", pseudo synchronization may occur.

FIG. 9 is a diagram showing a pseudo synchronization state of the conventional example. Normally, frame synchronization in a normal state is established at the F ₁ = '1' and F ₀ = '0' positions shown in FIG. 9A, and data can be accurately received. However, in particular, there is a high possibility that the SC signal and the EXOW signal will be fixed to '1' as described above, and in this case, the SC signal as shown in FIGS. 9 (b) and 9 (c). And when the EXOW signal becomes '1', a position different from the original frame bit, that is, SC = in FIG. 9 (b).
'1', RMT = '0' and EXOW = '1', SC = in Fig. 9 (c).
Frame synchronization may be established at the position of "0", so that accurate transmission / reception of the sub signal bit cannot be performed.

[Problems to be Solved by the Invention]

Therefore, there is a problem that frame synchronization may be established at a position different from the original frame bit, and accurate transmission / reception of the sub signal bit cannot be performed.

The present invention relates to a pseudo-synchronization prevention method that does not occur in pseudo-synchronization, and an object thereof is to ensure synchronization at a frame bit position regardless of the state of sub-bits.

[Means for Solving the Problems]

In the present invention, the transmitting side inserts a sub-bit, and the receiving side extracts the sub-bit to confirm the establishment of frame synchronization.In the sub-bit, the desired bit is scrambled to '1' and '0's' 10 'alternating signal and' 11 'and' 0
A 10 alternation / 1100 alternation generation unit 14 that generates a '1100' alternation signal of 0 ', and a sub-superimposing both the alternation signals of' 10 'and' 1100 'at the original position where the sub-bit existed. Bit superposition section
12 is provided on the transmitting side, and further, on the receiving side, from the sub-bit output from the sub-bit superimposing unit 12, the alternation number '10' and '1'.
A sub-bit separation unit 24 that separates the 100 'alternating signal and a 10 alternating / 1100 alternating decoding unit 25 that decodes the' 10 'alternating number and the' 1100 'alternating signal to the specific bit is provided, and the data conversion processing is performed. By using the scrambled specific bit when performing, pseudo synchronization is configured not to occur.

[Work]

In the present invention, as shown in FIG. 1, by inputting a specific bit of the sub-bits to 10 alternation / 1100 alternation generation section 14 and scrambling, 10 alternation signals and 1100 alternation signals are output. The alternating signal is input to the sub-bit superimposing unit 12 so that it is superposed at the 1-bit position of the data string,
Further, the 10 alternating signal and the 1100 alternating signal among the received sub-bits are input to the sub-bit separating section 24 to be decoded into desired specific bits and output.

Therefore, when performing data processing on the sending side and the receiving side,
It is possible to prevent the pseudo synchronization from occurring.

〔Example〕

FIG. 1 is a diagram showing a circuit configuration of the present invention, FIG. 2 is a circuit diagram of a 10-alternating / 1100-alternating generator of the present invention, and FIG. It is a figure. 4 to 7 are diagrams showing the frame state (sub-bits) of the present invention, FIG. 4 is a diagram showing the transmission conditions of the RMT signal and SVC signal, and FIG. 5 is the frame configuration of the present invention. FIG. 6 is a diagram showing an example, FIG. 6 is a diagram for explaining a synchronization state in the present invention,
Further, FIG. 7 is a diagram showing a synchronization state of the RMT signal and the SVC signal in the present invention. In the present invention, in order to prevent the pseudo-synchronization that occurs in the frame of the conventional example, the circuit configuration shown in FIGS. 1 to 3 is used to superimpose sub-bits, and FIGS. The frame structure is as shown in FIG.

In the present invention, as shown in FIG. 4, the transmission conditions of the RMT signal and the SVC signal are set, that is, the alternating signal of "1" and "0" is used in the normal state, and "11" and "00" are transmitted in the transmitting state. The alternating signals of are superimposed on each other.

As shown in FIG. 5, the order of the SVC signal, the OW signal, and the EXOW signal in the conventional sub-bit array is changed to the EXOW signal,
Make the frame structure in the order of OW signal and SVC signal.

By realizing these two conditions, pseudo synchronization cannot be performed. By converting the SMT signal and the SVC signal as described above, the configuration of each sub-signal bit has the relationship shown in FIGS. 5 and 6. In FIGS. 5 and 6, the OW signal is a voice and is not fixed at the DC level, so that it is not considered.

As shown in FIGS. 5, 6 and 7, the following five cases of ~ as shown in FIG. 6 can be considered as the frame conditions in which synchronization and pseudo synchronization occur.

A synchronous normal operation of the synchronous in this state of F ₁ -F _0, always'1'
When it is '0', the frame is synchronized.

Synchronization of SC-RMT Even if SC = '1', since RMT always operates at '10' or '1100', no pseudo synchronization occurs.

Synchronization of RMT-SVC As shown in Fig. 7, both RMT and SVC have alternating data of "1" and "0" or alternating data of "11" and "00". As shown in the figure, A (normal),
Four patterns of B (at the time of sending), C (at the time of normal), and B (at the time of sending) can be considered. As for A, B, C and D, it becomes '1' and '0' at the places marked with *, and it is sure to enter the synchronization. However, the frequency is once in four times, and if the synchronization state is judged only when 5 times are consecutively repeated "1" and "0" by applying the synchronization protection, the synchronization is always lost and the pseudo synchronization is not generated. It cannot happen and is therefore not treated as a synchronization establishment.

EXOW-F ₁ F ₁ is always '1', so the sync state of '1' and '0' does not occur, and pseudo sync does not enter.

Even if SVC-SC SC = "0", SVC is always "10" or "1100".
Since it is running on, pseudo sync does not occur.

FIGS. 1 to 3 are circuits for making the signals shown in FIGS. 4 to 7 so that the pseudo-synchronous state does not occur.

FIG. 1 is a diagram showing a circuit configuration of the present invention. 11 to 14 are circuits on the transmitting side, and 21 to 25 are circuits on the receiving side.

In a backbone data transmission system in which parallel-to-serial converted input data is transmitted and received data is received by serial-to-parallel conversion as shown in FIG. 1, a plurality of parallel input data is converted from parallel-to-serial. After being input to the unit 11 and converted into serial data, it is sent out to the receiving side via the transmission line 20, and at the receiving side, the received serial data is converted into parallel data by the serial-parallel conversion unit 21 and is output data. I am sending it out. Parallel of such data −
When performing serial conversion processing and serial-parallel conversion processing, frame synchronization is of course necessary. Therefore, on one transmission side, the reference pulse from the transmission pulse generation unit 13
1100 Input to the alternation generator 14, for example RM which is a specific bit
The T signal and the SVC signal are converted into the RMT alternating signal and the SVC alternating signal and output to the sub-bit superimposing unit 12. Then, the sub-bit superimposing unit 12 superimposes the RMT alternating signal and the SVC alternating signal as sub-bits on 1 bit of the data string once every 18 words of the input data and inputs them to the parallel-serial conversion unit 11. .

On the receiving side, the sub-bits in the final column of the parallel output data output from the serial-parallel converter 21 are input to the sync separator 22 and the sub-bit separator 24, respectively. Then, the sync separator 22 separates the sync bits into F ₁ and F ₀ . Further, in order to decode the RMT signal and the SVC signal which are specific bits, the separated synchronization bits of F ₁ and F ₀ are input to the reception side pulse generation unit 23 to generate a reference pulse, and this reference pulse is used. The RMT alternating signal and SVC alternating signal separated by the sub-bit separation unit 24 are not output as they are, but 10 alternating and 1
100 Alternate decryption unit 25'10 'Alternate data or' 1100 '
The transmitted data is discriminated by discriminating whether it is an alternation or not, and is output as an RMT signal and an SVC signal of specific bits.

FIG. 2 is a circuit diagram of the 10-alternating / 1100-alternating-alternating portion of the present invention, which corresponds to the circuit block 14 of FIG. A clock that repeats "1" and "0" and an RMT signal or SVC signal that repeats "1" and "0" are input to this circuit, and the output at each point is as follows.

Clock (a) 10101010 ... First FF output (b) 01010101 ... Second FF output (c) 11001100 ... RMT signal or SVC signal (d) 10101010 ... Selector output (e) RMT = SVC = 1 01010101 ..RMT = SVC = 011001100 .. That is, the output (e) from the selector 33 is 10 alternations or 11
00 Get the police box.

Further, FIG. 3 is a circuit diagram of the 10-alternating / 1100-alternating-decoding unit of the present invention, which corresponds to the circuit block 25 of FIG. This circuit has a clock that repeats "1" and "0" and "10" or "1".
The RMT alternating signal of 100 'or the received signal of the SVC alternating signal is input, and the output of each point is as follows.

(1) When the received signal is an alternation of '10' Received signal (a) 10101010 ... Clock (b) 10101010 ... First FF output (c) 01010101 ... Second FF output (d) 10101010 ... Third FF Output (e) 01010101 ... First EOR circuit output (f) 11111111 ... (and second EOR circuit output (g)) That is, a DC output of level '1' is obtained.

Next, (2) When the received signal is an alternation of '1100' Received signal (a) 11001100 ... Clock (b) 10101010 ... First FF output (c) 01100110 .. Second FF output (d) 00110011 .. Third FF output (e) 10011001 ... First EOR circuit output (f) 00000000 ... (Second EOR circuit output (g)) That is, a DC output of level '0' is obtained.

As described above, in the present invention, on the transmitting side, the level of "1" or "0" is changed from the DC RMT signal or SVC signal to "1".
RMT alternating signal or SVC alternating signal of 0'alternating or '1100' alternating is generated and superimposed as a sub-bit to avoid pseudo synchronization, and on the receiving side, opposite to the transmitting side, '10' alternating or '1100' alternating Input the RMT alternating signal or SVC alternating signal of, and the required RMT signal or SVC while avoiding pseudo synchronization.
The signal is decoded and output.

〔The invention's effect〕

As is clear from the above description, according to the present invention, the pseudo synchronization between the sub-signal bits, which has been conventionally generated, does not occur, and the synchronization at the positions of the normal synchronization bits F ₁ and F ₀ is It is important to enable the establishment and contribute to the improvement of the reliability of the frame synchronization circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of the present invention, FIG. 2 is a circuit diagram of a 10 alternation / 1100 alternation generation unit of the present invention, and FIG. 3 is a circuit diagram of a 10 alternation / 1100 alternation decoding unit of the present invention. FIG. 4 is a diagram showing transmission conditions of an RMT signal and an SVC signal, FIG. 5 is a diagram showing an example of a frame structure of the present invention, FIG. 6 is a diagram showing a synchronization state in the present invention, and FIG. 8 is a diagram showing a synchronization state of an RMT signal and an SVC signal in FIG. 8, FIG. 8 is a diagram showing a frame structure of a conventional example, and FIG. 9 is a diagram showing a pseudo synchronization state of the conventional example. In the figure, 11 is a parallel-serial conversion unit, 12 is a sub-bit superposition unit, 13 is a transmission side pulse generation unit, 14 is a 10-alternative / 1100 alternating-current generation unit, 21 is a serial-parallel conversion unit, 22 is a sync separation unit, Reference numeral 23 is a receiving-side pulse generation unit, 24 is a sub-bit separation unit, and 25 is a 10-alternating / 1100-alternating-decoding unit.

Claims (1)

[Claims] 1. A method for confirming establishment of frame synchronization by inserting a sub-bit at a transmitting side and extracting the sub-bit at a receiving side, wherein a desired bit among the sub-bits is scrambled to "1". Alternating signal of '0''10' and '11' and '00''1100'
10 alternation and 1100 alternation generators that generate alternating signals (14)
And a sub-bit superimposing section (12) for superimposing the alternating signals of '10' and '1100' on the original position where the sub-bit existed.
Is provided on the transmitting side, and further on the receiving side, a sub-bit separating section (24) for separating the "10" alternating number and the "1100" alternating number from the sub-bit output from the sub-bit superposing section (12). And decoding from the '10' alternating signal and the '1100' alternating signal to the specific bit 1
A pseudo-synchronization prevention circuit, characterized in that a 0-alternating / 1100 alternating-decoding section (25) is provided and pseudo-synchronization is not generated by using the scrambled specific bits when performing data conversion processing.