JPH0734451B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device applied to manufacture a memory cell of an MIS type dynamic RAM.

[Conventional technology]

Conventionally, a dynamic RAM (hereinafter referred to as DRAM) cell structure is a planar type cell in which a thermal oxide film is used as a dielectric material to form a planar capacitor with a silicon substrate and polycrystalline silicon.
Grooves are formed in a silicon substrate, impurities are doped into the sidewalls and bottom surfaces of the trenches to form a capacitor between the buried polysilicon and the sidewalls of the trench, or polycrystalline silicon is directly grown on the drain, and thermal oxidation is performed. There is a stacked capacitor type cell in which a second polycrystalline silicon layer is formed and a capacitor is formed between the polycrystalline silicon layers.

A conventional manufacturing method of the stacked capacitor type cell will be described with reference to FIG.

A field oxide film 2 and a gate oxide film 3 are formed on the surface of a P-type silicon substrate 1, a polycide gate electrode 4 is arranged as a gate electrode, and an N-type impurity (for example, As) is self-deposited on the polycide gate electrode 4. The source diffusion layer 5 and the drain diffusion layer 6 are formed in alignment with each other by high-dose ion implantation. Next, after forming an interlayer insulating film 7 and opening a drain contact region, a layer of polycrystalline silicon 8 doped with an impurity (for example, P) is grown (FIG. 2 (a)). Further, the electrode region of the capacitor is formed by dry etching, and polycrystalline silicon 8 is used as the dielectric material of the capacitor.
The thermal oxide film 10 is formed by oxidizing (FIG. 2 (b)). Further, a polycrystalline silicon layer 11 doped with an impurity (for example, P) is formed as an upper electrode of the capacitor, an interlayer insulating film 12 is formed, a contact is made with the source diffusion layer 5, and a bit line 13 is formed (FIG. 2). (C)).

[Problems to be solved by the invention]

In the DRAM cell structure to which the above-described conventional method for manufacturing a semiconductor device is applied, since the polycrystalline silicon 8 which is the lower electrode of the capacitor is thin, the capacitance of the sidewall of the polycrystalline silicon 8 is small and the total area of the capacitor is increased. In order to increase the number, it is necessary to make the area of the polycrystalline silicon 8 large, and there is a drawback that miniaturization is difficult.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a source and a drain by introducing an impurity of a second conductivity type onto a semiconductor substrate of a first conductivity type, and the first step of forming these source and drain. A step of forming an interlayer insulating film on a conductive type semiconductor substrate; a step of forming an opening for a drain contact region in the interlayer insulating film; and a low pressure chemical vapor deposition on the opening and the interlayer insulating film. Growing a first polycrystalline semiconductor layer to a thickness of three times or more the depth of the opening by a method to form a flat surface of the first polycrystalline semiconductor layer; A groove is formed in the first polycrystalline semiconductor on the drain region so as not to reach the drain by etching, and the unnecessary first polycrystalline semiconductor is formed.
Of removing the polycrystalline semiconductor, the step of thinly oxidizing the remaining surface of the first polycrystalline semiconductor to form an oxide film, and the step of forming a second polycrystalline semiconductor layer on the oxide film. And forming a capacitive element.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a drawing showing, in the order of steps, vertical cross-sectional views of a cell structure of a DRAM to which an embodiment of the present invention is applied.

The drain contact region of the interlayer insulating film 7 is opened (FIG. 1 (a)). The depth of the drain opening is about 8000Å, and when a layer of polycrystalline silicon 8 is grown to a thickness of 3 μm by LPCVD, the surface of polycrystalline silicon 8 becomes flat (FIG. 1 (b)). Further, a resist is applied, and the resist in the drain opening in the lower electrode region of the capacitor and in the unnecessary region is removed by photolinography (FIG. 1 (c)). After that, unnecessary portions of the polycrystalline silicon 8 other than the capacitor lower electrode are removed by anisotropic dry etching, and etching is performed so as to leave the layer of polycrystalline silicon 8 inside the drain opening. Since the layer of polycrystalline silicon 8 in the drain opening region has a large film thickness, it can be formed by one dry etching. Further, as the dielectric material of the capacitor, the surface of the polycrystalline silicon 8 is oxidized to form the thermal oxide film 10 (FIG. 1 (d)). further,
A polycrystalline silicon layer 11 and an interlayer insulating film 12 are formed as an upper electrode of the capacitor, a contact is made with the source diffusion layer 5, and a bit line 13 is formed (FIG. 1 (e)).

In FIG. 1 (e), the size of the polycrystalline silicon 8 is 5
μm square, the size of the groove inside the drain opening area is 1 μm
If the corner and the thickness of the polycrystalline silicon 8 are 3 μm and the thickness of the thermal oxide film 10 as a dielectric is 200 Å, the capacitance value of the capacitor is 172 fF. In the conventional DRAM capacitance forming method, when the size of the lower electrode is 5 μm square and the thickness of the thermal oxide film is 200 Å, it is 89 fF, and the capacitance value of the capacitor to which the present invention is applied is 93 fF. % Increase. For this reason, the cell area can be reduced, and miniaturization is facilitated.

As the dielectric of the capacitor, the capacitance value can be increased by the two-layer structure of the oxide film and the nitride film having a high dielectric constant.

Furthermore, by forming not only one groove but a plurality of grooves in the lower electrode of the capacitor within the limit of the fine processing technique, the capacitance can be further increased.

〔The invention's effect〕

As described above, according to the present invention, the polycrystalline silicon that is the lower electrode of the capacitor is flattened by growing thicker than the step in the drain opening region, and further, the drain is formed inside the drain opening region by anisotropic dry etching. It is possible to increase the side wall area of the lower electrode by deeply grooving a groove that does not reach the cell width, which has the effect of reducing the DRAM cell area.Also, since the present invention has a stacked capacitor structure, α-rays emitted from the package material etc. With respect to the soft error that destroys the cell information, the area of the drain is small, which is advantageous.

[Brief description of drawings]

1 (a) to (e) apply one embodiment of the present invention.
FIG. 2A is a vertical sectional view showing the manufacturing process of the DRAM cell structure.
8A to 8C are vertical cross-sectional views showing the manufacturing process of the DRAM cell structure by the conventional semiconductor device manufacturing method. 1 ... P-type silicon substrate, 2 ... field oxide film, 3
...... Gate oxide film, 4 ... Polycide gate electrode, 5 ...
... source diffusion layer, 6 ... drain diffusion layer, 7 ... interlayer insulating film, 8 ... polycrystalline silicon, 9 ... photoresist,
10 ... Thermal oxide film, 11 ... Polycrystalline silicon layer, 12 ... Interlayer insulating film, 13 ... Bit line.

Claims (1)

[Claims] 1. A step of forming a source and a drain by introducing an impurity of the second conductivity type onto a semiconductor substrate of the first conductivity type, and the first step of forming the source and the drain.
A step of forming an interlayer insulating film on the semiconductor substrate of conductivity type, a step of forming an opening for a drain contact region in the interlayer insulating film, and a low pressure chemical vapor deposition step on the opening and the interlayer insulating film. Depending on the growth method, the depth of the opening is 3
A step of growing a first polycrystalline semiconductor layer with a thickness more than twice the thickness of the first polycrystalline semiconductor layer to form a flat surface on the first polycrystalline semiconductor layer; and anisotropically etching the first polycrystalline semiconductor layer on the drain region. A step of forming a groove in the first polycrystalline semiconductor so as not to reach the drain and removing the unnecessary first polycrystalline semiconductor; and thinly oxidizing the surface of the remaining first polycrystalline semiconductor. And a step of forming an oxide film, and a step of forming a second polycrystalline semiconductor layer on the oxide film to form a capacitor element.