JPH0734591B2 - Solid-state imaging device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a high resolution by using a plurality of semiconductor elements such as CCDs (charge coupled devices) as solid-state imaging elements.

2. Description of the Related Art Conventionally, a solid-state image pickup device using a plurality of solid-state image pickup elements has a configuration as shown in FIG. 3, and as a means for achieving high resolution, a "pixel" shown in FIG. 4 is generally used. The "shift method" is applied.

That is, in FIG. 3, 1R, 1G.1B are solid-state imaging devices for red (R), green (G), and blue (B), respectively, and these solid-state imaging devices 1R, 1G, 1B are As shown in Fig. 4, 1R and 1B solid-state image pickup devices have τ / 2 for 1G solid-state image pickup device (τ is the horizontal scanning 1-pixel array pitch, which corresponds to the clock pulse period in CCD). They are arranged in a staggered manner.

2R, 2G, and 2B are preamplifier circuits that perform R, G, and B signal processing, respectively, and 3R, 3G, and 3B are low-pass filters for R signal, G signal, and B signal that pass through the base hand, respectively. A circuit (L, P, F), 4 is a τ / 2 delay circuit for matching the phase of the G signal with the phase of the R signal and the B signal, and 5R, 5G, 5B are R, G, and 5B, respectively. A process circuit that performs signal processing of the B signal, 6 is a color encoder circuit that generates a color composite output based on the R, G, B signals, and 7
Is a pulse generation circuit for pulses applied to the solid-state image pickup devices 1R, 1G, and 1B.

Next, the operation of the conventional device having the above configuration will be described.

The outputs of the solid-state image pickup devices 1R, 1G, 1B are the preamplifier circuits 2R, 2G,
Amplified by 2B, band-limited to frequency components of fc (1 / τ) or less by LPF3R, 3G, 3B, only G signal passes through the delay circuit 4, and other R and B signals are directly processed by the process circuits 5R, 5
Signal processing such as gamma correction is performed in G and 5B, and converted into a color composite signal in the encoder circuit 6.

Here, the matrix of the luminance signal Y in the encoder circuit 6 is YL = 0.59G + 0.3R + 0.11B YH = 0.5G + 0.5 (R + B), where YL is the low frequency component and YH is the high frequency component. Is configured.

By the way, as shown in FIGS. 5 (a) and 5 (b), a false signal centered on fc (1 / τ) is generated only by the G signal.
It is difficult to reproduce the components up to fc.

However, as shown in FIG. 4, 1R and 1B are arranged at a half pitch with respect to 1G, that is, shifted by τ / 2, and spatial sampling is performed. Therefore, as shown in FIG. As a result, the phases of the false signals of the R signal and the B signal become opposite phases. As a result, the high frequency component YH of the luminance signal Y can be reproduced up to fc at which the false signal is canceled.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described conventional solid-state imaging device, a delay circuit for matching the phase of the G signal with the phases of the R signal and the B signal is necessary, and in particular, a change in the delay amount is a false signal. Since it greatly contributes to the cancellation of the high frequency component of, a high-precision delay circuit capable of holding a high-precision delay time constant is required in order to achieve high resolution.

Further, as shown in FIGS. 6 (a) and 6 (b), the output of the solid-state imaging has a longer signal component than that in the reset period, and as shown in FIG. Is getting worse. That is, the output of the solid-state image pickup device has a frequency characteristic that decreases in a high frequency range. In other words,
This means that the response characteristics in the high frequency range have deteriorated.

If the response characteristic is R (f), then R (f)
Can be represented as:

Here, f is the frequency, and Δτ is the sampling aperture time as shown in FIG. 7. As is clear from FIG. 7, the smaller Δτ, that is, the smaller the aperture time, the better the response characteristics in the high frequency range.

The present invention has been falsified in view of the above-mentioned circumstances, and an object of the present invention is to provide a solid-state imaging device which avoids the use of a delay circuit and improves the high frequency response characteristics. Especially.

Means for Solving the Problems In order to achieve the above object, the present invention provides a sample hold circuit, a DC reproduction circuit, and a horizontal 1 clock in a stage subsequent to a preamplifier circuit that amplifies each output of a plurality of solid-state imaging devices. Providing a gate circuit that gates the G signal and the R and B signals,
The output of the gate circuit is input to the encoder circuit by the process circuit via the low-pass filter circuit.

Action The present invention has the following actions and effects due to the above configuration.

That is ,. The high-precision delay circuit used in the conventional device can be omitted in the device of the present invention.

． In FIG. 2, a is a reset pulse of the solid-state image sensor, b is the output of the R, G, B 3-channel preamplifier circuit (the output of the solid-state image sensor is inverted but the output of the preamplifier circuit is in positive phase). When the output b of this preamplifier circuit passes through the sample hold circuit having the sample pulse c, the output of the sample hold circuit (R, G, B) becomes as shown in FIG. 2d.

Next, the output d of the sample hold circuit for the R, G, B signals is gated by the gate pulse e. In this case, the R and B signals are negative, the G signal is blocked, and the R and B signals are positive, and the G signal is passed.

As a result, the R and B signals are gated like the output f of the gate circuit, and the G signal is gated like the output g of the gate circuit.
The signal is accurately delayed by τ / 2 from the R and B signals. Moreover, the aperture time (sampling period) of each sampling signal is shortened to 1/2. That is, the sample pulse width becomes narrow. From this, the response characteristic in the high frequency range is also improved.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a solid-state image pickup device which is an embodiment of the present invention.

1 is different from FIG. 3 in that a preamplifier circuit is used.
Preamplifier circuit 2R, 2G, 2B output between 2R, 2G, 2B and low pass filter circuit (LPF) 3R, 3G, 3B (see Fig. 2b)
Sample-hold circuit 8R, 8G, 8B that samples and holds
And its sample and hold circuit 8R, 8G, 8B output (Fig. 2d
(Refer) to a fixed DC, that is, a DC reproduction circuit 9R, 9G, 9B for fixing the DC of the video signal, and a gate circuit for gating the G signal and the R and B signals within one horizontal clock.
Providing 10G, 10R, 10B, each solid-state imaging device 1R, 1G, 1B
A sampling pulse (see FIG. 2c) is applied from the pulse generation circuit 7 that applies a reset pulse (see FIG. 2a) to the sample and hold circuits 8R, 8G, 8B, and a gate pulse (see FIG. 2e). ) Is applied to the gate circuits 10R, 10G, and 10B. At that time, only when the gate pulse is applied to the gate circuit 10G of the G signal, it is configured to be applied via the inverting circuit 11 and then LPF3G Between the process circuit 5G and the process circuit 5G
(See FIG. 3) is removed.

Since the other points are the same as those in FIG. 3, the same reference numerals are given and the details thereof are omitted.

In the device configured as described above, the solid-state imaging device 1R, 1
The R, G, B signal outputs of G, 1B are input to the preamplifier circuits 2R, 2G, 2B and amplified. The R, G, B signal outputs of the preamplifier circuits 2R, 2G, 2B are sampled and held by the sampling hold circuit 8R, 8G, 8B by the sampling pulse c (see FIG. 2) as shown in FIG. As shown in FIGS. 2f and 2g, only the G signal is delayed by τ / 2 and gated. In that case, the sample period is also halved.

As a result, it is no longer necessary to use a delay circuit as in the past, and at the same time, it is possible to improve the response characteristics in the high frequency range.

Further, the DC reproduction circuit 9R, 9G, 9B fixes the signal-free portion of the output of the gate circuit 10R, 10G, 10B (see FIG. 2, f, g), and matches it with the signal-free portion, This is to suppress generation of clock components from the gate circuits 10R, 10G, 10B as much as possible.

In the gate circuits 10R, 10G, and 10B of FIG. 1, 1/2 of one clock component is passed, but if this is made smaller, the response characteristics in the high frequency band can be further improved (however, There is an upper limit due to the horizontal opening width).

Further, when the shift direction of the solid-state image pickup device 1G is opposite to the direction shown in FIG. 4, the gate timing within one clock is naturally opposite to the relationship shown in FIG. 2e. That is, in the same figure e, the R and B signals are first and the G signal is switched later, but this is reversed.

EFFECTS OF THE INVENTION As is apparent from the above embodiments, the present invention amplifies each output of a plurality of solid-state image pickup devices in which a semiconductor device such as a CCD is used as a solid-state image pickup device, and a sample-hold circuit that samples and holds this output. , DC recovery circuit that fixes each output of each sample and hold circuit to a constant DC voltage, and each DC
A gate circuit that gates each output of the reproduction circuit is provided, and each output of each gate circuit is used as an encoder input through a low-pass filter. Since the output of the solid-state image pickup device is gated with respect to the output of another solid-state image pickup device with a timing shift within one clock cycle of the horizontal clock, the use of a delay circuit as in the prior art is unnecessary, and It is possible to improve the response characteristic in the high frequency range because the sample pulse width can be narrowed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device which is an embodiment of the present invention, FIG. 2 is a timing chart of each circuit in FIG. 1, and FIG. 3 is a schematic configuration of a conventional solid-state imaging device. FIG. 4 is a block diagram, FIG. 4 is a layout diagram of a solid-state imaging device to which the pixel shift method is applied, FIG. 5 (a) is a component diagram of a signal of the solid-state imaging device output and a false signal, and FIG. 6A is a waveform diagram showing a reset pulse of the solid-state image sensor, FIG. 6B is an output waveform diagram of the solid-state image sensor, and FIG. 7 shows a relationship between the sampling pulse width and the response characteristic. It is a diagram for explaining. 1R, 1G, 1B ... Solid-state image sensors for red, green, and blue,
2R, 2G, 2B …… Similar preamplifier circuit, 3R, 3G, 3B …… Similar range pass filter circuit (LPF), 5R, 5G, 5B …… Similar process circuit, 6 …… Encoder circuit, 7 ... … Pulse generation circuit, 8R, 8G, 8B …… Similar sample and hold circuit,
9R, 9G, 9B ... Similar DC regeneration circuit, 10R, 10G, 10B ... Similar gate circuit, 11 ... Inversion circuit.

Claims (1)

[Claims] 1. An amplifying means for amplifying each output of a plurality of solid-state image pickup devices, a sample hold circuit for sampling and holding each output from each amplifying means, and each output of each sample and hold circuit having a constant DC voltage. In the solid-state imaging device, which is provided with a DC reproduction circuit that fixes the voltage, and a gate circuit that gates each output of each DC reproduction circuit, and outputs each output of each gate circuit as an encoder input via a low-pass filter, Each of the gate circuits gates an output of a specific solid-state image sensor among the plurality of solid-state image sensors with a timing shift with respect to an output of another solid-state image sensor within one clock cycle of a horizontal clock. Solid-state imaging device.