JPH0736499B2 - Power amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a BTL power amplifier circuit, and in particular, a reference voltage is generated from a power supply voltage by a filter and a buffer amplifier composed of a resistor and a capacitor, and an output terminal DC is generated from the reference voltage. The present invention relates to a BTL power amplifier circuit that sets a voltage.

[Conventional technology]

FIG. 2 shows an example of this type of BTL power amplifier circuit. In the reference voltage circuit 100, the resistors 6 and 7 are connected in series between the positive power supply terminal 17 and the ground potential, and the capacitor 14 is connected between the connection point of the resistors 6 and 7 and the ground potential. Further, the input terminal of the buffer amplifier 13 is connected to the connection point of the resistors 6 and 7. The input terminal 21 is connected to the non-inverting input terminal of the first stage amplifier 24. A feedback resistor is provided at the inverting input terminal of the first stage amplifier 24.
23 is connected to the output terminal of the buffer amplifier 13 of the reference voltage circuit 100, and the feedback resistor 22 is connected to the output terminal of the first-stage amplified air 24. The output terminal of the first-stage amplifier 24 is connected to the base of the PNP transistor 1 of the inverting / non-inverting signal amplifier 200 which generates the inverting / non-inverting signal from the output signal of the first-stage amplifier 24. The PNP transistors 3, 4, and 5 constitute a current mirror circuit, each emitter is connected to the positive power supply terminal 17, and the bases are commonly connected. The collector of the PNP transistor 5 is connected to the base and further connected to the constant current source 18. A resistor 12 is connected between the collectors of PNP transistors 3 and 4,
Further, the collector of the PNP transistor 4 is the emitter of the PNP transistor 1 and the final stage amplifier 16 for power amplification.
Is connected to the output terminal 20 through the feedback resistor 9. PN
The collector of the P-transistor 3 is connected to the emitter of the PNP transistor 2 and the feedback resistor 8 to the output terminal 19 of the final stage amplifier 15.
Connected through. The base of the PNP transistor 2 is connected to the output of the buffer amplifier 13. The collector of the PNP transistor 1 is connected to the base of the NPN transistor 28 of the output stage amplifier 16, and further connected to the GND 32 via the resistor 10. The collector of the PNP transistor 2 is connected to the base of the NPN transistor 25 of the final stage amplifier 15 and further connected to the GND 32 via the resistor 11. The emitter of the NPN transistor 25 of the final stage amplifier 15 is connected to the GND of the base of the NPN transistor 27 and the resistor 26, and the emitter of the NPN transistor 27 is connected to the GND 33. The emitter of the NPN transistor 28 of the final stage amplifier 16 is connected to the base of the NPN transistor 30 and the resistor 29 to GND 34.
And the emitter of the NPN transistor 30 is connected to GND 34. A load resistor 31 is connected between the output terminals 19 and 20 of the final stage amplifiers 15 and 16. The power supplies of the final stage amplifiers 15 and 16 are connected to the positive power supply terminal 17.

Next, how to determine the terminal voltages of the output terminals 19 and 20 in the circuit of FIG. 2 will be described. It is assumed that the output terminal voltage of the first stage amplifier 24 is the output voltage of the buffer amplifier 13 of the reference voltage circuit 100 (hereinafter referred to as Vref) when there is no signal. Further, the base-emitter voltages of the PNP transistors 1 and 2 are V _BE1 and V _BE2 , the resistance values of the feedback resistors 8 and 9 are R8 and R9, and the voltage drops at the feedback resistors 8 and 9 are V _R8 and V _R9 , respectively. Then BTL
Output DC voltage of output terminals 19 and 20 of power amplifier circuit V _OUT19 , V
_OUT20 is V _OUT19 = Vref + V _BE2 -V _R8 (1) V _OUT20 = Vref + V _BE1 -V _R9 (2) If the current values flowing in the feedback resistors 8 and 9 are I _R8 and I _R9 respectively, V _R8 = R ₈ I _R8 , V _R9 = R ₉ · I _R9 (3) Make the current values of the PNP transistors that make up the current mirror circuit equal, and set the current value to I ₁ and the PNP transistor.
If the emitter currents of 1 and 2 are I _E1 and I _E2 respectively, I _R8 and I _E2
R9 becomes I _R8 = I ₁ −I _E2 and I _R9 = I ₁ −I _E1 . Where PNP
If h _{FE of} transistors 1 and 2 is sufficiently large and the base current is negligible, and the collector currents of PNP transistors 1 and 2 are I _C1 and I _C2 , respectively, I _R8 = I ₁ −I _C2 , I _R9 = I ₁ −I _C1 (4) Here, the base potentials of NPN transistors ₂₅ and 28 are V _B25 and V, respectively.
_{If B28} , then I _C1 and I _C2 are I _C1 = V _B28 / R ₁₀ , I _C2 = V _B25 / R ₁₁ (5) From the above equations (1), (2), (3), (4) and (5) _{V OUT19 = Vref + V BE2 -V} R · (I 1 -V B25 / R 11) (6) V OUT20 = Vref + V BE1 -R 8 · (I 1 -V B28 / R 10) become (7).

Next, the operation of the BTL power amplifier circuit when the voltage at the positive power supply terminal 17 (hereinafter referred to as V _CC ) drops sharply will be described with reference to FIGS. 3 (a) and 3 (b). To do. FIG. 3 (a) shows potential fluctuations of the output terminal voltages V _OUT19 , V _OUT20 , and Vref of the BTL power amplifier circuit when there is no signal.
When V _CC drops from V _CC1 to V _CC2 , Vref is the value when V _CC is V _CC1
From Vref ₁ to V _CC value of V _{CC 2} Vref ₂ Resistors 6, 7, Capacitor 14
V _OUT19 and V _OUT20 are reduced by the time constant of
It goes down following Vref from (7).

Next, FIG. 3 (b) shows potential fluctuations of the output terminal voltages V _OUT19 and V ref of the BTL power amplifier circuit at the time of signal input. At signal input, when V _CC drops from V _CC1 to V _CC2 , V _CC
The signal waveform of _OUT19 is clipped at the upper amplitude.
The output terminal voltage V _OUT20 also operates in the same manner, and the signal waveform appearing across the load 31 is also clipped.

[Problems to be Solved by the Invention]

In the conventional BTL power amplifier circuit described above, the reference voltage Vref is set through the filter from the power supply voltage V _CC , and the output terminal voltage is set from Vref, so if the power supply voltage V _CC drops sharply, the output terminal voltage Does not follow V _CC ,
There is a drawback that the output waveform during signal clipping.

Also, by decreasing the time constant of the filter circuit, Vr
ef can follow V _CC , but S ・ V ・ R ・ R
(Supply Voltage Ripple Rejection: ratio of the noise component when the noise component is superimposed on the power supply voltage and the level of the noise component appearing at the output terminal of the BTL power amplifier circuit) has the drawback of lowering the characteristics.

[Means for Solving the Problems]

The BTL power amplifier circuit of the present invention includes a reference voltage circuit that generates a reference voltage from a power supply voltage by a filter and a buffer amplifier composed of a resistor and a capacitor, a first-stage amplifier biased by the reference voltage, and an output signal of the first-stage amplifier. It has an inverted / non-inverted signal amplifier that generates an inverted signal / non-inverted signal, a final-stage amplifier that power-amplifies the inverted signal / non-inverted signal, and a comparator circuit that operates by comparing the power supply voltage and the reference voltage. ing.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit of an embodiment of the present invention. The present invention includes the NPN transistor 20 in the circuit shown in FIG.
1,202, resistors 101,102,103,104,105, power supply voltage V
Comparator circuit that operates by comparing _CC and reference voltage Vref
It is provided with 300.

The configuration of the comparator circuit 300 is such that resistors 101 and 102 are connected in series between the output of the buffer amplifier 13 and the ground potential, the base of the NPN transistor 201 is connected to the connection point of the resistors 101 and 102, and the collector of the NPN transistor 201 is a PNP transistor. It is connected to 5 collectors. Connect resistors 103 and 104 in series between the positive power supply terminal 17 and ground potential.
The base of NPN transistor 202 is connected to the connection point of
The collector of the N-transistor 202 is connected to the positive power supply terminal 17. A resistor 105 is connected between the connection point of the emitters of the NPN transistors 201 and 202 and the ground potential.

Here, the setting of the resistors 101, 102, 103, 104 is such that when the V _{CC is} constant and the V ref is constant, the transistor 202 is conductive and the transistor 2
Set so that 01 is in the cutoff state, V _CC drops sharply, Vref drops due to the time constant of the filter circuit, and transistor 201 is conductive and transistor 202 is cut off until it stabilizes again. Set to.

Next, the circuit operation when V _CC sharply drops will be described. As described above, the resistors 101, 10
Set the resistance value of 2,103,104, V _CC suddenly decreases, NPN
If transistor 201 is conducting, NPN transistor 201
Let I _{2 be} the collector current of I ₁ = I ₀ + I ₂ (8) In addition, the resistance values of resistors 101, 102, 105 are R101, R102, R103,
If the base-emitter voltage of the NPN transistor is V _BE201 , Becomes From equations (6) and (7) and equations (8) and (9) Becomes

Next, FIG. 3 (c) shows the operation of V _CC , the voltage of V _OUT19 when _there is no signal, the waveform of V _OUT19 when _there is no signal, and V _ref when V _CC sharply drops.
Will be explained.

Period t ₁ is the operation before the V _CC decreases rapidly from V _CC1 to V _CC2.

The period t ₂ is an operation in which V _CC sharply drops from V _CC1 to V _CC2 and the NPN transistor 201 of the comparator circuit 300 is conducting. Similar to the circuit of the conventional example, Vref decreases due to the filter time constant of the reference voltage circuit 100. The voltage of V _OUT19 when there is no signal is the NPN transistor of the comparator circuit 300.
Although 201 becomes conductive and I ₂ flows and decreases according to the equation (10), by setting the resistor 105 of the comparator circuit 300 to an appropriate value, the operation following V _CC as shown in FIG. 3 (C) is performed. It is possible to prevent the clipping of the signal waveform at the time of signal input. V _{OUT20 Performs the} same operation.

Here when V _CC in the circuit of the present invention decreases rapidly from V _CC1 to V _CC2, inverted output terminal voltage V _OUT19, non-inverted output terminal V
_OUT20 also fluctuates rapidly, but the inverting output terminal voltage V _OUT19
If the non-inverting output terminal voltage V _OUT20 changes in the same phase, the load
Since a potential difference does not occur at both ends of 31, the signal waveform that appears at both ends of the load 31 during signal generation does not have an abnormal potential fluctuation.

〔The invention's effect〕

As described above, according to the present invention, the power supply voltage V _CC and the reference voltage V _CC
By adding a comparator circuit that operates by comparing refs, it is possible to prevent clipping of the output waveform when the power supply voltage V _CC sharply drops without deteriorating the S · V · R characteristics.

[Brief description of drawings]

FIG. 1 is a circuit of an embodiment of the present invention, FIG. 2 is a conventional circuit,
3 (a) to 3 (c) show the output terminal voltages V _OUT19 , ₂₀ and the reference voltage V when the power supply voltage V _CC sharply drops from V _CC1 to V _CC2 .
Fig. 3 (a) shows the operation of ref. The operation of the output terminal voltage V _OUT19 (when there is no signal) and V _ref when the power supply voltage V _CC sharply drops from V _CC1 to V _CC2 in the conventional circuit. FIG. 3 (b) shows the waveform of the signal at the output terminal 19 and the operation of Vref when the power supply voltage V _CC sharply drops from V _CC1 to V _CC2 in the conventional circuit, and FIG. 3 (c) shows the present invention. Operation of the output terminal voltages V _OUT19 and V ref when the power supply voltage V _CC sharply drops from V _CC1 to V _CC2 in the circuit of the embodiment. 1,2,3,4,5,25,27,28,30,201,202 …… Transistor,
6,7,8,9,10,11,12,22,23,26,29,101,102,103,104,105 ...
… Resistor, 31 …… Load, 17 …… Positive power supply terminal, 18 …… Constant current source, 14 …… Capacitor, 13 …… Buffer amplifier, 15,1
6 …… Last stage amplifier, 21 …… Input terminal, 19,20 …… Output terminal, 100 …… Reference voltage circuit, 200 …… Inverting / non-inverting amplifier, 300 …… Comparator circuit, 24 …… First stage amplifier, 32 ,
33,34,35,106 …… Ground potential.

Claims (1)

[Claims] 1. A first and a second terminal between a power supply terminal and a ground terminal.
Is connected in series, a capacitor is connected between the connection point of the first and second resistors and the ground terminal, and the reference voltage is the voltage at the connection point of the first and second resistors. A first and second current source is connected to the respective emitters of the first and second transistors whose bases are biased by the circuit, and a third transistor is connected between the emitters of the first and second transistors.
Of the first and second amplifier circuits are connected to the collectors of the first and second transistors, respectively, and the output terminals of the first and second amplifier circuits and the first and second amplifier circuits are connected. In a BTL power amplifier circuit having a configuration in which fourth and fifth resistors are connected as feedback resistors between the emitters of the two transistors, first and second BTL power amplifier circuits generated based on the power supply voltage and the reference voltage, respectively. And a means for increasing the currents of the first and second current sources based on the detection output of the comparison circuit. BTL power amplifier circuit equipped.