JPH073859B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device including a one-transistor type memory cell.

[Conventional technology]

The one-transistor type memory cell is the mainstream of the memory cell of the MOS dynamic memory. However, due to the high integration, the cell area is reduced, the charge storage capacity is reduced, and the α ray soft error easily occurs. There is.

2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method for manufacturing a semiconductor memory device.

As shown in FIG. 2A, a field insulating film 2 for element isolation is selectively formed on one main surface of a P-type silicon substrate 1 to partition an element formation region, and a MOS capacitor is formed in the element formation region. The N-type diffusion region 3 is formed by selectively introducing N-type and P-type impurities for increasing the carrier concentration and increasing the charge storage capacity of the depletion layer. Next, a silicon oxide film 15 having a film thickness of 50 to 60Å and a silicon nitride film 4 having a film thickness of 150 to 200Å are formed on the surface including the element formation region, and the surface of the silicon nitride film 4 is oxidized by wet oxidation at 950 ° C. Thus, a silicon oxide film 5 having a film thickness of 30 Å is formed, and a polycrystalline silicon film 7 is formed on the silicon oxide film 5. Next, a photoresist film 8 having a pattern for forming an electrode for a MOS capacitor is formed on the polycrystalline silicon film 7, and the polycrystalline silicon film 7 is removed by an etching method using the photoresist film 8 as a mask.

Next, as shown in FIG. 2B, the photoresist film 8 is removed and the surface of the polycrystalline silicon film 7 is oxidized to form a silicon oxide film 9.

Next, as shown in FIG. 2C, the silicon oxide film 9, the silicon nitride film 4, and the silicon oxide film 15 are sequentially etched using the silicon oxide film 9 as a mask to expose the P-type silicon substrate 1.

Next, as shown in FIG. 2D, the P-type silicon substrate 1
A gate insulating film 11 is formed on the surface of the silicon oxide film by a thermal oxidation method, and a gate electrode 12 having a polycrystalline silicon film selectively formed on the gate insulating film 11 and the silicon oxide film 9 is provided.
The surface of 12 is oxidized to form a silicon oxide film 13. Next, by using the gate electrode 12, the silicon oxide film 13 and the field insulating film 2 as a mask, an N ⁺ type diffusion region 14 is provided in the P type silicon substrate 1 by an ion implantation method to form a MOS transistor for a transmission gate adjacent to the MOS capacitor. .

[Problems to be solved by the invention]

In the conventional method for manufacturing a semiconductor memory device described above, a three-layer composite film formed by sequentially stacking a silicon oxide film, a silicon nitride film and a silicon oxide film on a semiconductor substrate is used as a charge storage dielectric layer of a MOS capacitor. Although used, the silicon oxide film formed on the silicon nitride film cannot be thinner than the conventional example in order to prevent pinholes in the silicon nitride film,
Further, if the silicon nitride film is made thin, there is a risk that the entire silicon nitride film will be oxidized by wet oxidation, and it is not possible to reduce the film thickness of the charge storage dielectric layer and increase the charge storage capacity of the MOS capacitor. There is a problem.

Further, the silicon nitride film cannot be thinned because it is used as an etching stopper for the polycrystalline silicon film and as an oxidation resistant mask when the surface of the polycrystalline silicon film is wet-oxidized.

An object of the present invention is to provide a method of manufacturing a semiconductor memory device that increases the charge storage capacity of a MOS capacitor.

[Means for solving problems]

According to the method of manufacturing a semiconductor memory device of the present invention, (A) a field insulating film for element isolation is selectively formed on one main surface of a semiconductor substrate of one conductivity type to partition an element formation region, A step of sequentially stacking and forming a first silicon nitride film and a first silicon oxide film on the surface including (B) a MOS transistor forming region for a transmission gate of the element forming region on the first silicon oxide film. Forming a polycrystal silicon film on the surface including the second silicon nitride film, and forming a charge storage electrode forming pattern on the polycrystal silicon film. Forming a photoresist film and etching the polycrystalline silicon film using the photoresist film as a mask and the second silicon nitride film as an etching stopper; (C) removing the photoresist film And a step of forming a thick second silicon oxide film on the surface of the polycrystalline silicon film and a thin third silicon oxide film on the surface of the second silicon nitride film by a wet oxidation method. A step of sequentially removing the third silicon oxide film, the second silicon nitride film, the first silicon oxide film, and the first silicon nitride film by etching using the second silicon oxide film as a mask; ) A gate insulating film is formed on the exposed surface of the semiconductor substrate, a gate electrode is selectively formed on the gate insulating film and the second silicon oxide film, and a silicon oxide film covering the gate electrode is formed. And then forming an N-type diffusion region on the surface of the semiconductor substrate using the gate electrode and the field insulating film as a mask.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1A, a field insulating film 2 for element isolation is selectively formed on one main surface of a P-type silicon substrate 1 to partition an element formation area, and a MOS capacitor is provided in the element formation area. The N-type diffusion region 3 is formed by selectively introducing N-type and P-type impurities for increasing the carrier concentration and increasing the charge storage capacity of the depletion layer. Next, a silicon nitride film 4 having a film thickness of 70 to 80Å is formed on the surface including the element formation region, and the surface of the silicon nitride film 4 is oxidized by wet oxidation at 950 ° C. to form a silicon oxide film 5 having a film thickness of 30Å. Form. Next, a silicon nitride film 6 is selectively formed on the silicon oxide film 5 corresponding to the transmission gate MOS transistor formation region in the element formation region, and a polycrystalline silicon film 7 is formed on the surface including the silicon nitride film 6. Form. Next, a photoresist film 8 having an electrode formation pattern for a MOS capacitor is formed on the polycrystalline silicon film 7, and the polycrystalline silicon film 7 is etched by using the photoresist film 8 as a mask and the silicon nitride film 6 as an etching stopper. To remove.

Next, as shown in FIG. 1B, the photoresist film 8 is removed, the surface of the polycrystalline silicon film 7 is wet-oxidized by using the silicon nitride film 6 as an oxidation resistant mask, and the surface of the polycrystalline silicon film 7 is removed. Thick silicon oxide film 9 and silicon nitride film 6
A thin silicon oxide film 10 is formed on the surface of.

Next, as shown in FIG. 1C, the silicon oxide films 9 and 5 are buffered and hydrofluoric acid, and the silicon nitride films 6 and 4 are phosphoric acid solution from the upper layer using the silicon oxide film 9 as a mask. The P-type silicon substrate 1 is exposed by sequentially etching.

Next, as shown in FIG. 1D, the P-type silicon substrate 1
A gate insulating film 11 is formed on the surface of the substrate by a thermal oxidation method, and then a gate electrode 12, a silicon oxide film 13 and an N ⁺ type diffusion region 14 are provided in the same process as in the conventional example, and a MOS transistor for a transmission gate adjacent to a MOS capacitor To form.

〔The invention's effect〕

As described above, according to the present invention, an MO film is formed by forming a dedicated silicon nitride film as an etching stopper and an oxidation resistant mask for a polycrystalline silicon film of a charge storage electrode on a semiconductor substrate.
By providing it separately from the silicon nitride film forming the charge storage dielectric layer of the S capacitor, the film thickness of the silicon nitride film of the charge storage dielectric layer can be reduced and the charge storage dielectric layer can be made of silicon nitride. The double layer of the film and the silicon oxide film has an effect that the charge storage capacity can be doubled in the same area as in the conventional case and the occurrence of the α ray soft error can be prevented.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are conventional semiconductor memory device manufacturing processes. FIG. 7 is a cross-sectional view of the semiconductor chip showing the order of steps for explaining the method. 1 ... P-type silicon substrate, 2 ... field insulating film, 3 ... N
Type diffusion region, 4 ... Silicon nitride film, 5 ... Silicon oxide film, 6 ... Silicon nitride film, 7 ... Polycrystalline silicon film, 8 ...
Photoresist film, 9, 10 ... Silicon oxide film, 11 ... Gate insulating film, 12 ... Gate electrode, 13 ... Silicon oxide film, 14 ... N ⁺ diffusion region, 15 ... Silicon oxide film.

Claims (1)

[Claims] (A) A field insulating film for element isolation is selectively formed on one main surface of a semiconductor substrate of one conductivity type to partition an element formation region, and a first surface is formed on a surface including the element formation region. Forming a silicon nitride film and a first silicon oxide film by sequentially laminating the same, (B) forming a second MOS transistor forming region for a transmission gate in the element forming region on the first silicon oxide film; Selectively forming the second silicon nitride film, forming a polycrystalline silicon film on the surface including the second silicon nitride film, and forming a photoresist film having a charge storage electrode forming pattern on the polycrystalline silicon film. Etching the polycrystalline silicon film using the photoresist film as a mask and the second silicon nitride film as an etching stopper; (C) removing the photoresist film and performing a wet oxidation method. Forming a thick second silicon oxide film on the surface of the polycrystalline silicon film and a thin third silicon oxide film on the surface of the second silicon nitride film; (D) masking the second silicon oxide film As a step of sequentially removing the third silicon oxide film, the second silicon nitride film, the first silicon oxide film, and the first silicon nitride film by etching, (E) exposing the exposed semiconductor substrate A gate insulating film is formed on the surface, a gate electrode is selectively formed on the gate insulating film and the second silicon oxide film, and a silicon oxide film covering the gate electrode is formed. And a step of forming an N-type diffusion region on the surface of the semiconductor substrate using the field insulating film as a mask.