JPH073983B2 - Telephone semiconductor integrated circuit - Google Patents
Telephone semiconductor integrated circuitInfo
- Publication number
- JPH073983B2 JPH073983B2 JP60199954A JP19995485A JPH073983B2 JP H073983 B2 JPH073983 B2 JP H073983B2 JP 60199954 A JP60199954 A JP 60199954A JP 19995485 A JP19995485 A JP 19995485A JP H073983 B2 JPH073983 B2 JP H073983B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- semiconductor integrated
- integrated circuit
- circuit
- telephone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000001514 detection method Methods 0.000 claims description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 2
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は,電話用ダイアラー半導体集積回路(以下ダイ
アラーICと称する),またはダイアル機能を内臓した集
積回路(以下ICと称する)に関する。The present invention relates to a telephone dialer semiconductor integrated circuit (hereinafter referred to as a dialer IC) or an integrated circuit having a dial function (hereinafter referred to as an IC).
この発明は,書き換え可能な半導体記憶装置(以下RAM
と称する)を内蔵し電話番号を記憶するダイアラーICま
たは同様のダイアル機能を内蔵するICにおいて,電源投
入時に電話番号の最初の一桁乃至複数桁にデータ終了符
号(以下エンドコードと称する)を書き込むことによ
り,未開き込みのアドレスが誤つて呼び出された時にま
ちがい電話となることを防止するものである。This invention relates to a rewritable semiconductor memory device (hereinafter referred to as RAM
In the dialer IC that stores a telephone number or that has a similar dial function, a data end code (hereinafter referred to as an end code) is written to the first digit or digits of the telephone number when the power is turned on. This prevents a wrong call when an unopened address is called by mistake.
従来の電話用ダイアラーICはメモリを有する場合,電源
投入時に逐一マニユアル操作でメモリクリアを行なうも
のと,ソフトウエアによりメモリをアクセスして初期化
するものとがあつた。When a conventional dialer IC for a telephone has a memory, there are one that clears the memory by manual operation every time the power is turned on and one that accesses the memory by software and initializes it.
しかしながら,マニユアルでメモリクリアを行なうこと
は面倒であり,誤操作が介在する可能性もある。またソ
フトウエアでメモリをイニシヤライズするためには,ア
ドレスを変化させながらメモリをアクセスし初期化デー
タを書き込むという操作を記憶する電話番号の数だけ繰
り返さねばならず,そのための回路は複雑でありかつ時
間もかかるという欠点を有していた。However, manually clearing the memory is troublesome, and there is a possibility that an erroneous operation may be involved. In addition, in order to initialize the memory by software, the operation of accessing the memory while changing the address and writing the initialization data must be repeated by the number of stored telephone numbers, and the circuit for that is complicated and time-consuming. It had the drawback of taking up too much.
そこで,この発明は,従来のこの様な欠点を解決するた
めに,電源投入時にハードウエア的にメモリの初期化を
行なうことにより,容易に且つ高い信頼性でダイアラー
ICの誤操作によるまちがい電話を防止することを目的と
している。Therefore, according to the present invention, in order to solve such drawbacks of the related art, the memory is initialized by hardware when the power is turned on, so that the dialer can be easily and highly reliable.
The purpose is to prevent wrong phone calls due to incorrect operation of the IC.
上記問題点を解決するために,この発明は電話番号の最
初の一桁乃至複数桁を記憶するRAMメモリセルに初期化
信号入力端子を設け,電源投入時にパワーオンリセツト
信号等を用いて該RAMにエンドコードが書き込まれる様
にした。In order to solve the above-mentioned problems, the present invention provides an initialization signal input terminal in a RAM memory cell for storing the first digit or a plurality of digits of a telephone number, and uses the power-on reset signal or the like when the power is turned on. The end code is written in.
上記の様に構成されたRAMを内蔵した電話用ダイアラーI
Cでは電話番号未記入のアドレスがアクセスされると,
エンドコードが読み出され,エンドコード検出ゲートの
出力が制御回路に入力されて直ちにRAMのアクセスは停
止され,出力発生回路の出力も停止される。このためま
ちがい電話が防止できるのである。Telephone dialer I with built-in RAM configured as above
In C, when an address without a telephone number is accessed,
The end code is read, the output of the end code detection gate is input to the control circuit, the access to the RAM is immediately stopped, and the output of the output generation circuit is also stopped. For this reason, wrong phone calls can be prevented.
以下にこの発明の実施例を図面にもとづいて説明する。
第1図においてRAMのアドレスカウンタ1の出力2,3は,
それぞれYアドレスデコーダ4,Xアドレスデコーダ5に
入力されている。初期化信号入力端子付RAM6は,各電話
番号格納アドレスの最初の桁内至複数桁に位置し,他は
通常のRAM7によりメモリ全体が構成されている。初期化
信号入力端子付RAM6には,パルス発生回路8の出力9が
入力される。この出力9は,さらに制御回路10にも入力
され,制御部の初期化を行なう。メモリの出力11は,REA
D/WRITEバッフア12より出力発生回路13及びエンドコー
ド検出ゲート14に入力される。検出ゲート14の出力15が
制御回路10に入力されて,制御回路10の出力16,17,18が
それぞれ出力発生回路13,READ/WRITEバツフア12,アドレ
スカウンタ1に入力される。この結果,RAMの出力にエン
ドコードが検出されると直ちに出力,RAMの読み出し,ア
ドレスカウンタのインクリメントが停止する。入力信号
19は通常,同一集積回路上に設けられたキーボードイン
ターフエース回路(図示されていない)を通して外部の
キーボード(図示されていない)より入力される。Embodiments of the present invention will be described below with reference to the drawings.
In FIG. 1, the outputs 2 and 3 of the RAM address counter 1 are
It is inputted to the Y address decoder 4 and the X address decoder 5, respectively. The RAM 6 with the initialization signal input terminal is located in the first digit to the plural digits of each telephone number storage address, and the other RAM 7 constitutes the entire memory. The output 9 of the pulse generation circuit 8 is input to the RAM 6 with the initialization signal input terminal. The output 9 is also input to the control circuit 10 to initialize the control unit. Memory output 11 is REA
Input from the D / WRITE buffer 12 to the output generation circuit 13 and the end code detection gate 14. The output 15 of the detection gate 14 is input to the control circuit 10, and the outputs 16, 17, and 18 of the control circuit 10 are input to the output generation circuit 13, the READ / WRITE buffer 12, and the address counter 1, respectively. As a result, as soon as the end code is detected in the RAM output, output, RAM reading, and address counter increment stop. input signal
19 is normally input from an external keyboard (not shown) through a keyboard interface circuit (not shown) provided on the same integrated circuit.
なお,第2図(a)はRAM6の第1の詳細回路図,同様に
第2図(b),(c)はそれぞれRAM6の第2,第3の詳細
回路図である。2 (a) is a first detailed circuit diagram of the RAM 6, and similarly, FIGS. 2 (b) and 2 (c) are second and third detailed circuit diagrams of the RAM 6, respectively.
この発明は以上説明したように,簡単な構成でメモリの
初期化を行なうことにより,電話用ダイアラーICのまち
がい電話を防止できるという効果がある。As described above, the present invention has an effect that it is possible to prevent an erroneous call of a telephone dialer IC by initializing the memory with a simple configuration.
第1図はこの発明の実施例のブロツク図,第2図
(a),(b),(c)は,それぞれこの発明にかかる
初期化信号入力端子付RAMの第1,第2及び第3の詳細回
路図である。 6……初期化信号入力端子付RAM 7……RAM 8……パルス発生回路 10……制御回路 13……出力発生回路 14……エンドコード検出ゲートFIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 (a), (b), and (c) are first, second, and third of a RAM with an initialization signal input terminal according to the present invention, respectively. 3 is a detailed circuit diagram of FIG. 6 ... RAM with initialization signal input terminal 7 ... RAM 8 ... Pulse generator circuit 10 ... Control circuit 13 ... Output generator circuit 14 ... End code detection gate
Claims (4)
記パルス発生回路の出力によりその内容が初期化される
初期化信号入力端子付書き換え可能な記憶装置を各電話
番号格納アドレスの1桁目乃至最初の複数桁に持つ書き
換え可能な記憶装置と,前記書き換え可能な記憶装置の
出力からデータ終了符号を検出する検出ゲートと,前記
検出ゲートの出力を受けて前記記憶装置の読み出しを停
止する制御回路と,前記制御回路により制御され前記記
憶装置から読み出されたデータに対応する出力を発生
し,且つ前記検出ゲートの出力を受けた前記制御回路に
よりその出力発生が停止される出力信号発生回路とから
成る電話用半導体集積回路。1. A circuit for generating a pulse when the power is turned on and a rewritable storage device with an initialization signal input terminal, the contents of which are initialized by the output of the pulse generation circuit, in the first digit of each telephone number storage address. To a rewritable memory device having a plurality of first digits, a detection gate for detecting a data end code from the output of the rewritable memory device, and a control for receiving the output of the detection gate and stopping the reading of the memory device Circuit, and an output signal generation circuit controlled by the control circuit to generate an output corresponding to the data read from the storage device, and the generation of the output is stopped by the control circuit receiving the output of the detection gate And a semiconductor integrated circuit for telephones.
力を互いに他の入力に接続した2入力NRゲートとイ
ンバータとにより構成されることを特徴とする特許請求
の範囲第1項記載の電話用半導体集積回路。2. The storage device with an initialization signal input terminal is constituted by a two-input NR gate whose output is connected to another input and an inverter, according to claim 1. Telephone semiconductor integrated circuit.
力を互いに他の入力に接続した2入力NANDゲートとイン
バータとにより構成されることを特徴とする特許請求の
範囲第1項記載の電話用半導体集積回路。3. The storage device with an initialization signal input terminal is configured by a two-input NAND gate whose output is connected to another input and an inverter, according to claim 1. Telephone semiconductor integrated circuit.
力を互いに他の入力に接続した一対のインバータより成
るフリツプフロツプと,前記フリツプフロツプの一方の
出力と或る電位との間に電気的に接続されたスイツチン
グ素子とから構成されることを特徴とする特許請求の範
囲第1項記載の電話用半導体集積回路。4. A storage device with an initialization signal input terminal is electrically connected between a flip-flop composed of a pair of inverters whose outputs are connected to other inputs, and between one output of the flip-flop and a certain potential. 2. The telephone semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit comprises a connected switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199954A JPH073983B2 (en) | 1985-09-10 | 1985-09-10 | Telephone semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199954A JPH073983B2 (en) | 1985-09-10 | 1985-09-10 | Telephone semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6260341A JPS6260341A (en) | 1987-03-17 |
| JPH073983B2 true JPH073983B2 (en) | 1995-01-18 |
Family
ID=16416360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60199954A Expired - Lifetime JPH073983B2 (en) | 1985-09-10 | 1985-09-10 | Telephone semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073983B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033329B2 (en) * | 1979-01-23 | 1985-08-02 | アンリツ株式会社 | automatic dialing device |
-
1985
- 1985-09-10 JP JP60199954A patent/JPH073983B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6260341A (en) | 1987-03-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
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| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
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| EXPY | Cancellation because of completion of term |