JPH0740060B2 - On-board scan test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention is an on-board scan suitable for testing an LSI having a scan test function by an external scan ring mounted on a printed board. Regarding test equipment.

(Prior Art) A scan test method is one of means for facilitating testing of LSIs, particularly VLSIs. In this scan test method, all flip-flops (F / Fs) inside the LSI are connected so as to function as shift registers, data is serially shifted in, data is set in each F / F, and then one clock The system operation is performed, the data of each F / F is serially shifted out, and the operation of each F / F and the random logic (combination circuit) between the F / Fs are tested. However, this method has a problem that it is impossible to set and observe the input signal from the outside of the LSI and the output signal to the outside.

Therefore, as shown in FIG. 2, an F / F 12 for external scan corresponding to each input / output signal is formed on the LSI 11 and these F / F 12 are formed.
A method of connecting / F12 serially and providing an external scan ring is being considered. In this system, the input section is constructed as shown in FIG. According to the configuration of FIG. 3, the data set in the external scan F / F 12 by the shift operation is the tri-state buffer (3-ST buffer) 13
Is enabled and is taken out to a pad (bonding pad) 14 (for input). Therefore,
By taking in the data taken out to the pad 14 into the system, the same effect as when the data (system input data) is inputted from the outside (to the pad 14) is given. On the other hand, the output section is constructed as shown in FIG. According to the configuration of FIG. 4, the selector 15 is set to the pad 16 (for output) during the test.
By switching to the side, the data output from the inside of the system to the pad 16 (system output data) can be taken into the external scan F / F 12. After that, by returning the selector 15 to the original position and taking it out by shift-out, the result of the system can be observed.

Now, when the LSI 11 having the scan test function by the external scan ring as described above is mounted on a printed board (printed circuit board) and used, in a normal state, as shown in FIG. An active signal (system input signal) is given from the circuit element 21. Therefore, in order to set the input of the scan test for the LSI 11, when the data is taken out from the inside of the LSI 11 to the pad 14 through the 3-ST buffer 13 as described in FIG. Data collision occurs and correct data cannot be set.

(Problems to be Solved by the Invention) As described above, in a system in which an LSI having a scan test function by an external scan ring is mounted on a printed board, when setting an input for a scan test, the setting data is Then, a collision occurs with a system input signal input from the outside of the LSI, and there is a problem that the LSI scan test cannot be performed in the state where the LSI is mounted on the printed board.

Therefore, an object of the present invention is to make it possible to perform a scan test of a single LSI having a scan test function by an external scan ring even when mounted on a printed board.

[Structure of the Invention] (Means for Solving the Problems) The present invention is an LSI mounted on a printed board and having a scan test function by an external scan ring.
An input buffer means for controlling the input of a system input signal for I to the LSI, and a control means for controlling the execution of a scan test for the LSI, the input buffer means during the scan test. And a control means for setting the means to the output disable state.

(Operation) According to the above configuration, the input buffer means is set to the output disable state under the control of the control means, thereby preventing the system input signal from being input to the LSI in the normal state (system operating state). To be done. In this state, the input setting for the scan test by the external scan ring can be correctly performed without being influenced by the system input signal. Therefore, by setting the input buffer means in the output disable state as described above during the scan test, the control means can perform the scan test of the above LSI alone with the same LSI mounted on the printed board. .

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, and 21 is an LSI similar to the LSI 11 shown in FIG. 2 having a scan test function by an external scan ring. LSI21
Is mounted on a print board (not shown), and has the same well-known configuration as the input section shown in FIG. 3 and the output section shown in FIG. 22,23 are system input signals (to LSI21) generated by system operation, and 24,25 are signals 22,23
3-ST (tri-state) that controls the input to the LSI21
The buffers 26 and 27 are input terminals of the LSI 21 to which the outputs of the 3-ST buffers 24 and 25 are connected (similar to the input terminal 17 of FIG. 5). There are system input signals to the LSI 21 other than the signals 22 and 23, and some 3-ST buffers for inputting these signals to the corresponding input terminals (not shown) of the LSI 21 are also provided. It exists but is omitted in FIG. That is, in this embodiment, the 3-ST buffer is prepared for all system input signals to the LSI 21.

Reference numeral 31 is a control circuit for controlling execution of scan tests of various LSIs mounted on a printed board such as LSI 21, 32 is a scan test signal path used for execution control of scan tests for the LSI 21 by the control circuit 31, 33 Is the control circuit
This is a control signal that becomes high level during the scan test of the LSI 21 by the 31. This control signal 33 is 3
-Used to set the ST buffers 24, 25, etc. to the output disable state. 34 is an inverter that inverts the level of the control signal 33, 35 is a control signal generated by the system operation for controlling the 3-ST buffer 25, and 36 is a 3-ST controlled by the control signal 35 in the normal state. A gate, for example, a NAND gate, for forcibly setting the buffer 25 to the output disable (output high impedance) state according to the output signal of the inverter 34 during the scan test.

Next, the operation of the configuration shown in FIG. 1 will be described.

First, during a normal system operation period, the control signal 33 from the control circuit 31 is at a low level (low level). In this case, the 3-ST buffer 24 is in the output enable state, and the system input signal 22 generated by the system operation is 3
-Input to the input terminal 26 of the LSI 21 via the ST buffer 24. Further, since the output signal of the inverter 34 is high level (high level) while the control signal 33 is low level, the level of the output signal of the NAND gate 36 is the level inversion signal of the control signal 35 generated by the system operation. Matches
The 3-ST buffer 25 is controlled according to the control signal 35.
As a result, the system input signal generated by the system operation
23 via 3-ST buffer 25 in response to control signal 35
It is input to the input terminal 27 of the LSI 21. That is, in this embodiment,
While the control signal 33 from the control circuit 31 is at the low level, all system input signals including the signals 22 and 23 are given to the LSI 21 in a state according to the expected value of the system.

Next, with the LSI21 mounted on the printed board,
The operation when performing the 21 scan test will be described. In this case, first, the control signal 33 from the control circuit 31 is switched to the high level. When the control signal 33 becomes high level, the 3-ST buffer 24 is in the output disable state, and the system input signal 22 is prevented from being input to the input terminal 26 of the LSI 21. When the control signal 33 becomes high level, the output signal of the NAND gate 36 is the control signal 35 generated by the system operation.
It goes high regardless of the state. As a result, 3-ST
The buffer 25 is also forced to the output disable state,
The system input signal 23 is prevented from being input to the input terminal 27 of the LSI 21. That is, in this embodiment, when the control signal 33 from the control circuit 31 becomes high level, input of all system input signals to the LSI 21, including the signals 22 and 23, is blocked. In this state, the control circuit 31 scans data to the LSI 21 via the scan test signal path 32, sets input data via a pad (not shown) of the LSI 21, operates a single system, and scans output data via the pad. The LSI 21 is independently tested on the printed board by performing a series of well-known operations such as fetching to the F / F (not shown) and scanning out the data fetched to the F / F.

[Effect of the Invention] As described in detail above, according to the present invention, even when an LSI having a scan test function by an external scan ring is mounted on a printed board, during the scan test period,
Since the system input signal can be prevented from inputting to the LSI regardless of the system operation, this state can be used to correctly perform the LSI independent test on the printed board without being affected by the system operation. Therefore, when a plurality of LSIs are mounted on the same printed board, it becomes possible to identify the faulty LSI, and by separating from the faults other than the LSIs, the fault location can be identified early.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic diagram of an ordinary LSI having a scan test function by an external scan ring, and FIG. 3 is an input section of the LSI shown in FIG. FIG. 4 is a diagram showing the configuration, FIG. 4 is a diagram showing the configuration of the output section of the LSI of FIG. 2, and FIG. 5 is a diagram showing the interface section between the input section of the LSI of FIG. 2 and the outside of the LSI. 21 …… LSI, 22,23 …… System input signal, 24,25 …… 3
-ST (tri-state) buffer, 31 ... Control circuit,
33 …… Control signal.

Claims (1)

[Claims] 1. A system in which an LSI (large-scale integrated circuit) having a scan test function by an external scan ring is mounted on a printed board, and an input buffer which controls input of a system input signal intended for the LSI to the LSI. Means and a control means for controlling execution of a scan test targeting the LSI, the control means for setting the input buffer means in an output disable state during the scan test. On-board scan test equipment.