JPS6225212B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention provides a scan loop circuit configured by cascading a plurality of flip-flops. This invention relates to a scan loop circuit control method that prevents a state output circuit from causing bus collision.

(b) Prior Art and Problems In recent years, the degree of integration of LSIs has increased, and a large number of circuit elements have come to be housed in one LSI. In this case, as a method to facilitate LSI diagnosis, a scan loop method is often used in which internal flip-flops are connected in the form of a shift register. This scan loop is generally used for LSI
This loop is intended to improve the diagnostic efficiency of printed (PT) boards equipped with this LSI, but in certain data processing systems, this loop is used to collect log (LOG) information or provide services. It realizes various service functions from the processor (SVP). In such data processing systems, several LSI chips are mounted on a printed board, and one
One loop is constructed by configuring two shift registers, connecting their outputs to the inputs of the shift registers in the service processor, and using the outputs of the shift registers in the service processor as scan-in data to the printed circuit board. Configure.
Then, while performing the shift operation, the service processor reads out the values of each flip-flop in the scan loop and displays them on a screen or the like. When one round of shift operations for the scan loop is completed, the state of each flip-flop returns to its original state.

Additionally, it is also possible to scan data into certain flip-flops. That is, by performing an appropriate shift on the scan loop, the state of the target flip-flop is loaded into the shift register in the service processor, the service processor rewrites the bits corresponding to the flip-flop, and by shifting one round again, the state of the target flip-flop is transferred. Any pattern can be set.

By the way, if a certain pattern is set in one flip-flop and another flip-flop during and after such an operation, a bus collision will occur at the output of the tristate output circuit controlled by these flip-flops. there is a possibility. Therefore, in order to prevent this bus collision, a bus collision prevention circuit as shown in FIGS. 1 and 2 has been devised. In Figures 1 and 2, 1 and 2 are LSIs or printed boards made of a set of these, 3 to 8 are flip-flops,
9 and 10 are tri-state output circuits, 11 is a dot-OR coupled common bus, 12 and 13 are AND gates, 14 is a scan-in terminal, and 15 is a scan-out terminal.

The circuit of FIG.
This circuit is designed to prevent the two outputs from outputting at the same time. In the circuit shown in FIG. 1, the flip-flop 7
There is a problem in that it takes time to finally put the other party's tri-state output circuit 9 in an output inhibited state due to the output of , and in some cases bus collisions cannot be sufficiently prevented. For this reason, the circuit shown in FIG. 2 has been considered.

The circuit shown in FIG. 2 prohibits the input operation to the flip-flop 4 that controls the other tri-state output circuit 9 by the output of the flip-flop 6 in the preceding stage of the flip-flop 7 that controls one of the tri-state output circuits 10. Accordingly, the control signal input timings to the tri-state output circuits 9 and 10 are made to match.

In normal circuit operation, if the circuit format shown in Figure 2 is adopted, there is no risk of bus collision. When operated in scan mode, flip-flop 4 shown in Figure 2
There is a possibility that flip-flop 7 and flip-flop 7 will be turned on at the same time. In order to prevent this, in the scan mode, a scan mode signal (not shown) is input to the tri-state output circuits 9 and 10 shown in the figure to force both the tri-state output circuits 9 and 10 to be in a prohibited state. I have to.
However, if a pattern that causes a bus collision is mistakenly scanned in, and then the scan mode is canceled and the system starts operating, a bus collision may occur and the LSI may be destroyed.

(c) Purpose of the Invention The present invention aims to prevent bus collisions such as those described above from occurring during scan operation even when a circuit format as shown in FIG. 2 is adopted in a system capable of having a printed board configuration. The purpose is

(d) Structure of the Invention In order to achieve the above object, the present invention provides a scan loop in which a plurality of flip-flops each having a normal operation input and a scan operation input are connected in cascade using the scan operation inputs. A circuit section that is configured as a circuit, controls a tri-state output circuit in which N flip-flops among the plurality of flip-flops are connected to the same common bus, and further controls a specific one of the tri-state circuits. In a processing device configured to cause a flip-flop that controls another tri-state output circuit to set data that does not cause a bus collision based on a signal from the flip-flop that controls the other tri-state output circuit, the flip-flop that controls the other tri-state output circuit is excluded from the scan loop circuit. When operating the entire scan loop circuit, the flip-flop that controls the other tri-state output circuit is excluded from the scan loop, and the excluded flip-flop is loaded with data that will not cause the bus collision. It is characterized by setting.

(e) Embodiment of the invention FIG. 3 is a block diagram of an embodiment of the invention, in which 20 and 21 are LSIs, 22 to 27 are flip-flops, 28 and 29 are tri-state output circuits, and 30 is a dot.・OR-coupled common bus, 31 is an AND gate, 32 and 33 are selection gates, 34 is a scan-in terminal, 35 is a scan-out terminal, 36 is a printed board test mode signal terminal, 37 and 38 are scan mode signal lines, 39
4 is a clock control circuit, 40 is an A clock input terminal, 41 is a B clock input terminal, 42 is a scan mode signal input terminal, 43 is a normal clock input terminal, 44 is a normal clock line, and 45 is a shift clock line.

4 is a block diagram of a service processor that controls scan-in, scan-out operations, etc. of the system of the embodiment shown in FIG. 3. In the diagram,
50 is a processor, 51 is a shift register, 52
53 is a shift clock control circuit, 53 is a parallel load and data line, 54 is a clock control line, 55 is a scan-out data input terminal, 56 is a scan-in data output terminal, 57 is an A clock terminal, 5
8 is a B clock terminal, and 59 is a scan mode signal terminal.

The operation of the embodiment is as follows. During normal operation, the printed board test mode signal terminal 3
6, the selection gate 32 selects the output of the flip-flop 22 and inputs it to the flip-flop 23, and the selection gate 33 selects the output of the flip-flop 23 and inputs it to the flip-flop 24. In addition, scan mode signal lines 37, 3
8 sets the tri-state output circuits 28 and 29 to a non-inhibited state. As a result, the circuit of the embodiment shown in FIG. 3 performs the same operation as the circuit shown in FIG. 2 described above.

Next, during scan mode operation, scan mode signal lines 37 and 38 inhibit tristate output circuits 28 and 29, as in the conventional example. At the same time, in response to a signal from the printed circuit board test mode signal terminal 36, the selection gate 32 selects the output of the AND gate 31 and inputs it to the flip-flop 23, and the selection gate 33 selects the output of the flip-flop 22 and inputs it to the flip-flop 24.
Enter.

As a result, the flip-flop group shown in FIG. 3 constitutes a scan loop with flip-flop 23 excluded. Data controlled by the output of the flip-flop 25, that is, the same data as should be set in the flip-flop 4 in the configuration shown in FIG. 2, is set in the flip-flop 23. Therefore,
Even if the scan mode signal lines 37 and 38 accidentally disable the tristate output circuits 28 and 29, the relationship between the two tristate output circuits 28 and 29 will be the same as in the case shown in FIG. 2, and bus collision will not occur. It will no longer occur.

In this way, when performing a scan operation from the service processor shown in FIG. 4 to the system shown in FIG. The safety of the system is maintained even in the event of operator error.

Note that when diagnosing a single printed board, it is possible to test one scan loop including the flip-flop 23 shown in the figure using diagnostic data from which patterns that cause bus collisions have been deleted, so there is no reduction in the diagnostic rate. do not have.

(F) Effects of the Invention As described above, according to the present invention, bus collisions can be effectively prevented when performing scan-in and scan-out for a system consisting of multiple printed circuit boards, and the reliability of the system during diagnosis can be improved. can be improved.

[Brief explanation of the drawing]

1 and 2 are examples of a bus collision prevention circuit, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of a service processor. In Figure 3, 20 and 21 are LSI, 22 to 2
7 is a flip-flop, 28 and 29 are tri-state output circuits, 30 is a common bus, 31 is an AND gate, and 32 and 33 are selection gates.

Claims (1)

[Claims] 1 A plurality of flip-flops each having an input for normal operation and an input for scan operation are connected in cascade using the input for normal operation to form a scan loop circuit, and N flip-flops among the plurality of flip-flops are control tri-state output circuits connected to the same common bus, and a signal from a circuit section controlling a particular one of the tri-state circuits connects the bus to a flip-flop controlling another tri-state output circuit. In a processing device configured to set data that does not cause collisions, when the flip-flop controlling the other tri-state output circuit is excluded from the scan loop circuit, and the entire scan loop is operated, the other A scan loop circuit control method characterized in that a flip-flop that controls a tri-state output circuit is operated while being excluded from the scan loop, and data that does not cause the bus collision is set in the excluded flip-flop.