JPH0740632B2 - Method for manufacturing hybrid integrated circuit - Google Patents
Method for manufacturing hybrid integrated circuitInfo
- Publication number
- JPH0740632B2 JPH0740632B2 JP63144028A JP14402888A JPH0740632B2 JP H0740632 B2 JPH0740632 B2 JP H0740632B2 JP 63144028 A JP63144028 A JP 63144028A JP 14402888 A JP14402888 A JP 14402888A JP H0740632 B2 JPH0740632 B2 JP H0740632B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- hybrid integrated
- integrated circuit
- resin thin
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000000034 method Methods 0.000 title description 4
- 239000011347 resin Substances 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 21
- 239000011231 conductive filler Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 239000000945 filler Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910000760 Hardened steel Inorganic materials 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は低熱抵抗回路基板を用いた混成集積回路の製造
方法に関する。The present invention relates to a method for manufacturing a hybrid integrated circuit using a low thermal resistance circuit board.
（ロ）従来の技術 本願出願人はすでに特公昭46−13234号公報に厚膜混成
集積回路の組み込みに適した金属基板を用いた低熱抵抗
回路基板を開発した。斯る基板はアルミニウム板の表面
を陽極酸化として酸化アルミニウム被膜で被覆したもの
であり、その表面に約30μの厚さのエポキシ樹脂で銅箔
を接着している構造なので熱抵抗は１cm2の面積あたり
1.3℃/W程度であった。(B) Conventional technology The applicant of the present application has already developed a low thermal resistance circuit board using a metal substrate suitable for incorporating a thick film hybrid integrated circuit in Japanese Patent Publication No. 46-13234. Such a substrate is an aluminum plate whose surface is covered with an aluminum oxide film for anodic oxidation, and a copper foil is adhered to the surface with an epoxy resin with a thickness of about 30μ, so the thermal resistance is an area of 1 cm 2 . Around
It was about 1.3 ° C / W.
最近集積化の要請より、更に大出力回路をも組み込みで
きる低熱抵抗基板が提案された。この基板はアルミニウ
ム等の良熱伝導性金属基板の一主面に多量のアルミナ
（Al2O3）を含有したエポキシ樹脂層を薄く付着した構
造を有し、樹脂層の厚さが60μと２倍になったにもかか
わらず、熱抵抗は0.8℃/Wと改善されている。Recently, due to the demand for integration, a low thermal resistance substrate has been proposed which can incorporate a larger output circuit. This substrate has a structure in which an epoxy resin layer containing a large amount of alumina (Al 2 O 3 ) is thinly attached to one main surface of a metal substrate with good thermal conductivity such as aluminum, and the thickness of the resin layer is 60 μ and 2 μm. Despite the doubling, the thermal resistance is improved to 0.8 ℃ / W.
（ハ）発明が解決しようとする課題 しかしながら斯上の基板を用いて混成集積回路を生産す
ると大きな問題が生じた。これは一枚の基板に多数個の
混成集積回路を形成した後にプレスで各混成集積回路に
打抜く工程で、プレス金型の寿命が従来の基板が100万
ショットであるのに対しこの基板では5000ショットで摩
耗してしまうのである。この原因はアルミナにある。即
ちアルミナのモース硬度は９であり、プレス金型を形成
する焼入れ鋼のモース硬度は約6.5でありプレス金型の
側面を削る。即ち、プレス金型の寿命を著しく低下させ
る大きな問題点があった。(C) Problems to be Solved by the Invention However, when a hybrid integrated circuit is produced using the above substrate, a big problem occurs. This is a process of forming a large number of hybrid integrated circuits on one substrate and then punching each hybrid integrated circuit with a press.The life of the press die is 1 million shots in the conventional substrate, whereas in this substrate It will wear out after 5000 shots. This is due to alumina. That is, the Mohs hardness of alumina is 9, and the hardened steel forming the press die has a Mohs hardness of about 6.5, and the side surface of the press die is ground. That is, there is a big problem that the life of the press die is remarkably reduced.
（ニ）課題を解決するための手段 本発明は上述した問題点に鑑みて為されたものであり、
短冊状の金属基板を準備し、前記基板上の複数の所定領
域に高熱伝導性フィラーが含有された絶縁樹脂薄層をス
クリーン印刷し、前記高熱伝導性フィラーを含有する前
記絶縁樹脂薄層が印刷された以外の前記基板領域上に絶
縁層を形成し、前記高熱伝導性フィラーが含有された絶
縁樹脂薄層上に所望形状の回路導体を形成し、前記回路
導体上に回路素子を固着した後、前記絶縁樹脂薄層近傍
の前記絶縁層領域の前記基板をプレス打抜きし、個々の
混成集積回路に分離して解決する。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems,
Preparing a strip-shaped metal substrate, screen-printing an insulating resin thin layer containing a high thermal conductive filler in a plurality of predetermined regions on the substrate, the insulating resin thin layer containing the high thermal conductive filler is printed After forming an insulating layer on the substrate area other than the above, forming a circuit conductor of a desired shape on the insulating resin thin layer containing the high thermal conductive filler, after fixing the circuit element on the circuit conductor The substrate in the insulating layer region in the vicinity of the insulating resin thin layer is punched by a press and separated into individual hybrid integrated circuits to solve the problem.
（ホ）作用 この様に本発明に依れば、高熱伝導性フィラーが含有さ
れた絶縁樹脂薄層を直接プレス金型で切断することがな
いので、従来の問題点を大幅に改善した低熱抵抗回路基
板を用いた混成集積回路を提供することができる。(E) Action As described above, according to the present invention, the insulating resin thin layer containing the high thermal conductive filler is not directly cut by the press die, so that the conventional problems are greatly improved. A hybrid integrated circuit using a circuit board can be provided.
（ヘ）実施例 以下に図面を参照して本発明の一実施例を詳述する。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.
本発明の第１の工程は第１図Ａに示す如く、短冊状の金
属基板（１）を準備することにある。金属基板（１）は
アルミニウムが適しており、アルミニウム板の表面に陽
極酸化により酸化アルミニウム薄層を形成した絶縁金属
板を用いる。斯る金属基板（１）上には所定の間隔で所
定領域、即ち、低熱抵抗回路基板となる領域に高熱伝導
性フィラー（２）が含有された絶縁樹脂薄層（３）をス
クリーン印刷により所定の膜厚で付着する。The first step of the present invention is to prepare a strip-shaped metal substrate (1) as shown in FIG. 1A. Aluminum is suitable for the metal substrate (1), and an insulating metal plate having a thin aluminum oxide layer formed on the surface of the aluminum plate by anodic oxidation is used. On such a metal substrate (1), a predetermined area is formed at predetermined intervals, that is, an insulating resin thin layer (3) containing a high thermal conductive filler (2) in a predetermined area of a low thermal resistance circuit board by screen printing. It adheres with a film thickness of.
絶縁樹脂薄層（３）はエポキシ樹脂、ポリイミド樹脂、
フェノール樹脂、プラチラール樹脂等の樹脂が用いら
れ、その樹脂中にプレス金型よりもモース硬度の大きい
Al2O3,AlN,SiC,ダイヤモンド及び金型よりモース硬度は
小さいが特に熱伝導性の優れたBN等のフィラー（２）が
10％〜80％重量比で混入されている。The insulating resin thin layer (3) is made of epoxy resin, polyimide resin,
A resin such as phenol resin or pratillal resin is used, and its Mohs hardness is higher than that of the press die.
Filler (2) such as BN, which has a lower Mohs hardness than Al 2 O 3 , AlN, SiC, diamond and metal molds but has particularly good thermal conductivity, is used.
It is mixed in 10% to 80% weight ratio.
本発明の第２の工程は第１図Ｂに示す如く、高熱伝導性
フィラー（２）を含有した絶縁樹脂薄層（３）が印刷さ
れた以外の領域に絶縁層（４）を形成するところにあ
る。In the second step of the present invention, as shown in FIG. 1B, the insulating layer (4) is formed in a region other than the region where the insulating resin thin layer (3) containing the high thermal conductive filler (2) is printed. It is in.
絶縁層（４）は絶縁樹脂薄層（３）と同じ樹脂が用いら
れ、スクリーン印刷により絶縁樹脂薄層（３）と同一膜
厚となる様に付着させる。また。絶縁層（４）中に高熱
伝導性フィラーを含有させることも可能であるこの場合
の高熱伝導性フィラーはプレス金型のモース硬度より小
さいものを使用する。The insulating layer (4) is made of the same resin as the insulating resin thin layer (3) and is attached by screen printing so as to have the same thickness as the insulating resin thin layer (3). Also. It is also possible to include a high thermal conductive filler in the insulating layer (4). In this case, the high thermal conductive filler used is smaller than the Mohs hardness of the press die.
本発明の第３の工程は第１図Ｃに示す如く、絶縁樹脂薄
層（３）上に所望形状の回路導体（５）を形成し、その
回路導体（５）上に複数の回路素子（６）を固着する。In the third step of the present invention, as shown in FIG. 1C, a circuit conductor (5) having a desired shape is formed on the insulating resin thin layer (3), and a plurality of circuit elements () are formed on the circuit conductor (5). Fix 6).
回路導体（５）は絶縁樹脂薄層（３）及び絶縁層（４）
全面に銅箔を貼着して絶縁樹脂薄層（３）上のみに回路
導体（５）を形成する様にエッチングする。このとき銅
箔の片面には接着剤があらかじめ付着されており、絶縁
樹脂薄層（３）及び絶縁層（４）との接着性は十分であ
る。The circuit conductor (5) is an insulating resin thin layer (3) and an insulating layer (4).
A copper foil is attached to the entire surface and etched so that the circuit conductor (5) is formed only on the insulating resin thin layer (3). At this time, an adhesive is previously attached to one surface of the copper foil, and the adhesiveness with the insulating resin thin layer (3) and the insulating layer (4) is sufficient.
回路導体（５）上にはトランジスタ、集積回路、チップ
部品等の複数の回路素子（６）を固着し、必要とされる
ものは近傍の回路導体（５）とワイヤ等で接続する。A plurality of circuit elements (6) such as transistors, integrated circuits, chip parts and the like are fixed on the circuit conductor (5), and necessary ones are connected to neighboring circuit conductors (5) by wires or the like.
本発明の第４の工程は第１図Ｄに示す如く、絶縁樹脂薄
層（３）近傍の絶縁層（４）領域の基板（１）をプレス
金型（７）でプレス打抜きを行い第１図Ｅに示す如く、
個々の混成集積回路（８）に分離するところにある。In the fourth step of the present invention, as shown in FIG. 1D, the substrate (1) in the region of the insulating layer (4) near the insulating resin thin layer (3) is punched by a press die (7). As shown in Figure E,
It is about to be separated into individual hybrid integrated circuits (8).
このときのプレス金型（７）のプレス面は回路素子
（６）と接しない様に凹型に形成されていることが望ま
しい。At this time, the pressing surface of the pressing die (7) is preferably formed in a concave shape so as not to contact the circuit element (6).
斯る本発明に依れば、高熱伝導性フィラー（２）が含有
された絶縁樹脂薄層（３）をプレス金型（７）でプレス
打抜きすることなく、低熱抵抗用の混成集積回路（８）
を形成することができ、プレス金型（７）が摩耗されず
プレス金型（７）の寿命を著しく延ばすことができる。According to the present invention, the hybrid integrated circuit (8) for low thermal resistance is formed without punching the insulating resin thin layer (3) containing the high thermal conductive filler (2) with the press die (7). )
Can be formed, and the life of the press die (7) can be remarkably extended without abrasion of the press die (7).
（ト）発明の効果 以上に詳述した如く、本発明に依れば、高熱伝導性フィ
ラーを含有する絶縁樹脂薄層を直接プレス金型によって
プレス打抜きしないためプレス金型の寿命を著しく延ば
すと同じに低熱抵抗用の混成集積回路を個々に分離する
ことができる。(G) Effect of the Invention As described above in detail, according to the present invention, the insulating resin thin layer containing the high thermal conductive filler is not directly punched by the press die, so that the life of the press die can be remarkably extended. Similarly, hybrid integrated circuits for low thermal resistance can be individually isolated.
また本発明ではプレス金型で直接絶縁樹脂薄層をプレス
打抜きしないため、モース硬度の高いフィラーを絶縁樹
脂薄層中に含有させることができることにより、高い熱
伝導率を有する混成集積回路を容易に提供することがで
きる。Further, in the present invention, since the insulating resin thin layer is not directly punched by a press die, a filler having a high Mohs hardness can be contained in the insulating resin thin layer, so that a hybrid integrated circuit having high thermal conductivity can be easily obtained. Can be provided.
第１図Ａ乃至第１図Ｅは本発明の実施例を説明する断面
工程図である。 （１）…金属基板、（２）…高熱伝導性フィラー、
（３）…絶縁樹脂薄層、（４）…絶縁層、（５）…回路
導体、（６）…回路素子、（７）…プレス金型。1A to 1E are sectional process drawings for explaining an embodiment of the present invention. (1) ... Metal substrate, (2) ... High thermal conductivity filler,
(3) ... Insulating resin thin layer, (4) ... Insulating layer, (5) ... Circuit conductor, (6) ... Circuit element, (7) ... Press die.
Claims (1)
形成予定の多数個の混成集積回路領域に高熱伝導性フィ
ラーが含有された絶縁樹脂薄層を形成し、 前記高熱伝導性フィラーを含有する前記絶縁樹脂薄層が
形成された混成集積回路領域間上に前記絶縁樹脂薄層と
ほぼ同じ膜厚でフィラーの含有していない絶縁層を形成
し、 前記高熱伝導性フィラーが含有された絶縁樹脂薄層上に
所望形状の回路導体を形成し、前記回路導体上に回路素
子を固着した後、 前記絶縁樹脂薄層間の前記絶縁層領域に対応する前記金
属基板をプレス打抜きし、個々の混成集積回路に分離す
ることを特徴とする混成集積回路の製造方法。1. A metal substrate is prepared, and a thin insulating resin layer containing a high thermal conductive filler is formed on a large number of hybrid integrated circuit regions to be formed on the metal substrate. An insulating layer not containing a filler is formed with a film thickness substantially the same as the insulating resin thin layer between the mixed integrated circuit regions in which the insulating resin thin layer containing is formed, and the high thermal conductive filler is contained. A circuit conductor having a desired shape is formed on the insulating resin thin layer, and after a circuit element is fixed on the circuit conductor, the metal substrate corresponding to the insulating layer region between the insulating resin thin layers is punched out, A method of manufacturing a hybrid integrated circuit, characterized in that the hybrid integrated circuit is separated into individual hybrid integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63144028A JPH0740632B2 (en) | 1988-06-10 | 1988-06-10 | Method for manufacturing hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63144028A JPH0740632B2 (en) | 1988-06-10 | 1988-06-10 | Method for manufacturing hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01312890A JPH01312890A (en) | 1989-12-18 |
| JPH0740632B2 true JPH0740632B2 (en) | 1995-05-01 |
Family
ID=15352644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63144028A Expired - Fee Related JPH0740632B2 (en) | 1988-06-10 | 1988-06-10 | Method for manufacturing hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0740632B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9115000B2 (en) | 2011-04-18 | 2015-08-25 | Showa Denko K.K. | Process for producing carbonyl sulfide |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715496A (en) * | 1980-07-02 | 1982-01-26 | Sumitomo Bakelite Co | Method of producing heat dissipating insulating board |
| JPS5910080A (en) * | 1982-07-07 | 1984-01-19 | Nec Ic Microcomput Syst Ltd | Receiver for television sound multiplex broadcast |
| JPS605589A (en) * | 1983-06-23 | 1985-01-12 | 松下電器産業株式会社 | High thermal conductivity metal base printed circuit board |
| JPS6050991A (en) * | 1983-08-31 | 1985-03-22 | 昭和電工株式会社 | Electrically insulated substrate |
-
1988
- 1988-06-10 JP JP63144028A patent/JPH0740632B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9115000B2 (en) | 2011-04-18 | 2015-08-25 | Showa Denko K.K. | Process for producing carbonyl sulfide |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01312890A (en) | 1989-12-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |