JPH0743936B2 - Sense amplifier - Google Patents

Description

The present invention relates to a sense amplifier used in a dynamic MOSRAM, and more particularly to a sense amplifier for setting the precharge level of a positive / complementary bit line to about 1/2 Vcc.

[Conventional technology]

Conventionally, the sense amplifier shown in FIG. 3 has been used in the dynamic MOSRAM. This sense amplifier employs a method of precharging both the positive and complementary bit lines to the power supply voltage Vcc level by the precharge signal PDL during the precharge period. The conventional sense amplifier has a drawback that the current consumption is large because the charge / discharge voltage of the bit line is Vcc. As a method of reducing the current consumption, a method of setting the precharge level of the bit line to 1/2 Vcc level is proposed as shown in FIG. In the case of the sense amplifier shown in Fig. 4, the level of charging / discharging is 1/2 Vcc, so it is possible to reduce the current consumption of the sense amplifier to 1/2 compared to the conventional method (Vcc precharge method). is there.

[Problems to be solved by the invention]

However, in the conventional sense amplifier described above, when the high level of the word line is Vcc, even if high data is written to the memory cell, the cell capacitance of the cell is not charged to the Vcc potential, and the MOSFET in the cell operates as a source follower. since the threshold voltage V _T min reduced the potential of the FET from Vcc (Vc
c−V _T ). Therefore, the memory cell is High
The difference voltage generated on the bit line when storing the data is C _S / (C _B + C _S )) × (Vcc−V _T / 1 / 2Vcc). Become.

1 / 2Vcc (1/1 + (C _B / C _S ))-V _T × (1+ (C _B / C _S )) On the other hand, when writing Low data to the memory cell, the bit line of MOSFET in the cell is Since it becomes a source, the potential of the cell capacitance becomes zero. Therefore, the potential difference that occurs on the bit line when the memory cell is low and stores data is 1 / 2Vcc × (1/1 + (C _B / C _S )).

Here, C _{B is the} bit line capacitance C _{S is the} memory cell capacitance V _{T is the} MOSFET threshold voltage, and there is a drawback that the bit line differential voltage becomes small when the memory cell is high.

[Means for solving problems]

The sense amplifier of the present invention has a dummy capacitor, a transistor for setting the dummy capacitor to the ground voltage, and a transistor for connecting the positive complementary bit line and the dummy capacitor.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of FIG. In FIG. 1, Q _{1 to} Q ₁₁ are MOS transistors, which are connected as shown.

At time t ₁ , the sense amplifier is activated,
The positive bit line is at Vcc level and the complementary bit line is at GND level. On the other hand, the dummy capacitor C _D is the MOS transistor Q ₉ , Q ₁₁
Is on and contacts 1 and 2 are at GND level.

Next, at time t ₂ , the sense amplifier is inactive and in a precharged state, the MOS transistors Q ₈ and Q ₁₀ are turned on, and the positive complementary bit line and the dummy capacitor are connected. As a result, the precharge level of the bit line is (Here, C _B and C _D are the bit line capacitance and the dummy capacitance, respectively). Can be lower. That is, assuming that the reduced voltage is ΔV, the precharge level is 1/2 Vcc-ΔV
Becomes

〔The invention's effect〕

As described above, the present invention reduces the precharge level of the bit line by connecting the dummy bit line and the complementary bit line. Since the voltage is 1/2 Vcc-ΔV, which is lower, the voltage difference between the bit lines when the memory cell is High is (C _S / (C _B + C _D + C _S )) × (Vcc−V _T − (1 / 2Vcc−Δ V) = (1/2 Vcc + ΔV) x (C _S / (C _B + C _D + C _S ) -V _T x (C _S / C _B + C _D + C _S )) while the memory cell is low The line differential voltage is (1/2 Vcc-ΔV) x (C _S / (C _B + C _D + C _S )) Therefore, the bit line differential voltage when the memory cell is High is the same as when the memory cell is Low. The effect is that it can be equal to or larger than the voltage difference between the bit lines.

[Brief description of drawings]

1 is a sense amplifier circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the sense amplifier operation of FIG. 1, and FIG. 3 is a conventional example of a sense amplifier whose precharge level is Vcc. Figure 4 shows the precharge level Is a conventional example of the sense amplifier. _{Q 1, Q 3, Q 5} ...... P -channel MOS _{transistor, Q 2, Q 4, Q} 6 ~Q
₁₃ ... N-channel MOS transistor, C _B ... bit line capacitance, C _D ... dummy capacitance, B, ... complementary bit line, φ ₁ , φ
₂ , φ ₃ ...... Internal clock, 1,2 ...... Internal contact.

Claims (1)

[Claims] 1. A sense amplifier for connecting a positive and complementary bit line and setting a precharge level of the bit line to about 1/2 of a power supply voltage, wherein a dummy capacitor and the dummy capacitor are provided before a bit line precharge period. A sense amplifier comprising: a transistor that is set to a ground potential; and a transistor that connects the positive complementary bit line and the dummy capacitor during a bit line precharge period.