JPH0743939B2 - Superconducting circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting circuit device using a superconducting loop, and more particularly to a superconducting circuit device in which noise is reduced and operation is stabilized.

[Prior Art] Generally, SQUID (Superconducting Quantum Interferenc
A superconducting circuit device such as an e Device) or a memory cell has a circuit portion including a superconducting loop.

FIG. 7 is a block diagram showing a conventional superconducting circuit device, for example, a memory cell array using a Josephson junction element.

In the figure, (1) is a column address decoder to which a column address from a processing device (not shown) is input, (2) is a writing address decoder to which a writing address from the processing device is input, (3)
Is a read address decoder that receives the read address from the processor, and each has a 3-bit input terminal (11)
To (13), (21) to (23) and (31) to (33).

(4) is a column line driver connected to the column address decoder (1), (5) is a write line driver connected to the write address decoder (2), and (6) is a read address decoder (3) connection Read line drivers, and eight drivers (41) to (48), (51) to (58) and (61) to (68) corresponding to respective addresses "000" to "111" respectively.
It consists of The output terminals of each column line driver (4), write line driver (5) and read line driver (6) are connected to eight column lines, a write line and a read line, respectively.

(7) is a memory cell array consisting of 64 (8 × 8) superconducting loops L11 to L88 arranged in a matrix. The superconducting loops L11 to L18, L21 to L28, ..., L81 to L88 correspond to respective columns. The drivers (41) to (48) are connected to the column line. Further, the write line and the read line are magnetically coupled close to the respective superconducting loops L11 to L88.

R1 to R8 are resistors inserted between the end of each column line and the ground, and resistors similar to these (not shown) are the end of each write line and read line and the ground. It is also inserted in between. (8)
Is an output terminal for reading the data stored in the memory cell array.

FIG. 8 is a circuit diagram showing the structure of one memory cell in FIG. 7, where L is a superconducting loop, J1 is a Josephson junction (hereinafter referred to as a loop junction) inserted in a part of the superconducting rape L, (4L) is a column line for supplying an electric current to the superconducting rape L, (5L) is a writing line arranged close to the loop junction J1 side of the superconducting rape L, and (6L) is a writing line (5L). It is a read line arranged close to the superconducting loop L on the opposite side. Reference numeral 12 denotes a Josephson junction (hereinafter referred to as a reading junction) inserted in the reading line (6L) corresponding to each superconducting loop L, and is arranged so as to be close to a symmetrical position with respect to the loop junction J1.

The superconducting loop L constitutes a circuit portion, and the lines (5L) and (6L) adjacent to the loop portion constitute a wiring portion.

The configuration of each memory cell for the superconducting loops L11 to L88 in FIG. 7 is the same as that in FIG. 8, and basically, the presence or absence of a persistent current in each superconducting loop L11 to L88 is detected by the read line (6L). It is supposed to do.

Next, the operation of the conventional memory cell array shown in FIG. 7 will be described with reference to FIGS.

FIG. 8 shows a state in which "0" is written (reset) in the superconducting loop L (memory cell), and there is no persistent current. This reset state is as shown by the arrow in FIG.
It is obtained by supplying the column current i4 from the column line (4L).

That is, the normal loop junction J1 is in a superconducting (zero voltage) state, and the column current i4 flows evenly to the left and right of the superconducting loop L. Therefore, if the column current i4 is cut off, a permanent current remains in the superconducting loop L. Absent.

On the other hand, in order to store 1-bit information "1" in the memory cell, the write current i5 is supplied to the write line (5L) at the same time as the column current i4 from the reset state of FIG.

At this time, since the write line (5L) is magnetically coupled to the loop junction J1, the write current i5 changes the loop junction J1 to the resistance (voltage) state, and all the column currents i4 are
As shown in FIG. 10, the current flows in the superconducting loop L in the direction without the loop junction J1.

Here, when the column current i4 and the write current i5 are cut off, the loop junction J1 is restored to the superconducting state, so that the persistent current ie continues to circulate in the superconducting loop L as shown in FIG. 11, and the memory cell is "1". Is written in the information storage state.

For example, in FIG. 7, when the column address “011” and the writing address “100” are selected and the column current i4 and the writing current i5 are supplied from the drivers (44) and (55), respectively, the persistent current ie to the superconducting rape L45 is shown. Remains and the information of "1" is written.

Thus, as shown in FIG. 8 or 11, information “0” or “1” is written in each memory cell depending on the presence / absence of the permanent current ie.

To read these “0” or “1” information, the column current
The reading current i6 may be supplied to the reading line (6L) at the same time as i4. The column current i4 at the time of reading is set to a current value that does not reset the permanent current ie in the superconducting loop L.

If there is a persistent current ie in the superconducting loop L as shown in FIG. 11, the column current i4 all flows to the side of the superconducting loop L without the loop junction J1 as shown in FIG. The read junction J2, which is magnetically coupled with, transitions to a voltage state. Therefore, the read current i6 cannot flow through the read line (6L) but flows through the output terminal (8) (illustrated in FIG. 12 for convenience).

For example, in FIG. 7, each driver (44) and (65)
When the memory cell corresponding to the superconducting loop L45 is selected by activating, the read current i6 cannot flow through the vicinity of the superconducting loop L45, so that the information of “1” is read from the output terminal (8). To be

On the other hand, for the superconducting loop L where the permanent current ie does not exist as shown in FIG. 8, the column current i4 is shunted to the left and right as shown in FIG. 13, so that the read junction J2 maintains the zero voltage state. Therefore, the read current i6 all flows through the read line (6L), and the output signal from the output terminal (8) cannot be obtained.
Information is read.

[Problems to be Solved by the Invention] As described above, in the conventional superconducting circuit device, one superconducting loop L constitutes a memory cell (circuit portion). Therefore, a wiring portion magnetically coupled to the circuit portion or When a magnetic field is generated by a current flowing in another superconducting loop, the permanent current ie or the like flowing in the superconducting loop L changes, and in the case of the memory cell array (7), there is a problem that the stored information is destroyed or a read operation error occurs. there were.

On the contrary, a similar magnetic field noise is given to a nearby circuit portion due to the current flowing through the circuit portion, so that the circuit portions cannot be brought close to each other and the integration degree cannot be increased. there were.

Further, as shown in FIG. 14 (a), the direction of the magnetic field HL generated by the permanent current ie in the superconducting loop L is mainly perpendicular to the plane of the superconducting loop L as shown in FIG. 14 (b). Therefore, there is a problem that the structure and material of the magnetic head for detecting the presence of the permanent current ie and reading the recorded information become expensive.

The present invention has been made to solve the above problems, and it is an object of the present invention to eliminate the influence of an external magnetic field, obtain a superconducting circuit device which is stable in operation, highly reliable and highly integrated, and inexpensive. To aim.

[Means for Solving the Problems] In the superconducting circuit device according to the present invention, the circuit portion is formed by a pair of loops whose rotation directions are opposite to each other.

[Operation] In the present invention, the magnetic field coupling noise between the circuit portion and the defeat portion is canceled by the pair of loops.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings by taking as an example the case where the superconducting circuit device is a memory cell array as described above. FIG. 1 is a circuit diagram showing one memory cell of one embodiment of the present invention, and (6L) is a read line or wiring portion similar to the above. Although only a typical reading line (6L) is shown here, a writing line (5L) that constitutes a wiring portion together with the reading line (6L)
Similarly (see FIGS. 8 to 13) are similarly arranged.

LA is a superconducting loop, that is, a circuit portion corresponding to the above-mentioned superconducting loop L (see FIGS. 8 to 14), and a pair of continuous loops L1 and L2 in which the rotating directions of the currents are opposite to each other and the areas in the loops are equal. And has a symmetrical 8 shape including a grade intersection (9) in the center.

H1 and H2 are magnetic fields generated on the read line (6L) by the permanent current ie flowing in the loops L1 and L2, and H6 is a magnetic field generated by the read current i6 flowing in the read line (6L).

Actually, the superconducting loop LA has the loop junctions J11 and J12 as many as necessary, or the loop junctions J11 and J12, as shown in FIG. 2 or 3.
Includes J12.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described.

Now, with the permanent current ie flowing in the superconducting loop LA, the read current i6 is applied to the wiring, for example, the read line (6L).
Flows in the direction of the arrow. Now, let us consider the magnetic field coupling noise that the read line (6L) and the superconducting loop LA give to each other.

First, the magnetic field H6 generated by the read current i6 is
The components interlinking with L1 and L2 are perpendicular to the drawing and are directed from the lower side to the upper side, and since the areas of the loops L1 and L2 are equal to each other, the magnetic flux amounts generated by the magnetic field H6 are equal to each other. At this time, since the rotation directions of the loops L1 and L2 are opposite to each other, the influence of the magnetic field H6 by the read current i6 is completely canceled as the entire superconducting loop LA. Therefore, the magnetic field coupling noise given to the superconducting loop LA by the read current i6 is zero.

On the other hand, the components in which the magnetic fields H1 and H2 generated by the permanent current ie in the superconducting loop LA cross the read line (6L) are:
Each is perpendicular to the drawing and opposite to each other. Therefore, as in the above, the reading line (6L) as a whole is offset and becomes zero. Strictly speaking, the reading line (6
Components of magnetic fields H1 and H2 are generated in the direction parallel to L),
It is clear that this will also be offset.

Thus, superconducting loop LA and read line (6L)
The magnetic field coupling noise components that give each other are canceled out.

Even if the loop junctions J11 and J12 are provided as shown in FIG. 2 or FIG. 3, the direction of the current flowing across them is perpendicular to the drawing, so that each loop junction J11 and J12 is
The characteristics of are not affected by the magnetic fields H6, H1 and H2 perpendicular to the drawing. Therefore, the magnetic field coupling noise received by the loop junctions J11 and J12 from the reading line (6L) becomes zero, the circuit operation is very stable, and the reading line (6L)
Since the distance between and can be reduced, the degree of integration is increased.

If a plurality of superconducting loops LA of FIG. 1 are arranged in a matrix and configured as shown in FIG. 7, since there is no magnetic field coupling noise between the superconducting loops LA, they can be arranged close to each other. High degree of integration. Further, as shown in FIG. 4, the conventional superconducting loop L, ...
Even if they are arranged alternately adjacent to LA, ..., Magnetic field coupling noises cancel each other out, so that the degree of integration can be similarly increased.

Further, the magnetic field H12 generated by the permanent current ie flowing through the superconducting loop LA in FIG. 1 is mainly a magnetic field component in the surface direction of the superconducting loop LA, as shown in FIGS. 5 (a) and 5 (b). Generally, when a magnetic head reads information recorded by a permanent current ie, it is extremely easy to detect a magnetic field parallel to the recording surface as compared with a case where a perpendicular magnetic field is detected. Therefore, the structure of the read magnetic head is simplified, and the cost of the memory cell array can be reduced.

In the above embodiment, the case where the circuit portion is the figure 8 superconducting loop LA including the grade intersection (9) has been described as an example, but as shown in FIG.
It may be a superconducting loop LB composed of L1 and L2.

In this case, the loops L1 and L2 are formed in different wiring layers, and the read line (6L) adjacent to the superconducting loop LB is formed in the same wiring layer as either loop L1 or L2. .

Even if the superconducting loop LB is formed as shown in Fig. 6, each loop
Due to the permanent current ie in L1 and L2, the magnetic fields H1 and H2 linked to the read line (6L) are in opposite directions, and the read current i6 causes the magnetic field H6 linked to the superconducting loop LB.
However, since the rotation directions of the loops L1 and L2 are opposite to each other, the magnetic field coupling noises between the superconducting loop LB and the read line (6L) are canceled and become zero.

Also, the case where the wiring portion adjacent to the superconducting loop LA is the reading line (6L) has been described as an example, but the same applies to other wiring, for example, the writing line (5L) (see FIGS. 8 to 13). Produce an effect.

Further, although the case where the superconducting circuit device is a memory cell array has been described, the same effect can be obtained even when applied to a SQUID including a superconducting loop.

Furthermore, the superconducting loop LA or LB shown in FIGS.
It is needless to say that not only the above structure, but also two or more wiring layers are used to interconnect the loop pairs whose rotation directions are opposite to each other, and the same effect can be obtained.

As described above, according to the present invention, the circuit portion is formed by a pair of loops whose rotation directions are opposite to each other, and the magnetic field coupling noise between the circuit portion and the wiring portion is canceled by the pair of loops. Therefore, there is an effect that a superconducting circuit device having stable operation, high reliability, high integration degree, and low cost can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing loop junctions provided in the superconducting loop of FIG. 1, and FIG. 4 is a superconducting loop of FIG. A circuit diagram showing a part of a memory cell array configured by using
1 (a) and 1 (b) are a plan view and a side view showing a magnetic field generated by the superconducting loop of FIG. 1, FIG. 6 is a perspective view showing another embodiment of the present invention, and FIG. FIG. 8 is a block diagram showing a memory cell array as a circuit device.
FIG. 13 is a circuit diagram showing different operating states of the memory cell in FIG. 7, and FIGS. 14 (a) and 14 (b) are a plan view and a side view showing a magnetic field generated by a conventional superconducting loop. (5L) …… writing line, (6L) …… reading line LI, L2 …… pair of loops, H1, H2, H6 …… magnetic field (9) …… overpass LA …… 8 figure-shaped superconducting loop LB ...... Superconducting loops arranged in a stacked manner Incidentally, in the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (5)

[Claims] 1. A superconducting circuit device comprising a circuit portion composed of a superconducting loop and a wiring portion arranged in proximity to the circuit portion, wherein the circuit portion comprises a pair of loops in which currents rotate in opposite directions. And a magnetic field coupling noise between the circuit portion and the wiring portion is cancelled. 2. The superconducting circuit device according to claim 1, wherein the circuit portion is formed by an 8-shaped loop including a grade intersection. 3. The superconducting circuit device according to claim 1, wherein the circuit portion is formed by a double loop which is formed in different wiring layers and is arranged in an overlapping manner. 4. The superconducting circuit device according to claim 1, wherein the circuit portion constitutes a memory cell. 5. The superconducting circuit device according to any one of claims 1 to 3, wherein the circuit portion constitutes a SQUID.