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JPH0744161B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0744161B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0744161B2
JPH0744161B2 JP1007256A JP725689A JPH0744161B2 JP H0744161 B2 JPH0744161 B2 JP H0744161B2 JP 1007256 A JP1007256 A JP 1007256A JP 725689 A JP725689 A JP 725689A JP H0744161 B2 JPH0744161 B2 JP H0744161B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
metal material
thin film
material thin
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1007256A
Other languages
Japanese (ja)
Other versions
JPH02187021A (en
Inventor
治 山▲崎▼
伸 清水
克典 三橋
弘亥 大竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1007256A priority Critical patent/JPH0744161B2/en
Publication of JPH02187021A publication Critical patent/JPH02187021A/en
Publication of JPH0744161B2 publication Critical patent/JPH0744161B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 <産業上の利用分野> この発明は、高融点金属材料薄膜を半導体基板上に選択
的に形成するようにした半導体装置の製造方法に関す
る。
TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which a high melting point metal material thin film is selectively formed on a semiconductor substrate.

<従来の技術> 半導体装置における半導体基板と配線材料との間の電気
的接続を得るためには、従来は、配線材料と半導体基板
との間で直接電気的接触を形成するようにしていた。第
3図はこのような方法を用いて製造されたMOSトランジ
スタの断面図である。この第3図において、31は半導体
基板、32はソース部、33はドレイン部、34はゲート部、
35はLOCOS酸化膜、36はフィールド酸化膜(絶緑膜)、3
7はアルミニウムあるいはその合金等の配線材料であ
る。このMOSトランジスタは、ソース部32およびドレイ
ン部33の絶緑膜開孔部38において、配線材料37とソース
部32およびドレイン部33との間で直接電気的接触を形成
している。
<Prior Art> In order to obtain an electrical connection between a semiconductor substrate and a wiring material in a semiconductor device, conventionally, a direct electrical contact was formed between the wiring material and the semiconductor substrate. FIG. 3 is a sectional view of a MOS transistor manufactured by using such a method. In FIG. 3, 31 is a semiconductor substrate, 32 is a source part, 33 is a drain part, 34 is a gate part,
35 is a LOCOS oxide film, 36 is a field oxide film (insulating film), 3
7 is a wiring material such as aluminum or its alloy. In this MOS transistor, a direct electrical contact is formed between the wiring material 37 and the source portion 32 and the drain portion 33 in the insulative film opening portion 38 of the source portion 32 and the drain portion 33.

<発明が解決しようとする課題> しかしながら、上記従来の方法では、段差被覆性が悪
く、素子の微細化に伴い、フォトリソグラフィー工程で
のアライメントマージンが少ないことや、アスペクト比
の増大に伴う配線の信頼性低下などが問題となってい
た。
<Problems to be Solved by the Invention> However, in the above-mentioned conventional method, the step coverage is poor, the alignment margin in the photolithography process is small with the miniaturization of the element, and the wiring with the increase in the aspect ratio is formed. There was a problem of reduced reliability.

そこで、最近になって、微細コンタクト部にコンタクト
プラグとしての高融点金属材料薄膜を形成するコンタク
トプラグ技術を用いて、上記のような絶縁膜開孔部(コ
ンタクト開孔部)の基板上に上記高融点金属材料薄膜を
形成し、その上に配線材料を形成するような方法がとら
れるようになった。
Therefore, recently, by using a contact plug technique for forming a high melting point metal material thin film as a contact plug on a fine contact portion, the above-mentioned insulating film opening portion (contact opening portion) is formed on the substrate. A method has been adopted in which a high melting point metal material thin film is formed and a wiring material is formed thereon.

ところで、これまでのコンタクトプラグ技術において
は、コンタクト開孔部を形成するための絶縁膜のドライ
エッチング後に、基板材料のエッチングによるダメージ
層の除去のためのプラズマエッチングおよびコンタクト
開孔部の自然酸化膜除去のための湿式洗浄を行い、その
後、そのコンタクト開孔部の基板上に高融点金属材料薄
膜を形成するようにしていた。しかしながら、この方法
では、上記金属材料薄膜の形成工程とそれ以前の工程と
の間で大気にさらされるため、また枚様式で高融点金属
材料薄膜を形成するために処理されるまでの経過時間の
違いなどにより、金属材料薄膜形成直前の半導体基板の
コンタクト開孔部の表面状態の再現性を得ることが困難
であり、そのために半導体基板表面と高融点金属材料薄
膜との界面の状態に良好な再現性が得られず、電気的接
触抵抗にばらつきを生じるとか、電気的接触抵抗が大き
くなるといった欠点があった。また、上記エッチングに
は四弗化炭素(CF4)ガスや三弗化窒素(NF3)ガスが一
般に用いられるが、基板に対するダメージが大きいこと
から、ダメージの少ない六弗化硫黄(SF6)ガスが用い
られる傾向にある。しかしながら、SF6ガス単体中では
低印加電圧での放電が起こりにくいため安定したエッチ
ングができず、膜はがれの発生といった構造上の不安定
さが生じたり、また、この種のエッチングは絶縁膜開孔
のためのエッチングに引き続いて行なわれるため、高融
点金属材料薄膜の形成までに装置間の移動で大気にさら
されたり、高融点金属材料薄膜形成までに時間がかかる
ことなどから、絶縁膜開孔部の汚染を回避できないとい
う欠点があった。
By the way, in the conventional contact plug technology, after the dry etching of the insulating film for forming the contact opening, the plasma etching for removing the damaged layer by the etching of the substrate material and the natural oxide film of the contact opening are formed. Wet cleaning for removal was performed, and then a high-melting-point metal material thin film was formed on the substrate in the contact opening portion. However, in this method, since the exposure is performed to the atmosphere between the step of forming the metal material thin film and the step before that, the elapsed time until the processing is performed to form the refractory metal material thin film in a single plate method Due to the difference, it is difficult to obtain the reproducibility of the surface condition of the contact opening portion of the semiconductor substrate immediately before the metal material thin film is formed. Therefore, the condition of the interface between the semiconductor substrate surface and the refractory metal material thin film is favorable. There are drawbacks such that reproducibility cannot be obtained, the electric contact resistance varies, and the electric contact resistance increases. In addition, carbon tetrafluoride (CF 4 ) gas or nitrogen trifluoride (NF 3 ) gas is generally used for the above etching, but since it damages the substrate, sulfur hexafluoride (SF 6 ) is less likely to be damaged. Gas tends to be used. However, since discharge at a low applied voltage is unlikely to occur in the SF 6 gas alone, stable etching cannot be performed, and structural instability such as film peeling occurs. Since it is performed after etching for the holes, the insulating film is not opened because it may be exposed to the atmosphere due to movement between the equipment before forming the high melting point metal material thin film, and it may take time to form the high melting point metal material thin film. There is a drawback that contamination of the holes cannot be avoided.

そこで、この発明の目的は、高融点金属材料薄膜と半導
体基板との電気的接触抵抗を小さくすることができ、ま
た、高融点金属材料薄膜の膜はがれを生じることのない
半導体装置の製造方法を提供することにある。
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device which can reduce the electrical contact resistance between a high melting point metal material thin film and a semiconductor substrate, and which does not cause film peeling of the high melting point metal material thin film. To provide.

<課題を解決するための手段> 上記目的を達成するため、この発明の半導体装置の製造
方法は、絶縁膜で被覆された半導体基板の表面をエッチ
ングにより部分的に露出させ、自然酸化膜を除去した
後、この半導体基板の表面の露出部分のみに高融点金属
材料薄膜を選択的に形成するようにした半導体装置の製
造方法において、上記高融点金属材料薄膜を形成する反
応室と同一反応室内において、上記半導体基板の温度を
室温乃至80℃に保持し、上記半導体基板の表面の露出部
分に上記エッチングにより生じたダメージ層を、六弗化
硫黄ガスに不活性ガスを添加した混合ガスを用いてエッ
チングして除去し、続いて、上記半導体基板を大気にさ
らすことなく上記半導体基板の表面の露出部分に上記高
融点金属材料薄膜を形成することを特徴としている。
<Means for Solving the Problems> In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is configured to partially expose a surface of a semiconductor substrate covered with an insulating film by etching and remove a natural oxide film. After that, in a method for manufacturing a semiconductor device in which a high-melting-point metal material thin film is selectively formed only on the exposed portion of the surface of the semiconductor substrate, in the same reaction chamber as the reaction chamber in which the high-melting-point metal material thin film is formed. The temperature of the semiconductor substrate is kept at room temperature to 80 ° C., the damaged layer formed on the exposed portion of the surface of the semiconductor substrate by the etching, using a mixed gas obtained by adding an inert gas to sulfur hexafluoride gas. It is characterized in that the refractory metal material thin film is formed on the exposed portion of the surface of the semiconductor substrate without exposing the semiconductor substrate to the air, by etching. There.

なお、室温とは、半導体製造工場で通常設定される25℃
±2℃の温度を意味する。
It should be noted that the room temperature is 25 ° C which is usually set in a semiconductor manufacturing factory.
It means a temperature of ± 2 ° C.

<作用> 自然酸化膜を除去した後、半導体基板の表面の露出部分
に生じたダメージ層を、六弗化硫黄ガスに不活性ガスを
添加した混合ガスを用いてエッチングして除去している
ので、六弗化硫黄ガスのみを用いる場合に比して六弗化
硫黄ガスの分圧が下がり、放電が起きやすくかつ均一に
なって安定したエッチングがおこなわれる。また、この
エッチングの際に、半導体基板の温度を室温乃至80℃に
保持しているので、エッチングレートが比較的低く抑え
られ、ダメージ層が精度良く除去される。
<Operation> Since the natural oxide film is removed, the damaged layer formed on the exposed portion of the surface of the semiconductor substrate is removed by etching using a mixed gas of sulfur hexafluoride gas and an inert gas. As compared with the case where only sulfur hexafluoride gas is used, the partial pressure of sulfur hexafluoride gas is lowered, discharge is more likely to occur and uniform, and stable etching is performed. Further, since the temperature of the semiconductor substrate is kept at room temperature to 80 ° C. during this etching, the etching rate can be suppressed to a relatively low level and the damaged layer can be removed with high accuracy.

続いて、同一反応室内において、上記半導体基板を大気
にさらすことなく上記半導体基板の表面の露出部分に上
記高融点金属材料薄膜を形成しているので、ダメージ層
除去及び高融点金属材料薄膜の形成が各処理基板ごとに
連続して行なわれる。したがって、各処理基板ごとの成
膜状態のばらつきが少なくなり、この結果、高融点金属
材料薄膜の膜はかれが生じなくなる。また、上記ダメー
ジ層を除去した直後に高融点金属材料薄膜が形成される
ので、電気的接触抵抗が少なくなる。
Subsequently, since the high melting point metal material thin film is formed in the exposed portion of the surface of the semiconductor substrate in the same reaction chamber without exposing the semiconductor substrate to the atmosphere, the damage layer is removed and the high melting point metal material thin film is formed. Is continuously performed for each processing substrate. Therefore, the variation in the film formation state among the respective processed substrates is reduced, and as a result, the refractory metal material thin film is not removed. Further, since the refractory metal material thin film is formed immediately after removing the damaged layer, the electrical contact resistance is reduced.

<実施例> 以下、この発明を図示の実施例により詳細に説明する。<Example> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

第1図はこの発明の一実施例の半導体装置の製造方法を
説明するための工程断面図である。
FIG. 1 is a process sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

第1図(a)に示すように、まず、半導体基板1のコン
タクト部の絶縁膜2をエッチングし、0.8μm角以下の
コンタクト開孔部5を作る。そして、このコンタクト開
孔部5における半導体基板表面にできた自然酸化膜3を
湿式洗浄(エッチングを含む)により除去すると第1図
(b)の状態となる。このとき、半導体基板1の表面の
露出部分にはエッチングによるダメージ層が生じてい
る。次に、第1図(c)に示すように、コンタクト開孔
部5に高融点金属材料薄膜を選択的に形成する反応室と
同一反応室内において、SF6ガスと不活性ガス(例え
ば、ヘリウムガス)との混合ガスによりコンタクト開孔
部5の半導体基板を表面から50Å〜300Å程度(図中4
で示す部分)エッチングして上記ダメージ層を除去す
る。エッチング時の基板温度は室温付近から80℃位まで
が適切であった。引き続いて同一反応室内において、第
1図(d)に示すように、高融点金属材料薄膜6をコン
タクト開孔部5の基板表面上のみに選択的に、絶縁膜2
の厚さに相当する厚さまで形成する。
As shown in FIG. 1A, first, the insulating film 2 on the contact portion of the semiconductor substrate 1 is etched to form a contact opening portion 5 of 0.8 μm square or less. Then, when the natural oxide film 3 formed on the surface of the semiconductor substrate in the contact opening 5 is removed by wet cleaning (including etching), the state shown in FIG. 1B is obtained. At this time, a damaged layer due to etching is formed in the exposed portion of the surface of the semiconductor substrate 1. Next, as shown in FIG. 1 (c), SF 6 gas and an inert gas (for example, helium) are placed in the same reaction chamber as the reaction chamber in which the high melting point metal material thin film is selectively formed in the contact openings 5. The mixed gas with the gas causes the semiconductor substrate of the contact opening 5 to be about 50Å to 300Å from the surface (4 in the figure).
The portion shown by) is etched to remove the damaged layer. The suitable substrate temperature during etching was from room temperature to around 80 ° C. Subsequently, in the same reaction chamber, as shown in FIG. 1D, the refractory metal material thin film 6 is selectively formed only on the substrate surface of the contact opening portion 5, and the insulating film 2 is formed.
To a thickness corresponding to the thickness of.

このようにして形成された高融点金属材料薄膜は、膜は
がれが発生せず、また、電気的接触抵抗値は従来の方法
で形成されたものに比べ約1/2〜1/5に低減することが確
認されている。
The high melting point metal material thin film thus formed does not cause film peeling, and the electrical contact resistance value is reduced to about 1/2 to 1/5 as compared with that formed by the conventional method. It has been confirmed.

第2図は本実施例の製造方法を適用したMOS−FETの断面
図である。ここで、21は半導体基板、22はソース部、23
はドレイン部、24はゲート部、25はLOCOS酸化膜、26は
フィールド酸化膜(絶縁膜)、27はアルミニウムあるい
はその合金等の配線材料、28はコンタクトプラグとして
の高融点金属材料薄膜である。このMOS−FETは通常のMO
S製造プロセスにおいて、第1図で説明したように、ソ
ース部22やドレイン部23上の絶縁膜26をエッチングして
コンタクト開孔部29を形成し、この開孔部29のみに選択
的に高融点金属材料薄膜28を絶縁膜26の厚さに相当する
厚さに形成する。その後、配線材料27を形成し、上記高
融点金属材料薄膜27を介してこの配線材料27とソース部
22およびドレイン部23との電気的接続を得るようにして
いる。
FIG. 2 is a sectional view of a MOS-FET to which the manufacturing method of this embodiment is applied. Here, 21 is a semiconductor substrate, 22 is a source part, and 23
Is a drain part, 24 is a gate part, 25 is a LOCOS oxide film, 26 is a field oxide film (insulating film), 27 is a wiring material such as aluminum or its alloy, and 28 is a refractory metal material thin film as a contact plug. This MOS-FET is a normal MO
In the S manufacturing process, as described with reference to FIG. 1, the insulating film 26 on the source part 22 and the drain part 23 is etched to form the contact opening 29, and only the opening 29 is selectively elevated. The melting point metal material thin film 28 is formed to a thickness corresponding to the thickness of the insulating film 26. After that, a wiring material 27 is formed, and the wiring material 27 and the source part are formed through the high melting point metal material thin film 27.
22 and the drain portion 23 are electrically connected.

このように、電気的接触抵抗が小さく、安定した構造の
コンタクトプラグを形成して、配線材料と基板との間の
電気的接続を得るようにしているので、第3図の従来例
におけるような素子の微細化に伴う配線の信頼性低下な
どの問題がなく、素子の信頼性が向上すると共に、高集
積化が容易に図れ、高機能デバイスの実現が可能とな
る。
As described above, since the contact plug having a small electric contact resistance and a stable structure is formed so as to obtain the electric connection between the wiring material and the substrate, as in the conventional example of FIG. There is no problem such as reduction in reliability of wiring due to miniaturization of the element, the reliability of the element is improved, high integration can be easily achieved, and a highly functional device can be realized.

<発明の効果> 以上より明らかなように、この発明の半導体装置の製造
方法は、自然酸化膜を除去した後、半導体基板の表面の
露出部分に生じたダメージ層を、六弗化硫黄ガスに不活
性ガスを添加した混合ガスを用いてエッチングして除去
しているので、六弗化硫黄ガスのみを用いる場合に比し
て六弗化硫黄ガスの分圧が下がり、放電が起きやすくか
つ均一になって安定したエッチングをおこなうことがで
きる。また、このエッチングの際に、半導体基板の温度
を室温乃至80℃に保持しているので、エッチングレート
を比較的低く抑えることができ、ダメージ層を精度良く
除去することができる。また、同一反応室内において、
上記半導体基板を大気にさらすことなく上記半導体基板
の表面の露出部分に上記高融点金属材料薄膜を形成して
いるので、ダメージ層除去及び高融点金属材料薄膜の形
成が各処理基板ごとに連続して行なわれる。したがっ
て、各処理基板ごとの成膜状態のばらつきが少なくな
り、この結果、高融点金属材料薄膜の膜はがれが生じな
くなる。また、上記ダメージ層を除去した直後に高融点
金属材料薄膜が形成されるので、電気的接触抵抗が小さ
くなる。従って、素子の信頼性の向上、高集積化が図
れ、高機能デバイスの実現が可能となる。
<Effects of the Invention> As is apparent from the above, according to the method of manufacturing a semiconductor device of the present invention, after removing the natural oxide film, the damage layer generated on the exposed portion of the surface of the semiconductor substrate is changed to sulfur hexafluoride gas. Since it is removed by etching using a mixed gas with an inert gas added, the partial pressure of sulfur hexafluoride gas is lower than that when only sulfur hexafluoride gas is used, and discharge is more likely and uniform. Therefore, stable etching can be performed. In addition, since the temperature of the semiconductor substrate is kept at room temperature to 80 ° C. during this etching, the etching rate can be kept relatively low and the damaged layer can be removed with high accuracy. In the same reaction chamber,
Since the refractory metal material thin film is formed on the exposed portion of the surface of the semiconductor substrate without exposing the semiconductor substrate to the atmosphere, the removal of the damaged layer and the formation of the refractory metal material thin film are continuously performed for each processing substrate. Will be performed. Therefore, variations in the film formation state among the respective processed substrates are reduced, and as a result, film peeling of the refractory metal material thin film does not occur. Further, since the refractory metal material thin film is formed immediately after removing the damaged layer, the electrical contact resistance is reduced. Therefore, the reliability of the element can be improved, the integration can be increased, and a highly functional device can be realized.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例の半導体装置の製造方法を
説明するための工程断面図、第2図は上記製造方法を用
いて作製したMOS−FETの断面図、第3図は従来の製造方
法を用いて作製したMOS−FETの断面図である。 1……半導体基板、 2……フィールド酸化膜(絶縁膜)、 3……自然酸化膜、4……エッチングされた部分、5…
…コンタクト開孔部、 6……高融点金属材料薄膜。
FIG. 1 is a process sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a MOS-FET manufactured by the above manufacturing method, and FIG. It is sectional drawing of MOS-FET produced using the manufacturing method. 1 ... Semiconductor substrate, 2 ... Field oxide film (insulating film), 3 ... Natural oxide film, 4 ... Etched portion, 5 ...
… Contact hole, 6 …… High melting point metal material thin film.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大竹 弘亥 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (56)参考文献 特開 昭62−291918(JP,A) 特開 昭63−41014(JP,A) 特開 昭63−125681(JP,A) 特開 昭62−11227(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyasu Otake 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (56) Reference JP-A-62-291918 (JP, A) JP-A-SHO 63-41014 (JP, A) JP-A-63-125681 (JP, A) JP-A-62-11227 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶緑膜で被覆された半導体基板の表面をエ
ッチングにより部分的に露出させ、自然酸化膜を除去し
た後、この半導体基板の表面の露出部分上のみに高融点
金属材料薄膜を選択的に形成するようにした半導体装置
の製造方法において、上記高融点金属材料薄膜を形成す
る反応室と同一反応室内において、上記半導体基板の温
度を室温乃至80℃に保持し、上記半導体基板の表面の露
出部分に上記エッチングにより生じたダメージ層を、六
弗化硫黄ガスに不活性ガスを添加した混合ガスを用いて
エッチングして除去し、続いて、上記半導体基板を大気
にさらすことなく上記半導体基板の表面の露出部分上に
上記高融点金属材料薄膜を形成することを特徴とする半
導体装置の製造方法。
1. A surface of a semiconductor substrate covered with an insulative film is partially exposed by etching to remove a natural oxide film, and then a high melting point metal material thin film is formed only on the exposed portion of the surface of the semiconductor substrate. In the method for manufacturing a semiconductor device that is selectively formed, the temperature of the semiconductor substrate is maintained at room temperature to 80 ° C. in the same reaction chamber as the reaction chamber in which the refractory metal material thin film is formed, The damaged layer formed on the exposed portion of the surface by the etching is removed by etching using a mixed gas of sulfur hexafluoride gas and an inert gas, and then the semiconductor substrate is exposed without exposing the semiconductor substrate to the atmosphere. A method of manufacturing a semiconductor device, comprising: forming the high melting point metal material thin film on an exposed portion of a surface of a semiconductor substrate.
JP1007256A 1989-01-13 1989-01-13 Method for manufacturing semiconductor device Expired - Fee Related JPH0744161B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1007256A JPH0744161B2 (en) 1989-01-13 1989-01-13 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1007256A JPH0744161B2 (en) 1989-01-13 1989-01-13 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02187021A JPH02187021A (en) 1990-07-23
JPH0744161B2 true JPH0744161B2 (en) 1995-05-15

Family

ID=11660949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1007256A Expired - Fee Related JPH0744161B2 (en) 1989-01-13 1989-01-13 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0744161B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291918A (en) * 1986-06-12 1987-12-18 Matsushita Electric Ind Co Ltd Selective deposition of metal
JPS6341014A (en) * 1986-08-06 1988-02-22 Sanyo Electric Co Ltd Epitaxial growth method
JPS63125681A (en) * 1986-11-12 1988-05-28 Matsushita Electric Ind Co Ltd Thin film forming device

Also Published As

Publication number Publication date
JPH02187021A (en) 1990-07-23

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