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JPH0744213B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0744213B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0744213B2
JPH0744213B2 JP3945587A JP3945587A JPH0744213B2 JP H0744213 B2 JPH0744213 B2 JP H0744213B2 JP 3945587 A JP3945587 A JP 3945587A JP 3945587 A JP3945587 A JP 3945587A JP H0744213 B2 JPH0744213 B2 JP H0744213B2
Authority
JP
Japan
Prior art keywords
oxide film
groove
silicon oxide
film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3945587A
Other languages
Japanese (ja)
Other versions
JPS63205927A (en
Inventor
裕幸 岡田
義晴 日高
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP3945587A priority Critical patent/JPH0744213B2/en
Publication of JPS63205927A publication Critical patent/JPS63205927A/en
Publication of JPH0744213B2 publication Critical patent/JPH0744213B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、とりわけ、トレンチキ
ャパシタなどのように、半導体基板内に溝領域を有する
半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device such as a trench capacitor having a groove region in a semiconductor substrate.

従来の技術 従来、半導体基板の表面部にトレンチキャパシタを形成
する場合、同基板に溝をエッチング形成する際に、CVD
法によって形成されたシリコン酸化膜をマスクとして用
いることが一般的である。しかし、溝エッチング終了後
に、マスクとして用いたシリコン酸化膜を除去する必要
があり、その際、弗酸溶液を用いるため、前工程で形成
した素子分離領域のLOCOS酸化膜までエッチングされ
て、膜厚と分離幅が減少して、素子分離特性が劣化す
る。この対策として、CVDシリコン酸化膜の下層にシリ
コン窒化膜を形成して、弗酸溶液によるエッチング時の
LOCOS酸化膜の保護膜とすることが提案されている。こ
の溝形成の方法について第2図(a)〜(d)に示す工
程順断面図により説明する。第2図(a)に示す様に、
LOCOS酸化膜1を形成した基板2に、10nmないし、70nm
の薄いシリコン酸化膜3を保護膜として形成した後、シ
リコン窒化膜4を20nmないし、100nmの厚さにCVD法によ
り、形成し、その後、溝エッチングのマスク用として、
CVD法によりシリコン酸化膜5を形成し、フォトエッチ
ング法を用いて、CVDシリコン酸化膜5、シリコン窒化
膜4、薄いシリコン酸化膜3を選択エッチングし、溝エ
ッチングの開口部6を形成した後、フォトエッチング用
のレジストを除去する。第2図(b)で、CVDシリコン
酸化膜5をマスクとしてシリコン基板2を選択エッチン
グし、溝形成を行う。
2. Description of the Related Art Conventionally, when forming a trench capacitor on the surface of a semiconductor substrate, CVD is used when forming a groove on the substrate by etching.
It is common to use a silicon oxide film formed by the method as a mask. However, after the trench etching is completed, it is necessary to remove the silicon oxide film used as the mask. At that time, since the hydrofluoric acid solution is used, the LOCOS oxide film in the element isolation region formed in the previous step is also etched, and the film thickness is reduced. The isolation width is reduced, and the element isolation characteristics are deteriorated. As a countermeasure against this, a silicon nitride film is formed under the CVD silicon oxide film, which is used when etching with hydrofluoric acid solution.
It has been proposed to use it as a protective film for the LOCOS oxide film. A method of forming the groove will be described with reference to process step sectional views shown in FIGS. As shown in FIG. 2 (a),
Substrate 2 on which LOCOS oxide film 1 is formed is 10 nm to 70 nm
After forming the thin silicon oxide film 3 as a protective film, the silicon nitride film 4 is formed to a thickness of 20 nm to 100 nm by the CVD method, and then used as a mask for groove etching.
After the silicon oxide film 5 is formed by the CVD method, the CVD silicon oxide film 5, the silicon nitride film 4, and the thin silicon oxide film 3 are selectively etched by the photoetching method to form the opening 6 for groove etching. The resist for photo etching is removed. In FIG. 2B, the silicon substrate 2 is selectively etched using the CVD silicon oxide film 5 as a mask to form a groove.

第2図(c)でエッチングマスクとして用いたCVDシリ
コン酸化膜を弗酸溶液でエッチングして除去する。その
際、シリコン窒化膜4の下部の薄いシリコン酸化膜3
は、その溝に面した端部から弗酸溶液が浸透し、LOCOS
酸化膜1の一部にまで及んで、エッチングされる。次
に、シリコン窒化膜4を除去するために、シリコン基板
2の露出部を10nmないし100nmの厚さで熱酸化して、リ
ン酸から同シリコン基板2を保護するための薄いシリコ
ン酸化膜8を形成し、次に、150℃程度をリン酸中で、
シリコン窒化膜を除去して、第2図(d)に示す形状を
得て、溝形成の工程を終える。
The CVD silicon oxide film used as the etching mask in FIG. 2C is removed by etching with a hydrofluoric acid solution. At this time, the thin silicon oxide film 3 below the silicon nitride film 4
Fluoric acid solution permeates from the end facing the groove, and LOCOS
The oxide film 1 is etched up to a part thereof. Next, in order to remove the silicon nitride film 4, the exposed portion of the silicon substrate 2 is thermally oxidized to a thickness of 10 nm to 100 nm to form a thin silicon oxide film 8 for protecting the silicon substrate 2 from phosphoric acid. And then in phosphoric acid at about 150 ° C
The silicon nitride film is removed to obtain the shape shown in FIG. 2 (d), and the groove forming process is completed.

発明が解決しようとする問題点 しかしながら、上述のような工程では、第2図(c)に
示すように、LOCOS酸化膜1と、溝との距離が1μm以
下になった場合、弗酸溶液によるCVDシリコン酸化膜5
のエッチング中に、溝に面した端部からシリコン酸化膜
3もエッチングされてLOCOS酸化膜1の一部まで進み、
素子分離用のLOCOS酸化膜1までもエッチングされると
いう問題があった。素子寸法の微細化のために、LOCOS
領域と溝部とが接する場合は、弗酸溶液の侵入部の幅が
さらに大きくなるため、LOCOS酸化膜1のエッチングさ
れる量がさらに拡大され、素子分離特性が劣化する。
However, in the above-described process, when the distance between the LOCOS oxide film 1 and the groove becomes 1 μm or less as shown in FIG. CVD silicon oxide film 5
During the etching of, the silicon oxide film 3 is also etched from the end facing the groove and progresses to a part of the LOCOS oxide film 1,
There is a problem that even the LOCOS oxide film 1 for element isolation is etched. LOCOS for miniaturization of device dimensions
When the region and the groove are in contact with each other, the width of the infiltrating portion of the hydrofluoric acid solution is further increased, so that the etching amount of the LOCOS oxide film 1 is further expanded and the element isolation characteristic is deteriorated.

問題点を解決するための手段 本発明では、溝側壁にシリコン窒化膜を形成して、薄い
シリコン酸化膜端部の溝に露出した部分を被って、この
薄いシリコン酸化膜に対する保護膜とするものである。
Means for Solving the Problems In the present invention, a silicon nitride film is formed on a side wall of a groove, and a portion of the end of the thin silicon oxide film exposed in the groove is covered to form a protective film for the thin silicon oxide film. Is.

作用 溝側壁に形成したシリコン窒化膜の保護効果により、薄
いシリコン酸化膜が露出せず、弗酸によるCVDシリコン
酸化膜のエッチング時に、薄いシリコン酸化膜およびLO
COS酸化膜が全くエッチングされない。
Action The thin silicon oxide film is not exposed due to the protective effect of the silicon nitride film formed on the side wall of the groove, and the thin silicon oxide film and the LO film are not removed when the CVD silicon oxide film is etched by hydrofluoric acid.
COS oxide film is not etched at all.

実施例 第1図(a)〜(f)に、溝形成用の窓開口の工程
(a)からシリコン窒化膜除去(f)までの工程順断面
図を示す。
Example FIGS. 1A to 1F show sectional views in order of steps from the step (a) of opening a window for forming a groove to the removal (f) of a silicon nitride film.

初め、第1図(a)のように、LOCOS酸化膜1を形成し
たシリコン基板2の表面に10nmないし100nmの厚さの第
1シリコン酸化膜3、10nmないし100nmの厚さの第1シ
リコン窒化膜4、500nmないし1500nmの厚さのCVD酸化膜
5を形成し、フォトエッチングにより溝開口部6を形成
する。次に、第2図(b)のように、CVD酸化膜5をマ
スクとして溝7を形成する。ついで、第2図(c)のよ
うに、シリコン基板保護膜として10nmないし150nmの厚
さの第2シリコン酸化膜8を溝7の内部に形成し、さら
に30nmないし150nmの厚さの第2シリコン窒化膜9を全
面に形成する。次に、第2図(d)のように、反応性イ
オンエッチングを用いて、第2シリコン窒化膜9を異方
的にエッチングし、溝7の側壁に第2シリコン窒化膜9
を残す。ついで、第2図(e)のように、弗酸溶液を用
いてCVD酸化膜5と溝7の底部の第2シリコン酸化膜8
をエッチングする。その際、LOCOS酸化膜1は、第1シ
リコン酸化膜3の端部がシリコン窒化膜9で保護されて
いるため、全くエッチングされない。最後に、第2図
(f)のように、溝7の底部で露出したシリコン基板を
20nmないし100nmの厚さで熱酸化して、次工程のリン酸
の煮沸によるシリコン基板の保護膜を形成し、約150℃
のリン酸中で、第1シリコン窒化膜4および第2シリコ
ン窒化膜9を除去する。
First, as shown in FIG. 1A, a first silicon oxide film 3 having a thickness of 10 nm to 100 nm and a first silicon nitride film having a thickness of 10 nm to 100 nm are formed on the surface of a silicon substrate 2 on which a LOCOS oxide film 1 is formed. A film 4, a CVD oxide film 5 having a thickness of 500 nm to 1500 nm is formed, and a groove opening 6 is formed by photoetching. Next, as shown in FIG. 2B, a groove 7 is formed using the CVD oxide film 5 as a mask. Then, as shown in FIG. 2 (c), a second silicon oxide film 8 having a thickness of 10 nm to 150 nm is formed inside the groove 7 as a silicon substrate protective film, and a second silicon film having a thickness of 30 nm to 150 nm is further formed. The nitride film 9 is formed on the entire surface. Next, as shown in FIG. 2D, the second silicon nitride film 9 is anisotropically etched by reactive ion etching, and the second silicon nitride film 9 is formed on the sidewall of the groove 7.
Leave. Then, as shown in FIG. 2 (e), the CVD oxide film 5 and the second silicon oxide film 8 at the bottom of the groove 7 are formed using a hydrofluoric acid solution.
To etch. At this time, the LOCOS oxide film 1 is not etched at all because the end portion of the first silicon oxide film 3 is protected by the silicon nitride film 9. Finally, as shown in FIG. 2 (f), the silicon substrate exposed at the bottom of the groove 7 is removed.
Thermal oxidation is performed at a thickness of 20 nm to 100 nm, and the protective film for the silicon substrate is formed by boiling phosphoric acid in the next step.
The first silicon nitride film 4 and the second silicon nitride film 9 are removed in the phosphoric acid of.

発明の効果 本発明により、LOCOS法で形成された厚いシリコン酸化
膜が、溝形成工程終了時でも初期の膜厚、形状のままで
残るため、素子分離特性が著しく向上する。
EFFECTS OF THE INVENTION According to the present invention, the thick silicon oxide film formed by the LOCOS method remains in the initial film thickness and shape even after the groove forming step, so that the element isolation characteristics are significantly improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(f)は本発明による溝形成工程の製造
工程を説明するための工程順断面図、第2図(a)〜
(d)は、従来の製造工程を示す工程順断面図である。 1……LOCOS酸化膜、2……シリコン基板、3……第1
シリコン酸化膜、4……第1シリコン窒化膜、5……CV
D酸化膜、6……溝開口部、7……溝、8……第2シリ
コン酸化膜、9……第2シリコン窒化膜。
1 (a) to 1 (f) are cross-sectional views in order of the steps for explaining the manufacturing process of the groove forming step according to the present invention, and FIGS. 2 (a) to 2 (f).
(D) is a process order cross-sectional view showing a conventional manufacturing process. 1 ... LOCOS oxide film, 2 ... silicon substrate, 3 ... first
Silicon oxide film, 4 …… First silicon nitride film, 5 …… CV
D oxide film, 6 ... groove opening, 7 ... groove, 8 ... second silicon oxide film, 9 ... second silicon nitride film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に第1のシリコン酸化膜、第
1のシリコン窒化膜および第2のシリコン酸化膜を順次
形成する工程、前記第2のシリコン酸化膜、前記第1の
シリコン窒化膜および前記第1のシリコン酸化膜を選択
的にエッチングし、これらに開口部を設ける工程、前記
開口部を通じて、前記半導体基板を選択的にエッチング
し、溝を設ける工程、熱酸化法により、前記溝の表面に
第3のシリコン酸化膜を形成する工程、前記溝を含む全
面に第2のシリコン窒化膜を形成する工程、異方性エッ
チングにより前記溝の側面に前記第2のシリコン窒化膜
を残す工程、前記第2のシリコン酸化膜と前記溝の底部
の前記第3のシリコン酸化膜を除去する工程、熱酸化法
により前記溝底部に露出した前記半導体基板を酸化する
工程を含むことを特徴とする半導体装置の製造方法。
1. A step of sequentially forming a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film on a semiconductor substrate, the second silicon oxide film, and the first silicon nitride film. And a step of selectively etching the first silicon oxide film to form openings therein, a step of selectively etching the semiconductor substrate through the openings to form a groove, and a step of forming the groove by a thermal oxidation method. Forming a third silicon oxide film on the surface of the substrate, forming a second silicon nitride film on the entire surface including the groove, and leaving the second silicon nitride film on the side surface of the groove by anisotropic etching. A step of removing the second silicon oxide film and the third silicon oxide film at the bottom of the groove, and oxidizing the semiconductor substrate exposed at the bottom of the groove by a thermal oxidation method. The method of manufacturing a semiconductor device according to symptoms.
JP3945587A 1987-02-23 1987-02-23 Method for manufacturing semiconductor device Expired - Lifetime JPH0744213B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3945587A JPH0744213B2 (en) 1987-02-23 1987-02-23 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3945587A JPH0744213B2 (en) 1987-02-23 1987-02-23 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63205927A JPS63205927A (en) 1988-08-25
JPH0744213B2 true JPH0744213B2 (en) 1995-05-15

Family

ID=12553515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3945587A Expired - Lifetime JPH0744213B2 (en) 1987-02-23 1987-02-23 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0744213B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420757B1 (en) 1999-09-14 2002-07-16 Vram Technologies, Llc Semiconductor diodes having low forward conduction voltage drop, low reverse current leakage, and high avalanche energy capability
US6433370B1 (en) 2000-02-10 2002-08-13 Vram Technologies, Llc Method and apparatus for cylindrical semiconductor diodes
US6580150B1 (en) 2000-11-13 2003-06-17 Vram Technologies, Llc Vertical junction field effect semiconductor diodes
US6537921B2 (en) 2001-05-23 2003-03-25 Vram Technologies, Llc Vertical metal oxide silicon field effect semiconductor diodes
US6958275B2 (en) 2003-03-11 2005-10-25 Integrated Discrete Devices, Llc MOSFET power transistors and methods

Also Published As

Publication number Publication date
JPS63205927A (en) 1988-08-25

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