JPH0744267B2 - Gate turn-off thyristor manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a gate turn-off thyristor.

B. Summary of the Invention The present invention relates to a method of manufacturing a gate turn-off thyristor (hereinafter abbreviated as GTO element), which is an improvement of the configuration of a surge absorber element connected between a gate and a cathode and the configuration of a main gate turn-off thyristor. A surge absorber element connected between the gate and cathode of the GTO element is formed on the same wafer and N ₅
And the layer surface portion, N _5-layer and P ₂ layer junction surface portion Yotsute the selective epitaxial growth so as to expose the P ₂ ^- the surface portion has failed to selective epitaxial growth to form a layer on the P ₂ layers By forming an annular groove with a constant depth by etching, the withstand voltage of the surge absorber element can be arbitrarily controlled without lowering the breaking resistance of the GTO element.

C. Prior art FIG. 5 is an explanatory diagram of the structure of a GTO element having an amplification gate.
In FIG. 5, the main GTO unit 1 is composed of P ₁ N ₁ P ₂ N ₂ ,
The amplification GTO unit 2 is composed of P ₁ N ₁ P ₂ N ₃ . 3 is the main GTO department 1
Cathode electrode, 4 is the gate electrode of the main GTO unit 1, 5 is the cathode electrode of the amplifying GTO unit 2, and this cathode electrode 5 is the main GTO unit.
It is connected to the gate electrode 4 of the TO part 1 by the connecting body 6. 7
Is a gate electrode of the amplification GTO unit 2. In the figure, G is a gate terminal and K is a cathode terminal.

8 is an amplification GTO section 2 that does not directly pass the gate current to the main GTO section 1.
A diode for flowing only into the amplifier, 9 is a zener diode that gives a bias to the amplifying GTO section 2, and a series body of the zener diode 9 and the diode 8 is a connecting body 6 and an amplifying GT
It is connected between the gate electrodes 7 of the O portion 2. 10 is amplification GTO section 2
Make sure that the on-current of the main GTO unit 1 does not flow to the cathode
A diode for flowing to the gate of the TO unit 1 and a Zener diode 11 for a surge absorber element that absorbs energy stored in the inductance due to wiring of the gate circuit. The series body of the diode 10 and the Zener diode 11 is connected between the connection body 6 and the cathode electrode 3.

FIG. 6 is an electric circuit diagram of FIG. 5, in which A is an anode terminal.

In the embedded gate type GTO device configured as shown in FIG. 5, a gate-off voltage of 60V is normally applied. However, when the GTO element is turned off, the gate G,
An overvoltage of 60 V or more may be applied between the cathodes K. It is known that the cause of this overvoltage is due to the energy stored in the inductance due to the wiring of the gate circuit and the like. Therefore, in the GTO element, the breakdown voltage between the gate G and the cathode K is set to sufficiently withstand up to about 120 V, but when an overvoltage higher than the breakdown voltage is applied, the junction between the gate G and the cathode K is destroyed. Will end up. Therefore, when an overvoltage is generated between the gate G and the cathode K, the Zener diode 11 operates to absorb the overvoltage and prevent the breakdown.

D. Problems to be Solved by the Invention However, since the Zener diode 11, which is a surge absorber element, is configured to be externally connected, the following problems occur.

(1) Since the surge absorber element is externally connected, the function as an absorber in which a surge occurs due to the inductance of the wiring is deteriorated.

(2) Since the external connection is made, there is a risk that the wiring may be shorted in the case.

(3) The case structure becomes complicated by externally connecting the surge absorber element.

(4) The number of steps for assembling the case increases.

(5) The case becomes large in size to accommodate the diode and the like in the case.

(6) Since a diode and a Zener diode are connected to the GTO element itself, the yield decreases due to a defective connection.

(7) In order to solve the above-mentioned problems, it has been considered to form a surge absorber element on the same wafer. As one of these, it is considered to be configured so as to obtain a Zener voltage on the same wafer. However, with such a structure, a new problem arises that interrupts the breaking current of the GTO element.

E. Means for Solving the Problems The present invention forms an independent N ₅ layer on the P ₂ layer surface on which the P ⁺ low resistance layer is formed, and forms the N ₅ layer surface portion and the N ₅ layer. As the surface of the junction with the P ₂ layer is exposed, P _{2 with} a lower impurity concentration than the surface concentration of the P ₂ layer was formed by selective epitaxial growth.
^- to form a layer, the selection epitaxial said surface portion has failed grown to form the annular groove of the O connexion predetermined depth in the etching process, the N ₂ Layers P ₂ ^- P so as to form the layer ₂ ^- A P ₂ ⁺ layer was formed on the outer peripheral surface of the layer, the P ₂ ⁺ layer and the cathode N ₂ layer formed on the P ₂ ⁻ layer were electrically connected, and a surge absorber portion was formed on the same wafer. It is a thing.

F. By action selective epitaxial growth, the N ₅ layer surface area, N ₅ layer and P
_2-layer surface portion P ₂ ^- since the layer of the both surfaces unit has failed to form etching process to form the annular groove of constant depth can be arbitrarily controlled Zener voltage of the surge absorber.

G. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings, in which the same portions as those in FIG.

In FIG. ₁ , _first , gallium is diffused on the original wafer N ₁ to form P ₁ and P ₂ layers. Wafer N _{1 at} this time
Is 4 × 10 ¹³ [Atoms cm ^-3 ] with a thickness of 400 μm, and the surface concentration of P ₂ is 1.8 × 10 ¹⁷ to 6.0 × 10 ¹⁷ [Atoms cm ^-3 ].
s cm ^-3 ], and the depth was 30 μm. The sheet resistance is 120
It was set to about Ω.

Next, phosphorus is diffused into the P ₂ layer to form an N ₅ layer. At this time N ₅
The surface concentration of the layer is 10 ¹⁸ [Atoms cm ^-3 ], and the diffusion depth is 15.5μ.
m. After forming the N ₅ layer, boron is diffused into the P ₂ layer to obtain the concentration.
A buried gate of P ⁺ layer of 10 ¹⁹ or more [Atoms cm ^-3 ] is formed. After the P ⁺ layer formed, and N ₅ layer surface portion on P ₂ layer surface, N _5-layer and P ₂
Row selection epitaxial growth as joint surface portions of the layer are exposed connexion P ₂ ^- to form a layer. To this end, an oxide film is formed on the junction surface between the N ₅ layer and the P ₂ layer, and the epitaxial film is selectively grown only on the part where there is no oxide film using this oxide film as a mask. P ₂ ^- surface concentration of the layers 10 ^-15 Atoms cm ^-3]
And the thickness is 30 μm. P ₂ ^- Omitsuku layer on the surface of the layer P ^+,
P ₂ ⁺ and cathode N ₂ and N ₃ layers are formed. The surface concentration of the N ₂ and N ₃ layers is 4 × 10 ¹⁹ [Atoms cm ⁻³ ] and the depth is 8 μm.

After forming the P ⁺ , N ₂ , and N ₃ layers on the P ₂ ⁺ layer as described above to form a GTO device, the portion (N ₅ layer surface portion, N ₅ layer and P The junction surface portion with the _two layers) is etched to form an annular groove 14 that deepens the diffusion depth during the etching.

Depending on the depth of this etching process, the surge absorber section
The breakdown voltage (Zener voltage) of 13 can be changed arbitrarily. For example, to design this voltage to about 70 V, etching is performed so that the P ₂ layer etching surface becomes about 10 ^{17 with the} etched surface impurity concentration. FIG. 2 is a net impurity concentration distribution characteristic diagram of the main GTO portion and the N ₅ layer portion.

Reference numeral 12 is an auxiliary electrode of the surge absorber portion 13, and this auxiliary electrode 12 is connected to the cathode electrode 3. FIG. 3A is an enlarged view of a main part of the surge absorber section 13, and FIG. 3B is an equivalent circuit diagram of the surge absorber section 13. A high resistance R (shunt resistance) is connected in parallel to the surge absorber section 13. ing. The breakdown operation of the surge absorber 13 thus formed has the characteristics shown in FIG. In FIG. 4, the region with high differential resistance depends on the high resistance R, and the region with low differential resistance breaks down the N ₅ P ₂ junction. The breakdown voltage at this time is about 70V as described above. That is, since the N ₅ layer is formed, only a voltage of up to 70 V is applied between the gate G and the cathode K, so that the gate G and cathode K junction can be protected from a surge generated at turn-off.

In the GTO element formed as described above, the Zener voltage is determined by the etching depth (depth of the annular groove 14). In this case, the etching depth is increased by increasing the diffusion depth. The shunt resistance R shown in FIG. 3A becomes large. However, AK determined by N ₁ P ₂ junction of GTO element
Since the withstand voltage is reduced, the depth must be set in consideration of the withstand voltage between A and K.

H. Effect of the Invention As described above, according to the present invention, the surge absorber portion is formed on the same wafer and the N ₅ layer surface portion and the N ₅ layer and P ₂ layer bonding surface portion are exposed. selective epitaxial growth Yotsute P ₂ ^- since its surface portion has failed is grown to form the annular groove of the O connexion constant depth to etching treatment so as to form the layer, improving the interruption capability of the GTO element It is possible to increase the Zener voltage as well as the voltage. In addition to the above, the external connection wiring of the surge absorber element is not required, and there is an advantage that the surge penetrating from the wiring is eliminated. Furthermore, since wiring is not required, the possibility of wiring shortage and disconnection can be greatly reduced, and the case structure can be simplified. In addition, since there are no external connection parts, the reliability of the device is improved, and the assembly is simple, and so on.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
Characteristic diagram of net impurity concentration distribution in GTO and N ₅ layers, No. 3
Figures A and B are enlarged and equivalent circuit diagrams of the surge absorber.
FIG. 4 is a breakdown characteristic diagram of the surge absorber portion, FIG. 5 is a configuration diagram showing a conventional example, and FIG. 6 is an electrical circuit diagram of FIG. 1 ... Main GTO section, 2 ... Amplifying GTO section, 3 ... Main GTO section cathode electrode, 4 ... Amplifying GTO section gate electrode, 5 ... Amplifying GTO section
Part Cathode electrode, 6 ... Connector, 7 ... Amplification GTO part gate electrode, 12 ... Surge absorber electrode, 13 ... Surge absorber part, 14 ... Annular groove, G ... Gate, K ...
Cathode, A ... Anode, R ... Diversion resistance.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/74 P 301

Claims (1)

[Claims] 1. A four layers of _{P 1 N 1 P 2 N 2} , on the current flowing through the P ₁ N ₁ P ₂ N ₂ by embedding a P ⁺ low resistance layer P _2, so as to turn off control In the method for manufacturing a semiconductor element configured as described above, after forming an independent N ₅ layer on the P ₂ layer surface on which the P ⁺ low resistance layer is formed, this N ₅ layer surface portion, N ₅ layer and P ₂ as joint surface portions of the layer are exposed, rather than the surface concentration of the P ₂ layer less P ₂ impurity concentration by selective epitaxial growth ^- constant to form a layer, the surface portion of the did not selective epitaxial growth by an etching process after forming the annular groove of depth, the P ₂ ^- to form a N ₂ layer to layer, the P ₂ ^- on the outer peripheral surface portion of the layer to form a P ₂ ⁺ layer, then, P ₂ ⁺ layer and the P ₂ ^- connecting the cathode N ₂ layer formed on the layer electrically, to form a surge absorber unit on the same wafer on this And a method for manufacturing a date turn-off thyristor characterized by.