JPH0744271B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a method for manufacturing an ultra-high speed and highly reliable VLSI device.

The present invention includes a gate. Source. The present invention provides a manufacturing method which is effective in reducing the resistance of a drain region and preventing alloy spikes and migration of a contact portion.

[Conventional technology]

Figures 2 and 3 show schematic diagrams of conventional devices. FIG. 2 shows the gate. Source. A silicide layer 28 is formed in the drain portion and wiring is made of AL alloy.

[Problems to be solved by the invention]

As described above, the silicide alone has a drawback that the barrier property between the Al alloy and the diffusion layer is not sufficient, and the contact resistance also varies widely. On the other hand, FIG. 3 shows an example in which the barrier layer is formed before the deposition of the Al alloy in order to improve this point. However, a new process is required, and the barrier property of the hepatorenal contact part is In some cases, it was insufficient due to the coverage. In addition, in order to solve the above-mentioned problems, after forming a metal silicide layer on the gate, source and drain regions, nitrogen ions are implanted into the metal silicide layer and annealing is performed to form a barrier layer only on the silicide. There is also an example in which a metal nitride film to be formed is formed in a self-aligned manner, but it requires two steps of a nitrogen ion implantation step and an annealing treatment step, and further, the impurities implanted into the source and drain regions by the annealing treatment are There was a problem of evaporation.

[Means for solving problems]

The method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device having a source region, a drain region and a gate electrode as constituent elements, and (a) forming the gate electrode on a semiconductor substrate via an insulating film. (B) a step of forming a sidewall insulating film on the side surfaces of both ends of the gate electrode,
(C) depositing a metal film on the semiconductor substrate having the gate electrode, (d) forming a metal silicide film on the semiconductor substrate on which the gate electrode and the sidewall insulating film are not formed, e) a step of forming a metal nitride film by nitriding the surface of the metal silicide film by performing heat treatment by lamp annealing in a nitrogen atmosphere at 1000 ° C. or higher, (f) through the metal nitride film and the metal silicide film A step of introducing impurities for forming the source and drain regions, (g) a step of forming an insulating film on the semiconductor substrate, and (h) a heat treatment by lamp annealing at 1000 ° C. or higher to activate the impurities. Forming the source and drain regions, (i)
It further comprises at least a step of forming a contact hole in the insulating film on the source and drain regions, and (j) a step of forming a wiring layer on the insulating film and in the contact hole.

〔Example〕

 The present invention will be described below with reference to examples.

FIG. 1 shows a schematic sectional view of the present invention. An element isolation layer 2 is formed on a semiconductor substrate 1, and a polycide electrode composed of a gate film 3, phosphorus-doped polysilicon 4 and molybdenum silicide 5 is formed, and then a low-concentration diffusion layer 6 is formed in order to improve photoelectron resistance. . Next, after forming the side wall oxide film 7 on the electrode end, a Ti film is formed on the entire surface.
Make a 500Å deposition.

Source is obtained by lamp annealing in N ₂ at 800 ° C. for 30 seconds and etching with NH ₄ OH + H ₂ O ₂ aqueous solution. A TiBi ₂ layer (850Å) is formed only on the drain part. Furthermore, at 1050 ℃, in N ₂ 3
By performing lamp annealing for 0 seconds, the TiSi ₂ layer 8 is
A TiN layer 10 is formed with a thickness of about 100Å. Subsequently, high-concentration impurities are ion-implanted from above the laminated film, and after the interlayer insulating film 11 is deposited, lamp annealing is performed at 1050 ° C., whereby the impurities are pushed out to the TiSi ₂ lower layer and activated. After the contact etching, the AL alloy wiring 12 is performed and completed.

〔The invention's effect〕

Source. The TiSi ₂ layer formed on the drain part is annealed at an appropriate temperature and time with N ₂ so that TiN _{2 is} removed from the surface.
Will be transformed. This TiN layer has good adhesion to the underlying TiSi ₂ layer, low interfacial resistance, is a conductor, and has a large barrier property with AL, so it can be formed on the surface without compromising the characteristics of the TiSi ₂ layer. . Contact resistance of the device thus formed is a 1μ ^□, 5Ω / ^□ or less, in Jiyankushiyon of 0.2.mu., is stable up to 550 ° C., hardly occur reaction with AL. In the present embodiment, the molybdenum polycide electrode has been described, but it goes without saying that the present invention is also applicable and effective for polysilicon, silicide, and refractory metal electrodes. Furthermore, according to the method for manufacturing a semiconductor device of the present invention, after forming the metal nitride film,
Impurities that form the source and drain regions (in the case of a semiconductor device having an LDD structure, impurities that form a high-concentration impurity region) are introduced, and the impurities are activated after being covered with an insulating film. Etc. can be prevented, and eventually impurities can be introduced with good controllability.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to the present invention, and FIGS. 2 and 3 are sectional views of a semiconductor device manufactured by a conventional manufacturing method. 1 ... Semiconductor substrate 2 ... Separation oxide film 3 ... Gate oxide film 4 ... Phosphorus-doped polysilicon 5 ... Molybdenum silicide 6 ... Low-concentration diffusion layer 7 ... Sidewall oxide film 8 ... TiSi ₂ layer 9 …… High-concentration diffusion layer 10 …… TiN layer 11 …… Interlayer insulating film 12 …… AL alloy wiring 28 …… TiSi ₂ layer 30 …… TiN layer

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a source region, a drain region and a gate electrode as constituent elements, comprising: (a) forming the gate electrode on a semiconductor substrate with an insulating film interposed between the gate electrode and the gate electrode; A side wall insulating film is formed on side surfaces of both ends of the gate electrode, (c) a metal film is deposited on the semiconductor substrate having the gate electrode, and (d) the gate electrode and the side wall insulating film are formed. A step of forming a metal silicide film on a non-existing semiconductor substrate, (e) a step of forming a metal nitride film by nitriding the surface of the metal silicide film by performing heat treatment by lamp annealing in a nitrogen atmosphere at 1000 ° C. or higher (F) introducing impurities for forming source and drain regions through the metal nitride film and the metal silicide film, (g) Forming an insulating film on a conductor substrate; (h) activating the impurities by heat treatment by lamp annealing at 1000 ° C. or higher to form the source and drain regions; (i) forming a source and drain region on the source and drain regions; A method of manufacturing a semiconductor device, comprising: at least a step of forming a contact hole in the insulating film; and (j) forming a wiring layer on the insulating film and in the contact hole.