JPH0744569B2 - Serial data receiving circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a receiving circuit in serial data communication, and more particularly to a serial data receiving circuit that requires status information.

[Conventional technology]

Conventionally, a certain data communication protocol, for example, HD
As a method of receiving serial data sent in LC (High Level Data Link-Control Procedure) frame format, there is a method of separately treating received data and status data related to the received data as shown in FIG. It was taken. When receiving the signal X sent by the signal line 306 in HDLC frame format, serial-parallel conversion is performed in the following procedure.
First, when the receiving circuit becomes the receivable state, the receiving circuit enters the synchronous detection mode, and the detection of the flag in the serial data X received by the shift register 301 is started. This state continues until the first flag is detected. When the flag is detected and the frame synchronization for the serial data X is established, the state transits to the data receiving state and the assembling of the received data is started. In the data receiving state, the received data output from the shift register 301 is assembled into n-bit parallel data Y by the serial / parallel conversion circuit 302 for each predetermined bit length n. Each time the parallel data Y is assembled, it is transferred to the reception FIFO memory 303 through the signal line 307. The normal reception FIFO memory 303 has a FIFO structure of several stages. Each stage of the reception FIFO memory 303 is an n-bit wide register for storing the parallel data Y, a 1-bit youth bit register indicating the existence of the parallel data Y, and the last data of the reception frame. It consists of a 1-bit end bit register that indicates that. The receiving circuit requests the host system to retrieve the parallel data Y by the use bit register at the top of the receiving FIFO memory 303. The host system continues to read parallel data from the receive FIFO memory 303 sequentially until the end bit register is active to read the received data.

The flag detection function is effective even during reception of data in the receiving circuit, and if the flag is detected again after shifting to the data receiving state once, it is regarded as the end of one frame and shifts to the receiving end state. When the reception of the frame is completed, the status generation circuit 304 writes the status data Z of the frame to the status register 305 through the signal line 308.

The host system receives the last data in the frame FIFO
Status register 305 after being removed from memory 303
To check that there is no error in the received frame.

By the above method, the serial data X sent in the HDLC frame format is converted into the parallel data Y and received.

[Problems to be solved by the invention]

According to the conventional method described above, when the parallel data Y converted from the input serial data X is read, the status data regarding the frame is read after reading all the parallel data Y of one frame. Determine the validity of the received frame. Therefore, until the status data of one received frame is read,
There is a drawback that the next frame cannot be received.

In the conventional receiving circuit described above, the received serial data and status data are processed as independent information, whereas the present invention treats each as the same received information, which has an original content.

The object of the present invention has been made in view of the above-mentioned drawbacks. In a receiving circuit for converting serial data X received by an HDLC frame format into parallel data Y, parallel data Y and its status data Z Are alternately written to the reception FIFO memory to store as one reception information including these two data for each frame, and continuously without waiting for the result of judgment of the validity of the status data Z by the host system. The point is to be able to receive frames.

[Means for solving problems]

The serial data receiving circuit according to the present invention is
Serial data X transmitted according to a predetermined frame format of data communication is received and temporarily stored in the shift register for each frame, and a predetermined flag is detected from the temporarily stored serial data X to detect the frame. When synchronization is established and a data reception state is established, the serial / parallel conversion circuit converts the serial data X supplied from the shift register into parallel data Y in units of n bits, and the status generation circuit receives the data. The cyclic receive check of the serial data X is performed to generate the status data Z, and the status data Z is read after the last data of the predetermined reception frame is read by the host system. The next frame can be received after the validity of In the serial data reception circuit; either the status generation circuit or the reception length counter that counts the data length of each reception frame, and the period of the start flag and end flag of each reception frame are inactive, and the end A status write control circuit that is active during the period between the flag and the next head flag, and one output signal of the status generation circuit and the reception length counter in response to the output signal of the status write control circuit and the serial / parallel signal. A multiplexer that selects one of the output signals of the conversion circuit and a reception FIFO that stores the selection output signal of the multiplexer are provided. When the output signal of the status write control circuit is inactive, the parallel data Y is , When said active The status data Z are alternately written in the reception FIFO memory and stored as one reception information including these two data for each frame, and the host system determines the validity of the reception frame. It is characterized in that the frame can be continuously received without waiting for the result.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of the first embodiment of the present invention. In the figure, 101 is, for example, an 8-bit shift register, which is a signal line in the HDLC frame format.
A flag is detected from the serial data X sent by 108 to establish frame synchronization with the HDLC frame. When the flag is detected and the frame synchronization for the serial data X is established, the data receiving state is transited and the assembling of the received data is started. In the data reception state, the received serial data X output from the shift register 101 by the serial / parallel conversion circuit 102.
Are assembled into parallel data Y having an n-bit length for each predetermined bit length n and output to the signal line 109. Each time the parallel data Y is assembled, it is transferred to the reception FIFO memory 104 through the multiplexer 103. The multiplexer 103 receives the parallel data Y output from the serial / parallel conversion circuit 102 and the reception CRC.
And the status data Z, which is the output of the reception CRC status generation circuit 105 for performing the check, is multiplexed by the status write control signal 107 described later to receive FIFO.
Transfer to the memory 104. The normal reception FIFO 104 has a FIFO structure of several stages. Each stage of the reception FIFO memory 104 is an n-bit wide register for storing the parallel data Y, a 1-bit use bit register indicating the existence of the parallel data Y, and the last data of the reception frame. It consists of a 1-bit end bit register that indicates that.
The receiving circuit uses the use bit register in the first stage of the receiving FIFO memory 104 for parallel connection to the host system.
Request to retrieve data Y. The flag detection function of the shift register 101 is effective even during reception of data in the reception circuit. If the flag is detected again after shifting to the data reception state, it is considered that one frame has ended, and reception is ended, but the next The frame shift detection state is entered for frame reception. The status writing control circuit 106 is a status writing control signal while the frame synchronization is established, that is, between the head flag and the end flag of the frame.
107 is made inactive and parallel data Y is written in the reception FIFO memory 104 through the multiplexer 103. Further, the status write control signal 107 becomes active between the reception frame and the next reception frame, that is, while the end flag is detected and the next flag is detected, and the reception C
The status data Z of the RC status generation circuit 105 is written in the reception FIF memory O104 through the signal line 101. When the reception of the frame is completed, the reception CRC status generation circuit 105 writes the status data Z of the reception frame into the reception FIFO memory 104 through the multiplexer 103. Through this series of operations, the reception circuit can continuously buffer the reception frames in the HDLC format in the reception FIFO memory 104 together with the reception status as long as the reception FIFO memory 104 has a free space. On the other hand, the host system sequentially continues to read the received data from the receive FIFO memory 104 until the received data whose end bit register is active, that is, the last data of the received frame is read. The host system detects the last data of one received frame by the end bit register,
After taking out the data from the reception FIFO memory 104, the reception FIFO memory 104 is read again. The read data is the CRC check status data Z related to the received frame generated by the received CRC status generation circuit 105, and it is confirmed from this status that the received frame has no error. If more data is stored in the receive FIFO memory 104, it is the next frame of received data and the host system again receives the receive FIFO memory 10
Start reading the received data from 4.

By the above method, the serial data X sent in the HDLC frame format is converted into the parallel data Y, and the status Z of the received frame is also continuously written in the receive FIFO memory.
LC frames can be received.

FIG. 2 is a block diagram showing the system configuration of the second embodiment of the present invention. This figure shows a configuration example in which a reception length counter is arranged for the status generation circuit which is the CRC check circuit in FIG. In this embodiment, the host
This is effective when the system uses DMA etc. to read the received data. A receiving circuit for converting the received serial data X sent through the signal line 208 into parallel data Y has the same configuration as the serial / parallel conversion circuit of FIG.

In FIG. 2, 201 is an 8-bit shift register, which is HDL.
A flag is detected from the serial data X sent in the C frame format to establish frame synchronization with the HDLC frame. When the flag is detected and the frame synchronization for the serial data X is established, the state transits to the data receiving state and the assembling of the received data is started. In the data receiving state, the serial / parallel conversion circuit 202 assembles the serial data X output from the shift register 201 into parallel received data Y having an n-bit length, and the signal line 209
Output to. The reception data Y is transferred to the reception FIFO 204 through the multiplexer 203 every time it is assembled. The multiplexer 203 outputs the parallel data Y output from the serial / parallel conversion circuit 202 and the status data Z output from the reception length counter circuit 205 that counts the data length of the reception frame, to a status write control signal 207 described later. By multiplexing and receiving FIF
Transfer to O memory 204. The normal reception FIFO memory 204 has a FIFO structure of several stages. Each stage of the reception FIFO memory 204 is an n-bit wide register for storing the parallel data Y, a 1-bit use bit register indicating the existence of the parallel data Y, and the last data of the reception frame. It consists of a 1-bit end bit register that indicates that. The receiving circuit requests the host system to take in the parallel data Y by the use bit register at the head stage of the receiving FIFO memory 204. The flag detection function is effective even when the receiving circuit is receiving data, and if the flag is detected again after shifting to the data receiving state, 1
The reception is considered to be the end of one frame, but the frame synchronization detection state is entered again for the reception of the next frame. The status write control circuit 206 makes the status write control signal 207 inactive while the frame synchronization is established, that is, between the head flag and the end flag of the frame, and sets the parallel data Y to the multiplexer 203.
Through the receive FIFO memory 204. Further, the status write control signal 207 becomes active between the reception frame and the next reception frame, that is, while the end flag is detected and then the next flag is detected, and the status data Z of the reception length counter circuit 205 is output 210. Is written to the reception FIFO memory 204 through. When the reception of the frame is completed, the reception length counter circuit 205 writes the status data Z of the reception frame into the reception FIFO 204 through the multiplexer 203. Through this series of operations, the reception circuit can continuously buffer the reception frames of the HDLC format in the reception FIFO 204 as long as the reception FIFO 204 has a free space. On the other hand, the host system sequentially continues to read the received data from the reception FIFO memory 204 until the end bit register is active, that is, the last data of the received frame is read. The host system detects the last received data of one received frame by the end bit register, retrieves the data from the receive FIFO memory 204, and then reads the receive FIFO memory 204 again. The read data is the status data Z relating to the received frame created by the received length counter circuit 205, and the host system confirms from this status data Z that the received frame has no error. If received
If more data is stored in the FIFO memory 204, it is the received data of the next frame, and the host system starts reading the received data from the receive FIFO memory 204 again.

By the above method, the serial data X sent in the HDLC frame format is converted into the parallel data Y, and the status of the received frame is continuously written in the receive FIFO memory.
The frame can be received.

〔The invention's effect〕

As described above, according to the present invention, for example, in a receiving circuit that converts serial data X, which is a received signal sent in the HDLC frame format, into parallel data Y, status write control from serial data X is performed. Parallel data Y and status data Z are alternately written to the reception FIFO memory in response to the active and inactive status control signals obtained by the circuit, and one reception including these two data is performed for each frame. Is stored as information,
It becomes possible to receive HDLC frames continuously without waiting for the result of the host system to judge the validity of received frames.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment using the present invention, FIG. 2 is a block diagram showing a second embodiment 2 using the present invention, and FIG. 3 is a system configuration of a conventional example. It is a block diagram shown. 101 ... Shift resistor, 102 ... Serial / parallel conversion circuit, 103 ... Multiplexer, 104 ... Reception FIFO memory, 105 ... Status generation circuit, 106 ... Status writing control circuit, 107 ... Status writing control signal , 108 ... serial data X, 109 ... parallel data Y, 110 ... status data Z, 201 ... shift register, 202 ... serial-parallel conversion circuit, 203
...... Multiplexer, 204 …… Reception FIFO, 205 …… Status generation circuit, 206 …… Status writing control circuit, 2
07 ... Status writing control signal, 208 ... Reception signal X, 209 ... Parallel conversion data Y, 210 ... Status data Z, 301 ... Shift register, 302 ... Serial / parallel conversion circuit, 303 ... Receive FIFO, 304 ... Status generation circuit, 305 ... Status register, 306 ...
… Received signal X, 307 …… Parallel conversion data Y, 308 ……
Status data Z.

Claims (1)

[Claims] 1. A predetermined frame for serial data communication.
When the serial data X transmitted according to the format is received and temporarily stored in the shift register for each frame, a predetermined flag is detected from the temporarily stored serial data X, frame synchronization is established, and a data reception state is set. , A serial-parallel conversion circuit converts the serial data X supplied from the shift register to n
The bit data is converted into parallel data Y, and the status generation circuit performs a cyclic redundancy check on the received serial data X to generate status data Z. In a serial data receiving circuit capable of receiving the next frame after determining the validity of the predetermined received frame by reading the status data Z after reading the data; the status generation circuit or the received frame A status in which one of the reception length counters that counts the data length of each frame, the head flag and the end flag of each received frame is inactive, and the end flag and the next head flag are active. Write control circuit and output of this status write control circuit A multiplexer that selects one of the output signals of the status generation circuit and the reception length counter and the output signal of the serial-parallel conversion circuit in response to a signal, and a reception FIFO that stores the selection output signal of the multiplexer. And when the output signal of the status write control circuit is inactive, the parallel data Y is written alternately in the receive FIFO memory and the parallel data Y is written in the receive FIFO memory in one frame. 1 including each of these two data
Is stored as one received information and the host
A serial data receiving circuit characterized in that it is possible to continuously receive the frame without waiting for a result of judgment of the validity of the received frame by the system.