JPH0746320B2 - History information storage device - Google Patents

Description

The present invention relates to an information processing system having an address conversion unit, and in particular, a history information storage device for storing history information generated by updating address conversion information by software. Regarding

(Prior Art) In fields such as data processing and data communication, an information processing system including a computer is generally used. In recent years, such information processing systems have become increasingly complex and include more sophisticated functions.

Therefore, it is often very difficult to investigate and analyze the illegal exception condition that occurs when the system is operating and to find out the cause. In particular, a virtual memory system that requires address conversion from a logical address on a program to an absolute address on a main memory device is executed because hardware, firmware, and software are intricately entangled with each other. It is even more difficult to find out the cause of the illegal exception condition. Furthermore, it is even more difficult in a multiprocessor system including a plurality of computer systems.

(Problems to be Solved by the Invention) The above-described conventional information processing system requires a great deal of man-hours and time to investigate and analyze the cause of such an illegal exception condition and measure the problem. There is a drawback that

An object of the present invention is to eliminate the above-mentioned drawbacks by sequentially storing information relating to execution of a translation information update instruction for address translation, and to read it when an illegal exception condition or the like occurs, thereby making it possible to investigate the cause. It is an object of the present invention to provide a history information storage device configured so as to quickly perform.

(Means for Solving Problems) The history information storage device of the information processing system according to the present invention is
At least one main memory device, and when reading information from the main memory device or writing information to the main memory device, on the main memory device based on the address conversion information from the logical address on the program An address translation mechanism for translating to an absolute address, an address translation buffer for speeding up the address translation, one or more software instructions for updating the address translation information, and a central processing unit,
In an information processing system including a supervisor processor and a supervisor processor, information relating to execution of the software instruction in the main memory device (eg, instruction counter, instruction code, address information for updating the address translation information, and update data) Etc.) as history information of execution of the software instruction, a history information storage unit, a storage permission state in which the history information storage unit is permitted to store the history information, and a storage inhibition state in which the storage is suppressed. Storage designation means for designating, and storage designation determination means in the central processing software for determining whether the storage designation means designates the storage permission state or the storage inhibition state when the software instruction is executed, When the memory designation determining means determines that the memory permission state is designated, the history information is Storage means for sequentially storing in the history information storage means, illegal exception occurrence notifying means for notifying the supervisor processor of the illegal exception when the illegal exception occurs, and in the supervisor processor History information storage means configured to read the history information from the history information storage means and store the history information in an error log file of a supervisor processor in response to the notification. The problem can be solved.

(Example) Next, a history information storage device according to the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment according to the present invention.

This system includes two central processing units (hereinafter referred to as CPUs) 21 and 22, two input / output control units (hereinafter referred to as IOPs) 25 and 26, and a main memory unit (hereinafter referred to as MMU). .)
23, a system control unit (hereinafter referred to as an SCU) 24 for centrally controlling an interface between the CPU and the IOP, and the SCU 2 via the SCU 24.
All RAS (Re
Supervisor processor (SV) that centrally controls liability, availability, and serviceability functions and at the same time controls the man-machine interface for RAS functions.
P) 27 and.

FIG. 2 is a diagram showing a control structure in the main memory device which constitutes a part of the history information storage device according to the present invention. In FIG. 2, 1 is a main memory, 2 is a pointer area, 3 is a FW work area, 4 is a FW stack pointer, 5 is a FW stack area, 6-9 are CPU areas, 10 are pointers, and 11 is history information storage. Area. Main memory device 1 in FIG.
Includes a pointer area 2 and an FW (firmware: FW) work area 3 according to the present embodiment.

The pointer area 2 is provided with a 4-byte FW stack pointer 4 starting from the address 20H (hexadecimal number), for example. The FW stack pointer 4 has an address indicating the FW stack area 5 included in the FW work area 3, a trace mode bit (indicating whether history information is stored or not), and a logout display bit (stored history information is stored). Indicates whether or not you are logged out.)

The FW stack area 5 includes areas having the same capacity corresponding to each CPU (central processing unit, referred to as CPU in the following description). That is, these areas are CPU # 0 area 6, CPU #
The first area 7, the CPU # 2 area 8 and the CPU # 3 area 9.

CPU♯0 region 6 and the pointer 10 to identify the CPU, 2 ¹⁰ -1
And a history information storage area 11. History information storage area
11 indicates the type of the executed instruction, each task at the time of executing the instruction, the content of the instruction counter (IC), the content of the general-purpose register G1,
And the contents of the general-purpose register G1 + 1 are stored.
These general-purpose registers will be described later. The CPU # 1 area 7, the CPU # 2 area 8, and the CPU # 3 area 9 are also configured in exactly the same manner as the CPU # 0 area 6.

FIG. 3 (a) is a diagram for explaining the format of an instruction related to updating address translation information. In FIG. 3 (a), the command is
It consists of 16 bits, and each instruction has an 8-bit instruction code.
It has general-purpose register numbers G1 and G2 each consisting of 4 bits.

FIG. 3 (b) is a diagram for explaining the format of a general-purpose register involved in updating address translation information.

General-purpose registers G1, G2, and G2 + 1 are used to execute the STGSD instruction. The general-purpose register G1 includes a segment number SEG # of 0th to 15th bits and a task name of 16th to 31st bits.
General register G2 is the first word of segment descriptor SD, and general register and G2 + 1 are segment descriptor SD.
Is the second word of.

General-purpose registers G1, G1 + 1, G2 are used to execute the STGPD instruction. In the general register G1, the 0th to 15th bits are undefined, and the 16th to 31st bits are the task name. General-purpose register G1
For the contents of +1, the 0th to 15th bits are segment numbers SEG #,
The 16th to 19th bits are the page number P #, and the 20th to 31st bits are undefined. General register G2 is the page descriptor PD
Is.

The general register G1 and the general register G2 are used to execute the RSTSD instruction. The format of general-purpose register G1 is STGSD
It is identical to the general purpose register G1 used by the instruction.

In the general-purpose register G2, the 0th to 7th bits are the reset mask RM, and the 8th and subsequent bits are undefined.

General-purpose registers G1, G1 + 1, G2 are used to execute the RSTPD instruction. The format of general-purpose registers G1 and G1 + 1 is STGPD
Identical to that used by the instruction. Also, the format of general register G2 is the same as that used by the RSTSD instruction.

Only general-purpose register G1 is used to execute the CLHRS instruction. The format of general register G1 is the same as general register G1 used by the STGSD instruction.

The general registers G1 and G1 + 1 are used to execute the CLHRP instruction. These formats are the same as those used by the STGPD instruction.

FIG. 4A is a flow chart for explaining the operation of the STGSD instruction and the STGPD instruction. First, process step 31
The type of the instruction is discriminated in step S31, and if the instruction is the STGSD instruction, the process moves to step 32. Process step 32 is STGSD
The absolute address W of the segment descriptor SD specified by the general register G1 in the instruction format is obtained. Then, in processing step 33, the contents of the general-purpose registers G2 and G2 + 1 in the same format as the STGSD instruction are stored in the 8-byte segment descriptor starting from the absolute address W on the main memory device 1.

On the other hand, if it is the STGPD instruction, the process proceeds to step 34. Processing step 34 uses general register G in the form of the STGPD instruction.
The absolute address W of the page descriptor PD specified by 1, G1 + 1 is obtained. Then, the processing step 35 is also the same as ST.
The contents of the general-purpose register G2 in the format of the GPD instruction are stored in the 4-byte page descriptor on the main memory device 1 starting from the absolute address W.

As described above, after executing the STGSD instruction or the STGPD instruction, the process proceeds to the processing step 36. Process step 36 is a process of storing history information, the details of which will be described later. A processing step 37 after the processing step 36 is processing for adding the instruction length 2 to the instruction counter IC.

FIG. 4B is a flow chart showing each operation of the RSTSD instruction, the RSTPD instruction, the CLHRS instruction, and the CLHRP instruction, and the procedure of the response between the plurality of CPUs. In FIG. 4 (b), processing step 41 and processing step 42 are for instructing and confirming a communication lock for exclusive communication between CPUs. Further processing step 43 and processing step 44
Is a communication instruction for temporarily stopping the execution of an instruction to another CPU (PAUSE), and confirms that another CPU has received the instruction.

The processing step 45 is a processing step for discriminating the type of the instruction, and when the instruction is the PSTSD instruction or the CLHRS instruction, the processing shifts from the processing step 45 to the processing step 46 to issue CLRSD communication to another CPU. The process at the time of reception by another CPU will be described later. Further, the processing step 47 discriminates the RSTSD instruction and the CLHRS instruction. When the instruction is the RSTSD instruction, the process moves from the processing step 47 to the processing step 48. On the other hand, when using the CLHRS instruction,
The processing shifts from the processing step 47 to the processing step 50.

Process step 48 determines the absolute address W of the segment descriptor SD specified by general register G1 in the form of a RSTSD instruction. Process step 49 indicates the absolute address W by ANDing the reset mask RM specified by general register G2 in the form of the RSSTSD instruction with the bit in the byte of the segment descriptor pointed to by absolute address W. Reset the bits in the byte.
Further processing step 50 clears from the TLB information about the segment specified by general register G1 in the form of an RSTSD instruction. The TLB is an address conversion buffer for converting a logical address to an absolute address at high speed. Similarly, processing step 50 clears from the TLB information about the segment specified by general register G1 in the form of a CLHRS instruction.

On the other hand, when the processing step 45 determines the RSTPD instruction or the CLHRO instruction, the processing shifts to the processing step 51 and the CPU is transferred to another CPU.
Issue LRPG communication.

Further, the processing step 52 determines the RSTPD instruction and the CLHRP instruction. If it is the RSTPD instruction, processing step 5
The processing shifts from 2 to processing step 53, and when the instruction is a CLHRP instruction, the processing shifts from processing step 52 to processing step 55.

The processing step 53 determines the absolute address W of the descriptor PD in the page designated by the general-purpose registers G1, G1 + 1 in the form of the RSTPD instruction. The processing step 54 depends on the absolute address W by ANDing the reset mask RM specified by the general register G2 in the form of the RSTPD instruction with the bit in the byte in the page descriptor pointed to by the absolute address W. Reset the bits in the indicated byte. In addition, process step 55 is RSTP
Clears from the TLB information about the page specified by general purpose registers G1, G1 + 1 in the form of the D instruction. Similarly, in process step 55, information about the page designated by the general-purpose registers G1, G1 + 1 in the CLHRP instruction format is cleared from the TLB.

As above, RSTSD instruction, RSTPD instruction, CLHRS instruction,
When either one of the CLHRP instruction and the CLHRP instruction is executed, the process proceeds to the processing step 56. Process step 56 is a process of storing history information.

The process step 57 is a process of confirming the end of the process based on the communication instruction corresponding to each instruction by another CPU. When this confirmation is obtained, the PAU of the other CPU is processed in processing step 58.
Issue a communication FREE to release the SE state. continue,
After confirming the reception of the FREE communication in processing step 59, the communication lock is released in processing step 60. Process step 61 is a process of adding the instruction length 2 to the instruction counter IC.

FIG. 4 (c) is a flow chart for explaining the operation of another CPU placed on the receiving side during communication.

The receiving CPU is the transmitting CPU described with reference to FIG.
It operates according to the communication instructions from.

The processing step 71 and the processing step 71a are processing responding to the processing step 43 of FIG. 4 (b). That is, receiving and responding to PAUSE communications is performed in these steps. Further, in processing step 72 to processing step 79, processing step 46 and processing step in FIG.
Receives and responds to the communication sent at 51.
First, processing step 72 determines the reception, and processing step 73 determines the communication instruction. That is, if the instruction is CLRSD communication, the processing moves to processing step 74, and if it is CLRPD communication, the processing moves to processing step 75.

In processing step 74, the information regarding the segment designated by CLRSD communication is cleared from the TLB. Similarly, in processing step 75, the information regarding the page designated by the CLRPD communication is cleared from the TLB.

When CLRSD communication or CLRPD communication is executed as described above, the process proceeds to processing step 76. Processing step
At 76, history information storage processing is executed. Processing step
At 77, the fact that the series of reception processing of the above communication is completed is reported to the transmitting side CPU. In subsequent processing step 78 and processing step 79, processing step 58 in FIG.
And a FREE communication corresponding to the processing step 59 is received and a response is executed.

FIG. 4 (d) shows the process step 36, 4th, in FIG. 4 (a).
Each history information storing process in the processing step 56 of FIG. 6B, the processing step 76 of FIG. 4C, and the processing step 76 of FIG. 4 is a flowchart illustrating the above. Fourth
In the processing step 81 in FIG. 2D, the content of the address 20H of the main memory device 1 in FIG. 2 is set to X ₀ . Subsequently, in process step 82, it is determined whether or not the arrangement of the 0th bit and the 1st bit of X ₀ is “10”. That is, the 0th bit of X ₀ is the trace mode bit,
When it is "1", it indicates that the history information is in the storage enabled state, and when it is "0", it indicates that the storage is in the storage inhibited state. The first bit is a logout display bit, and the fact that it is "0" indicates that the stored history information is not being logged out. During logout, registration of new history information is suppressed in order to fix the history information.

At processing step 83, X (FW stack pointer 4 in FIG.
In the address part of the CPU, that is, the start address of the FW stack area 5 generated from the second bit onward of X ₀ above, CPU # (C
The result of adding the product of the PU number, here CPU # = 0 to 3) and ¹⁴ , is obtained, and this is designated as Y.

That is, a main memory area of 2 ¹⁴ bytes is allocated to each CPU, and Y is the start address of the main memory area allocated to the CPU designated by CPU #.

In processing step 84, the result of adding the product of CPU # and "4" to X is obtained, and the contents of the main memory whose address is the result is given as Z. That is, CP in FIG.
In the pointer 10 that identifies U, the pointer of each CPU is 4
Since it has a byte area, Z is a pointer of the CPU designated by CPU #. Here, if Z is a relative address to the above Y, Y + Z is CP
The storage start address of the history information of the CPU designated by U # is designated.

In processing step 85, the instruction code and instruction of the history information to be stored (in the case of the instruction item CPU), or the communication (in the case of the communication / reception CPU), and the task name to which the corresponding instruction belongs are started from the above address Y + Z in 4 bytes. To store.

In processing step 86, 4 is added to Z, and in processing step 87, the contents of the instruction counter IC are started from the address Y + Z to 4
Store in bytes.

Subsequently, in processing step 88, 4 is again added to Z, and in processing step 89, the contents of the general-purpose register G1 are added to the address Y +.
Store in 4 bytes starting from Z.

Further, in processing step 90, 4 is added to Z, and in processing step 91, the contents of general-purpose register G1 + 1 are added to address Y.
Store in 4 bytes starting from + Z.

By the processing so far, one of the storage areas in FIG.
The information regarding the address translation information updating operation is stored as one piece of history information. Then process step 92
Then, 4 is added to the above Z, and in processing step 93 the Z is
Check if it equals 2 ¹⁴ . Therefore, since there is no more main memory area given to CPU♯ when the Z = 2 ^14, sets an initial value of 16 with respect to the processing steps 94 Z. As a result, the next history information is stored in the first storage area #.
Will be stored in 1.

On the other hand, when Z = ¹⁴ is not satisfied, the process proceeds to processing step 95. In processing step 95, Z is used as the CPU pointer designated by CPU #, and the storage address (X +
Store in CPU # 4). In this way, the history information regarding the address translation information updating operation can be sequentially stored separately for each CPU.

FIG. 5 is a flow chart for explaining the operation of the SVP command for updating the storage designation information.

In order to resolve the reference / update conflict at address 20H of the main memory device 23 with the processor other than the SVP executing this command, first, the processing steps 96, 97
Take the communication lock at. If the communication lock is successful,
Move to processing step 98.

At processing step 98, the contents of address 20H of the main memory device 23 including the trace mode bit and the logout during display bit are read out, and the logout during display bit is checked at processing step 99. If the logout in progress display bit is "1", the communication lock is released in processing step 100, the communication lock is returned to the state before the processing of this command, and the communication lock is acquired again. On the other hand, if the in-logout display bit is “0”, the command is discriminated in step 101. If the command is a command that sets the storage designation information to the history information storage permission state, the process proceeds to processing step 102, and if it is a command that also sets the history information storage inhibition state, processing step 10
Move to 3.

In processing step 102, the contents of address 20H of the main memory device 23 and "8000000" are set in order to set the trace mode bit to "1".
It is logically ORed with 0H ", and in processing step 103, in order to set the same bit to" 0 ", the contents of address 20H of main memory device 23 and" 7 "are set.
FFFFFFFH "and the logical product. Further, processing step 104
In, the result obtained as described above is stored in address 20H of the main memory device 23, and the trace mode bit in the main memory is updated.

In the processing step 105, the communication lock previously acquired is released and the processing ends. The SVP command is activated via the man-machine interface.

FIG. 6 is a flow chart for explaining the processing when an illegal exception occurs and the operation of the SVP 27, particularly the portion related to the present invention. As described in FIG. 1, in this embodiment, the SV
Since P controls the RAS function, the transfer control of the history information to the error log file is executed by SVP. The exception processing means is activated when an exception condition is detected during instruction execution, interrupt processing, or the like. Exception conditions include so-called functional exception conditions that can occur normally in software processing, such as missing page exceptions or floating-point data overflow exceptions, and illegalities that occur due to software processing errors such as memory infringement exceptions. There are exceptions. First, in process step 106, it is determined whether the detected exception condition is a functional exception condition or an illegal exception condition. In the case of the functional exception condition, the process proceeds to the process (omitted) for reporting the exception condition to the software as it is, and in the case of the illegal exception condition, the process proceeds to process step 107. In process steps 107 and 108, the communication lock is acquired as in the case of FIG. 5, and if the communication lock is successful, the process proceeds to process step 109. In process step 109, the contents of address 20H of main memory device 23 including the trace mode bit are read. Then, in processing step 110, in order to set the trace mode bit to "0", the contents of address 20H of the main memory device 23 and "7FFFFFFF" are set.
AND with H ".

Further, in processing step 111, the result of the logical product is stored in address 20H of the main memory device 23. In this way, the trace mode bit is set to "0" to set the history information storage suppression state, and then the process proceeds to step 112.

In the processing step 112, the inter-processor communication function is used for the logging of the history information by the SVP 27 to notify the SVP 27 of the occurrence of the illegal exception condition, and the processing step 113
Wait for the reply from SVP27.

When the reply from the SVP is received, the communication lock extracted from the above waiting is released and the communication lock previously acquired in the processing step 114 is released. After that, the process proceeds to report the exceptional condition to the software.

On the other hand, the SVP 27, which has received the notification of the occurrence of the illegal exception condition, first sets 20H of the main memory device 23 in process step 115 in order to set the logout in-progress bit of the main memory device 23 to “1”.
The contents of the address are read out, and in the processing step 116, the read data is ORed with "40000000H". Then, in processing step 117, the result of the logical sum is stored in the main memory device 23
Store at address 0H. This suppresses the subsequent update of the history information storage area, and the history information associated with the exception being processed can be frozen. Therefore, follow the processing steps
In 118, a reply is returned to the CPU that notified the illegal exception condition.

Next, in process step 119, the data in the memory area 64KB in which the history information is stored is transferred to the error log file based on the address information stored in the address 20H of the main memory device 23. When this transfer is completed, the in-logout display bit previously set in processing steps 120, 121, 122 is reset to "0", and all the operations are completed. In the above description, the memory area may be only the memory area corresponding to the valid CPU, but in order to simplify the control, the present embodiment adopts a method in which all areas for 4 CPUs are always targeted.

The history information stored in the SVP error log file as described above can be used as powerful information in investigating the cause of illegal exception conditions when it is printed out after the necessary edits. it can.

Although the number of CPUs has been described as four in this embodiment, it goes without saying that the number of CPUs can be easily set to m (m ≧ 1) in general.

(Effects of the Invention) As described above, according to the present invention, by sequentially storing the related information related to the execution of the address translation information update command as history information, a failure caused by complicated hardware, firmware, and software can be prevented. When it occurs, there is an effect that these history information can be read and the data effective for investigating the cause of the failure can be promptly provided.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing system showing an embodiment according to the present invention. FIG. 2 is a diagram for explaining the structures of the history information storage means defined on the main memory device and the storage designating means for designating whether or not the history information should be stored in the history information storage means. FIGS. 3A and 3B are diagrams for explaining the instruction format and the general-purpose register format, respectively. FIGS. 4A to 4D are flow charts for explaining the storage operation of the history information storage device. FIG. 5 is a flow chart for explaining the operation of the SVP command for updating the storage designation information. FIG. 6 is a flowchart explaining the operation of the SVP according to the present invention. 1, 23 ... Main memory device 2 ... Pointer area 3 ... FW work area 4 ... FW stack pointer 5 ... FW stack area 6-9 ... CPU area 10 ... Pointer 11 ... History information storage area 21, 22 ... Central processing unit 24 ... System controller 25, 26 ... Input / output processor 27 ... Supervisor processor 31-37, 41-61, 71-79, 81- 95, 96-122 ... Processing step

Claims (1)

[Claims] 1. At least one main memory device, and when the information is read from the main memory device or when the information is written to the main memory device, the logical address on the program is used to write the information based on the address conversion information. An address translation mechanism for translating an absolute address on a main memory device, an address translation buffer for speeding up address translation, one or more software instructions for updating the address translation information, and one or more for updating the address translation buffer. In an information processing system including a central processing unit having a software instruction and a supervisor processor, a history of storing a plurality of pieces of information related to execution of the software instruction in the main memory device as history information of execution of the software instruction The information storage means, and the history information storage means Storage designation means for designating a storage permission state for permitting storage of history information and a storage inhibition state for inhibiting storage; and in the central processing unit, the storage designation means is in the storage permission state when the software instruction is executed. Alternatively, a storage designation determining means for determining which one of the storage inhibition states is designated, and when the storage designation determining means determines that the storage permission state is designated, the history information is sequentially stored in the history information storage means. An illegal exception occurrence notifying means for notifying the supervisor processor of the illegal exception when the illegal exception occurs, and the history information in the supervisor processor in response to the notice of the illegal exception occurrence. Of the history information log for reading out from the history information storage means and storing it in the error log file of the supervisor processor. When the history information storage apparatus characterized by having a.