JPH0746321B2 - History information storage device - Google Patents

Description

The present invention relates to an information processing system having an address conversion unit, and in particular, a history information storage device for storing history information generated by updating address conversion information by software. Regarding

(Prior Art) In fields such as data processing and data communication, an information processing system including a computer is generally used. In recent years, such information processing systems have become increasingly complex, including increasingly sophisticated functions.

Therefore, it is often very difficult to investigate and analyze an illegal exception that has occurred during system operation and to find out the cause. In particular, a virtual memory system that requires address translation from a logical address on a program to an absolute address on a main memory device is executed because hardware, firmware, and software are complicatedly entangled and executed. It is even more difficult to find out the cause of the illegal exception. Furthermore, it is even more difficult in a multiprocessor system including a plurality of computer systems.

(Problems to be Solved by the Invention) The above-described conventional information processing system requires a great deal of man-hours and time to investigate and analyze the cause of such an illegal exception condition and measure the problem. There is a drawback that

It is an object of the present invention to eliminate the above-mentioned drawbacks by sequentially storing information relating to execution of a translation information update instruction for address translation, and reading it out when an illegal exception condition or the like occurs, to investigate the cause. It is an object of the present invention to provide a history information storage device configured so as to be able to perform quickly.

(Means for Solving Problems) A history information storage device of an information processing system according to the present invention is at least one main memory device, when reading information from the main memory device, or storing information in the main memory device. An address translation mechanism for performing translation into an absolute address on a program when writing, an address translation buffer for speeding up address translation, and one or more software instructions for updating the address translation information and an address translation buffer 1 In an information processing system including a central processing unit having one or more software instructions and a supervisor processor, information relating to execution of the software instructions in a main memory device (for example, instruction counter, instruction code, address conversion information) Address information and update data for updating History information storage means for storing a plurality of pieces of history information as execution history information of the software instructions, and the history information storage means by means of an instruction (either one instruction or two instructions) for updating the storage permission state and the storage inhibition state. A storage designation unit that designates a storage permission state that permits storage of the history information and a storage inhibition state that inhibits storage of the history information; and, in the central processing unit, the storage designation unit when executing the software instruction. Storage designation determining means for determining whether the storage permission state or the storage inhibition state is designated; and when the storage designation determination means determines that the storage permission state is designated, the history information is stored as the history information storage means. Storage means for sequentially storing the exceptions, and when the exception occurs, it is determined whether the exception is an illegal exception or a functional exception. Solve the conventional problems of the by having a history information storage device configured by a storage deterrent for updating designating means to the storage inhibited state can be reduced.

(Example) Next, a history information storage device according to the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a control structure in a main memory device which constitutes a part of a history information storage device according to the present invention. In FIG. 1, 1 is a main memory, 2 is a pointer area, 3 is a FW work area, 4 is a FW stack pointer, 5 is a FW stack area, 6-9 are CPU areas, 10 are pointers, and 11 is history information storage. Area. Main memory device 1 in FIG.
Includes a pointer area 2 and an FW (firmware: hereinafter referred to as FW) work area 3 according to this embodiment.

The pointer area 2 is provided with a 4-byte FW stack pointer 4 starting from the address 20H (hexadecimal number), for example. The FW stack pointer 4 has an address indicating the FW stack area 5 included in the FW work area 3, a trace mode bit (indicating whether history information is stored or not), and a logout display bit (stored history information is stored). Indicates whether or not you are logged out.)

The FW stack area 5 is composed of areas of the same capacity corresponding to each CPU (central processing unit having address conversion means for performing address conversion from a logical address to an absolute address, referred to as CPU in the following description). That is, these areas are the CPU # 0 area 6, the CPU # 1 area 7, the CPU # 2 area 8, and the # 3 area 9.

CPU # 0 area 6 the pointer 10 to identify the CPU, 2 ¹⁰ -1
And a history information storage area 11. History information storage area
11 indicates the type of executed instruction, the task name at the time of executing the instruction and the contents of the instruction counter (IC), the contents of general-purpose register G1,
And the contents of the general-purpose register G1 + 1 are stored.
The stored information will be described later.

CPU # 1 area 7, CPU # 2 area 8 and CPU # 3 area 9
Are also configured in exactly the same manner as the CPU # 0 area 6 described above.

FIG. 2A is a diagram for explaining the format of an instruction related to updating address translation information. In FIG. 2 (a), the instruction is
It consists of 16 bits, and each instruction has an 8-bit instruction code.
It has general-purpose register numbers G1 and G2 each consisting of 4 bits.

FIG. 2B is a diagram for explaining the format of the general-purpose register related to the address translation information update.

General-purpose registers G1, G2, and G2 + 1 are used to execute the STGSD instruction. The general-purpose register G1 includes a segment number SEG # of 0th to 15th bits and a task name of 16th to 31st bits.
General register G2 is the first word of segment descriptor SD, and similarly general register G2 + 1 is the second word of segment descriptor SD.

General registers G1, G1 + 1, and G2 are used to execute the STGPD instruction. In the general register G1, the 0th to 15th bits are undefined, and the 16th to 31st bits are the task name. General-purpose register G1
For the contents of +1, the 0th to 15th bits are the segment number SEG #,
The 16th to 19th bits are the page number P #, and the 20th to 31st bits are undefined. General register G2 is the page descriptor PD
Is.

The general register G1 and the general register G2 are used to execute the RSTSD instruction. The format of general-purpose register G1 is STGSD
It is identical to the general purpose register G1 used by the instruction.

In the general-purpose register G2, the 0th to 7th bits are the reset mask RM, and the 8th and subsequent bits are undefined.

General-purpose registers G1, G1 + 1, G2 are used to execute the RSTPD instruction. The format of general-purpose registers G1 and G + 1 is STGPD.
Identical to that used by the instruction. Also, the format of general register G2 is the same as that used by the RSTSD instruction.

Only general-purpose register G1 is used to execute the CLHRS instruction. The format of general register G1 is the same as general register G1 used by the STGSD instruction.

The general registers G1 and G1 + 1 are used to execute the CLHRP instruction. These formats are the same as those used by the STGPD instruction.

FIG. 3A is a flow chart for explaining the operation of the STGSD instruction and the STGPD instruction. First, process step 31
The type of the instruction is discriminated in step S31, and if the instruction is the STGSD instruction, the process moves to step 32. Process step 32 is STGSD
The absolute address W of the segment descriptor SD specified by the general register G1 in the instruction format is obtained. Then, in process step 38, the contents of the general-purpose registers G2 and G2 + 1 in the same format as the STGSD instruction are stored in the 8-byte segment descriptor on the main memory device 1 starting from the absolute address W.

On the other hand, if it is the STGPD instruction, the process proceeds to step 34. Processing step 34 is a general-purpose register G in the format of the STGPD instruction.
The absolute address W of the page descriptor PD specified by 1, G1 + 1 is obtained. Then, step 35 is the same as STGP.
The contents of the general-purpose register G2 in the format of the D instruction are stored in the 4-byte page descriptor on the main memory device 1 starting from the absolute address W.

After executing the STGSD instruction or the STGPD instruction as described above, the process proceeds to the processing step 36. Process step 36 is a process of storing history information, the details of which will be described later. A processing step 37 after the processing step 36 is processing for adding the instruction length 2 to the instruction counter IC.

FIG. 3B is a flow chart showing each operation of the RSTSD instruction, the RSTPD instruction, the CLHRS instruction, and the CLHRP instruction and the procedure of the response between the plurality of CPUs. In FIG. 3B, processing step 41 and processing step 42 are for instructing and confirming a communication lock for exclusive communication between CPUs. Further processing step 43 and processing step 44
Is a communication instruction for temporarily stopping the execution of an instruction to another CPU (PAUSE), and confirms that another CPU has received the instruction.

The processing step 45 is a processing step for discriminating the type of the instruction, and when the instruction is the PSTSD instruction or the CLHRS instruction, the processing shifts from the processing step 45 to the processing step 46 to issue CLRSD communication to another CPU. The process at the time of reception by another CPU will be described later. Further, the processing step 47 discriminates the RSTSD instruction and the CLHRS instruction.

When the instruction is the RSTSD instruction, the process moves from the processing step 47 to the processing step 48. On the other hand, when it is the CLHRS instruction, the process moves from the processing step 47 to the processing step 50.

Process step 48 determines the absolute address W of the segment descriptor SD specified by general register G1 in the form of a RSTSD instruction. The processing step 49 is the byte indicated by the absolute address W by logically ANDing the reset mask RM specified by the general register G2 in the form of the RSTSD instruction with the bit in the byte of the segment descriptor indicated by the absolute address W. Reset the bits in.

Further processing step 50 clears from the TLB information about the segment specified by general register G1 in the form of an RSTSD instruction. The TLB is an address conversion buffer for converting a logical address to an absolute address at high speed. Similarly, processing step 50 clears from the TLB information about the segment specified by general register G1 in the form of a CLHRS instruction.

On the other hand, when the processing step 45 determines the RSTPD instruction or the CLHRP instruction, the processing proceeds to the processing step 51 and the CPU is transferred to the other CPU.
Issue LRPG communication.

Further, the processing step 52 determines the RSTPD instruction and the CLHRP instruction. If it is the RSTPD instruction, processing step 5
The processing shifts from 2 to processing step 53, and when the instruction is a CLHRP instruction, the processing shifts from processing step 52 to processing step 55.

The processing step 53 determines the absolute address W of the descriptor PD in the page designated by the general-purpose registers G1, G1 + 1 in the form of the RSTPD instruction. The processing step 54 depends on the absolute address W by ANDing the reset mask RM specified by the general register G2 in the form of the RSTPD instruction with the bit in the byte in the page descriptor pointed to by the absolute address W. Resets the bits in the specified byte. Further processing step 55 is RSTPD
Clears from the TLB information about the page specified by general purpose registers G1, G1 + 1 in the instruction format. Similarly, in process step 55, information about the page designated by the general-purpose registers G1, G1 + 1 in the CLHRP instruction format is cleared from the TLB.

As above, RSTSD instruction, RSTPD instruction, CLHRS instruction,
When either one of the CLHRP instruction and the CLHRP instruction is executed, the process proceeds to the processing step 56. Processing step 56 is an operation of storing history information.

The process step 57 is a process of confirming the end of the process based on the communication instruction corresponding to each instruction by another CPU. When this confirmation is obtained, the PAU of the other CPU is processed in processing step 58.
Issue a communication FREE to release the SE state. continue,
After confirming the reception of the FREE communication in processing step 59, the communication lock is released in processing step 60. Process step 61 is a process of adding the instruction length 2 to the instruction counter IC.

FIG. 3C is a flow chart for explaining the operation of another CPU placed on the receiving side during communication. The receiving CPU operates according to the communication instruction from the transmitting CPU described with reference to FIG.

The processing step 71 and the processing step 71a are processing responding to the processing step 43 of FIG. 3 (b). That is, receiving and responding to PAUSE communications is performed in these steps. Further, in processing step 72 to processing step 79, processing step 46 and processing step in FIG.
Receives and responds to the communication sent at 51.
First, the processing step 72 discriminates the reception, and the processing step 73 discriminates the communication instruction. That is, if the instruction is CLRSD communication, the processing moves to processing step 74, and if it is CLRPD communication, the processing moves to processing step 75.

In processing step 74, the information regarding the segment designated by CLRSD communication is cleared from the TLB. Similarly, in processing step 75, the information regarding the page designated by the CLRPD communication is cleared from the TLB.

When CLRSD communication or CLRPD communication is executed as described above, the process proceeds to processing step 76. Processing step
At 76, history information storage processing is executed. Processing step
At 77, the fact that the series of reception processing of the above communication is completed is reported to the transmitting side CPU. In the subsequent processing steps 78 and 79, the processing step 58 of FIG.
And a FREE communication corresponding to the processing step 59 is received and a response is executed.

FIG. 3 (d) shows the processing step 36, the third of FIG. 3 (a).
7 is a flowchart illustrating each history storage process in process step 56 of FIG. (B) and process step 76 of FIG. 3 (c), that is, a process of storing history information regarding address translation information update. In the processing step 81 in FIG.
The content of the address 20H of the main memory device 1 in the figure is X ₀ . Subsequently, in process step 82, it is determined whether or not the arrangement of the 0th bit and the 1st bit of X ₀ is “10”. That is, the 0th bit of X ₀ is a trace mode bit, and when it is “1”, it indicates that the history information is in the storage enabled state, and when it is “0”, it indicates the storage inhibited state. The first bit is a logout display bit, and the fact that it is "0" indicates that the stored history information is not being logged out. During logout, registration of new history information is suppressed in order to fix the history information.

In processing step 83, CPU # is set to X (the address part of the FW stack pointer 4 in FIG. 1, that is, the start address of the FW stack area 5 generated from the second and subsequent bits of X ₀ ).
The result of adding the products of (CPU number, here CPU # = 0 to 3) and 2 ¹⁴ is obtained, and this is designated as Y. That is, each CPU
Is allocated a main memory area of 2 ¹⁴ bytes, and Y is the start address of the main memory area allocated to the CPU designated by CPU #.

In processing step 84, the result of adding the product of CPU # and "4" to X is obtained, and the contents of the main memory whose address is the result is given as Z. That is, CP in FIG.
In the pointer 10 that identifies U, the pointer of each CPU is 4
Since it has an area of bytes, Z is a pointer of the CPU designated by CPU #. Here, if Z is a relative address to the above Y, Y + Z is CP
The storage start address of the history information of the CPU specified by U # will be specified.

In processing step 85, the instruction code and instruction (in the case of the instruction executing CPU) of the history information to be stored, or the communication (in the case of the receiving CPU of the communication), and the task name to which the corresponding instruction belongs are started from the address Y + Z in 4 bytes. To store.

In processing step 86, 4 is added to Z, and in processing step 87, the contents of the instruction counter IC are started from the address Y + Z to 4
Store in bytes.

Subsequently, in processing step 88, 4 is again added to Z, and in processing step 89, the contents of the general-purpose register G1 are added to the address Y +.
Store in 4 bytes starting from Z.

Further, in processing step 90, 4 is added to Z, and in processing step 91, the contents of general-purpose register G1 + 1 are added to address Y.
Store in 4 bytes starting from + Z.

According to the processing so far, one of the storage areas in FIG.
The information regarding the address translation information updating operation is stored as one piece of history information. Then process step 92
Then, 4 is added to the above Z, and in processing step 93 the Z is
Check if it equals 2 ¹⁴ . Therefore, when Z = 2 ¹⁴ because there is no more main memory area given to CPU #, it sets an initial value of 16 with respect to the processing steps 94 Z. As a result, the next history information is stored in the first storage area #
Will be stored in 1.

On the other hand, when Z = 2 ¹⁴ is not satisfied, the routine proceeds to processing step 95. In processing step 95, Z is used as the pointer of the CPU designated by CPU #, and the storage address (X
Store in + CPU # ・ 4). In this way, the history information regarding the address translation information updating operation can be sequentially stored separately for each CPU.

FIG. 4 is a flow chart for explaining the operation of the instruction for updating the designated information given as the trace mode bit in order to designate whether or not the update information for updating the address translation information should be stored as the history information. .

In order to resolve the reference / update conflict at address 20H of the main memory between the CPU executing the instruction and the other CPUs, first take the communication lock in processing steps 96 and 97. . If the communication lock is successful, the process proceeds to processing step 98.

In process step 98, the contents of 4 bytes at address 20H of the main memory device including the trace mode bit are read. In the processing step 99, the execution instruction is judged, and if the instruction is an instruction to put the specified information into the history information storage permission state, the process proceeds to processing step 100, and if it is an instruction to put in the history information storage inhibition state, the processing step 101. Go to.

In processing step 100, the contents of address 20H of the main memory device and "80000000" are set in order to set the trace mode bit to "1".
The logical sum of "H" and "7FF" is set in processing step 101 in order to set the same bit to "0".
FFFFFH "and the logical product with FFFFFH". Further, in processing step 102, the result obtained as described above is stored in the main memory device.
Store in address 20H and update the trace mode bit in the main memory.

In processing step 103, the communication lock previously taken is released, and in processing step 104, the instruction length is added to the instruction counter IC so as to instruct the next instruction, and the IC is updated.

FIG. 5 is a flow chart for explaining the operation of the part of the exception handling means, which is particularly relevant to the present invention. The exception processing means is activated when an exception condition is detected during instruction execution, interrupt processing, or the like. Exception conditions include missing page exceptions or floating point data overflow exceptions,
In the first processing step 105, there is a so-called functional exception condition that can occur normally in software processing, and an illegal exception that occurs due to an error in software processing such as a memory protection violation exception. Is a functional exception condition or an illegal exception condition. In the case of a functional exception condition, a process for reporting the above exception condition to the software as it is (omitted)
If the condition is an illegal exception condition, the process proceeds to step 106. In process steps 106 and 107, the communication lock is acquired as in the case of FIG. 4, and if the communication lock is successful, the process proceeds to process step 108. In process step 108, the contents of address 20H of the main memory device including the trace mode bit are read. Then, in processing step 109, in order to set the trace mode bit to "0", the logical product of the contents of address 20H of the main memory device and "7FFFFFFFH" is taken.

Further, in processing step 110, the result of the logical product is stored in address 20H of the main memory device. In this way, after setting the trace mode bit to "0" to set the history information storage suppression state, the process proceeds to the process for reporting the previously detected exception condition to the software.

In this way, when an illegal exception condition occurs, the history information storage operation thereafter is suppressed, whereby history information related to the execution of the address translation information update instruction that has been stored until then is established, and the illegal exception condition processing is performed. The history information is handed over to the software processing of or the processing of extracting the information by the debug tool. Further, after collecting the history information, if necessary, the history information storing operation can be started by a command for setting the designated information described in FIG. 4 into the history information storing permission state.

Although the number of CPUs has been described as four in this embodiment, it goes without saying that the number of CPUs can be easily set to m (m ≧ 1) in general.

(Effects of the Invention) As described above, according to the present invention, by sequentially storing the related information related to the execution of the address translation information update command as history information, a failure caused by complicated hardware, firmware, and software can be prevented. When it occurs, there is an effect that these history information can be read and data effective for investigating the cause of the exceptional condition can be promptly provided.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the structures of history information storage means defined on the main memory device and storage designation means for designating whether or not history information should be stored in the history information storage means. FIGS. 2A and 2B are diagrams for explaining the instruction format and the general-purpose register format, respectively. FIGS. 3A to 3D are flow charts for explaining the storage operation of the history information storage device. FIG. 4 is a flow chart for explaining the operation of updating the storage designating means. FIG. 5 is a flow chart for explaining the operation of the exception handling means according to the present invention. 1 ... Main memory device 2 ... Pointer area 3 ... FW work area 4 ... FW stack pointer 5 ... FW stack area 6-9 ... CPU area 10 ... Pointer 11 ... History information storage area 31-37 , 41〜61,71〜79,81〜95,96〜110 …… Processing steps

Claims (1)

[Claims] 1. At least one main memory device, and when the information is read from the main memory device or when the information is written to the main memory device, the logical address on the program is used to write the information based on the address conversion information. An address translation mechanism for translating an absolute address on a main memory device, an address translation buffer for speeding up address translation, one or more software instructions for updating the address translation information, and one or more for updating the address translation buffer. In an information processing system including a central processing unit having a software instruction and a supervisor processor, history information for storing a plurality of pieces of information related to execution of the software instruction in a main memory device as history information of execution of the software instruction. Means of storage, memory enabled state and memory inhibited state A new instruction (may be either one instruction or two instructions) designates a storage permission state in which the history information storage means is permitted to store the history information and a storage inhibition state in which the storage is inhibited. Storage designation means, a storage designation determination means in the central processing unit for determining whether the storage instruction means designates a storage permission state or a storage inhibition state when the software instruction is executed, and the storage designation means Storage means for sequentially storing the history information in the history information storage means when the determination means determines that the storage permission state is designated, and whether the exception is an illegal exception or a function exception when an exception occurs. And a memory inhibiting means for updating the memory designating means to the memory inhibiting state when it is determined that the illegal exception has occurred.