JPH0746494B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and particularly to 0 from an arbitrary address.
The present invention relates to a dynamic serial memory device having a read reset function to an address.

(Prior Art) A serial storage device (hereinafter referred to as a serial memory) is a memory that is being rapidly developed with the development of digital processing technology for video signals. In other words, since the input / output format of this memory, which enables serial writing and reading asynchronously, is extremely suitable for digital processing of video signals, it is actively used in this technical field today.

Currently developed memory structures of this type usually consist of a matrix storage plane of semiconductor storage cells. Here, the external data is sequentially bit by bit in the memory cells arranged one by one from the address 0 in the first row and the first column to the final address in the last row and the last column attached to each intersection of this matrix. It is sequentially written according to the order of the array addresses and is immediately read out in this order. Therefore, when one data is composed of 7 to 11 bits like a digital code signal of a video signal, the same number of matrix storage planes as the number of bits are prepared.

By the way, in order to serially read the written external data from this storage plane, first, the respective address write data in the first row are read at once and then sequentially output in the column number order. While this read operation is being performed, the next data is written in each address storage cell of the second row, and when the read preparation is completed, the same operation is continued to read each address of the second row. Be done. External data is sequentially written and read in this manner in the address storage cells up to the final end row and the end column in this manner sequentially according to the control system of the storage device.

At this time, a static semiconductor memory cell is usually used for each address memory cell, but a dynamic semiconductor memory cell is used for the purpose of configuring a large capacity memory.
However, since a dynamic semiconductor memory cell generally has a slower reading speed than a writing speed, when a memory cell of this type is used, the speed is increased by using a special read control means usually called a preceding read method. . That is, all addresses are divided into two blocks and accommodated in respective storage planes, and while one row of one block is being read, one row of the other block is prepared for reading. The method of leaving is adopted. Using this read-ahead method apparently eliminates the delay in the read speed of the dynamic semiconductor memory cell, so that a high-speed, large-capacity dynamic serial memory having a constant delay bite number can be realized.

(Problems to be solved by the invention) In a normal use state, the entire memory plane is activated and 0
Writing and reading from the address to the final address are repeatedly executed. However, it is often the case that only a partial area of the storage plane should be used for this serial memory. For example, a case where another video signal is inserted into a part of one video signal and a small screen is simultaneously displayed on the television receiving surface corresponds to this. In such a case, since the serial memory on the video signal side to be inserted is limitedly used only in a partial area of the storage plane, unlike the usual case, writing and reading from address 0 to any address are repeated. Must be carried out. In other words, it is required to have a read reset function capable of quickly returning from an arbitrary address whose required time and location cannot be specified to address 0.

However, even if all the address storage cells are formed of static cells, or if all the addresses including rabbits and addresses 0 are formed of dynamic cells, the provisional read-ahead method may be used. A strict reset function cannot be added. The reason is that a reset request from an arbitrary address to address 0 occurs at an indefinite time, as is apparent even when considering a scene of inserting a small screen on the television receiving surface. Therefore, when this reset request occurs, the pre-reading preparation operation for the memory cells after an arbitrary designated address is completely invalid, but the first address including the 0th address to be read urgently
A situation occurs that the read-out preparation is not performed at all for the memory cells in the row. As a result, the read-ahead method of bending cannot exert an effect on the writing and reading of the first line including the address 0, and a significant access delay occurs, so that the address quickly returns to the address 0. It is essentially impossible to realize the read reset function.

(Purpose of the Invention) In view of the above-mentioned cleanliness, the purpose of the present invention is 0 from any address.
It is an object of the present invention to provide a semiconductor memory device having a dynamic serial memory structure having a read reset function capable of quickly returning to an address.

(Structure of the Invention) In the semiconductor memory device of the present invention, the data write memory plane for serially writing and reading the data to be written occupies the static memory cell array of a partial area including address 0 and the remaining address area. It is composed of a hybrid matrix with a dynamic memory cell array of a read-ahead readiness configuration, and the dynamic memory cell array is gate-controlled by a logical product output of a write transistor, a sensing transistor, a read transistor and a write selection signal and a write pointer signal. And a three-transistor dynamic memory cell including a write-transistor drive control means.

(Means for Solving the Problem) That is, according to the present invention, the static memory cells are arranged at at least the address of the first row including the address 0, and all the remaining addresses do not have the refresh function. Dynamic storage cells of a three-transistor configuration are arranged by the read-ahead method, including write transistor drive control means for outputting a logical product of a write selection signal and a write pointer signal.

(Operation) In this way, if the addresses are arranged in a hybrid matrix with different types of memory cells, the static cell read function will not be affected even if a read reset request from any address to address 0 is unexpectedly generated. It is possible to promptly output write data at addresses 0 and below without delaying access. At this time, in the dynamic cell area, the read-ahead preparation for the memory cells after an arbitrary designated address is completely invalid as in the conventional case, but during the reading of the first row including the address 0 by the static cell is performed. Since the writing for the second row and the subsequent rows and the preparation for the preceding reading are sequentially completed again, the normal serial memory operation can be immediately started. Here, the dynamic memory cell having a three-transistor structure is provided with write transistor drive control means for operating the write transistor only when the write selection signal and the write pointer signal are simultaneously input, while writing to the subsequent address is being performed. Since the write operation of itself is prohibited, it is possible to prevent the destruction of the preceding data that occurs when writing the subsequent address. Further, since this memory cell does not have a refresh function but can operate as a non-destructive memory having a memory holding capacity of about 1 ms, it can sufficiently function as a dynamic memory plane. Hereinafter, the present invention will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 and FIG. 2 are a configuration diagram of a data write storage plane and a connection circuit diagram of its dynamic storage cell array, respectively, showing an embodiment of the present invention.

According to the present embodiment, the data write storage plane 100 is composed of the storage plane 10 consisting of the static storage cell array from address 0 to address a, and the addresses (a + 1) to b and (b + 1) to c respectively. Storage planes 20 and 30 are comprised of a three-transistor dynamic storage cell array divided into two blocks as rows. Here, k indicates the final address, and the read-ahead method is applied to all the dynamic memory cells as in the conventional case. The three-transistor dynamic memory cell has input terminals for the write transistor Q ₁ , the sense transistor Q ₂ , the read transistor Q _{3, the} write selection line 3 and the write pointer signal lines 5 and 6, and the gate electrode of the write transistor. And an AND circuit 7 for connecting output terminals to each other, and are connected as shown in FIG. Here, 1 and 2 are write and read digit lines, 4 and 8 are read select lines and write data buses, and Q ₀ is a write load transistor.

Although this memory cell does not have a refresh circuit, its write / read operation is exactly the same as a normal three-transistor dynamic memory cell. That is, each storage cell connected to one selected write selection line 3 fetches external data into the sense transistor Q ₂ via the write transistor Q ₁ when the respective write digit line 1 is selected,
Further, when the read selection line 4 and the read digit line 2 are simultaneously selected, the external data taken in is output to the selected read digit line 2 via the read transistor Q ₃ .

Here, each of the write digit lines 1 is selectively driven by each pointer signal of the write pointer signal lines 5 and 6, and each of the write transistors Q ₁ outputs a logical product of the write selection signal and the pointer signal. Is selectively driven by. Therefore, when the memory cells in the upper row are selected for writing, external data is written from the write data bus 8 to the writing line cell A when the pointer signal from the writing pointer signal line 5 arrives. Writing to the memory cell B is performed with the arrival of the pointer signal from the signal line 6.
At this time, the write transistor Q _{1 of} each of the wiring cells A 1 and B ₂
Since operating independently from each other selected drive through the AND circuit 7, the memory write operation of the subsequent address storage cell B cell A is
The preceding data held by will not be destroyed. Also,
The memory cells C 1 and D 2 in the lower row can be serially written independently by the same procedure. Therefore, according to this memory cell, the dynamic memory planes 10 and 20 can be easily constructed by effectively utilizing the memory holding function of about 1 mS and the read-ahead method.

Although only the storage plane for 1 bit is shown in this embodiment, this is sufficient for understanding the write / read operation.
That is, since one data is all written in the same address, no matter how many bits this data consists of, the leading input data is all stored in the address 0 memory cell in FIG.
Next, the input data is stored in the memory cell at address 1 and further (k +
It is safe to consider that the 1) th input data is serially written in the k-th memory cell.

For serial memory, the final k in normal use
When an arbitrary read reset is applied from the address, for example, from address i, the process returns to the reading of address 0 data as indicated by the arrows. However, since the storage plane 100 is made up of different types of storage cells and the storage plane 10 including at least the first row from address 0 to address a is all made up of static storage cells, the dynamic storage plane
Regardless of which address 20 or 30 the read reset is unexpectedly performed, a part of the write data below the address 0 is immediately output without access delay. Further, while the read operation is being performed, the read preparation of the dynamic storage plane is successively prepared, so that the serial memory operation can be continued without causing an access delay. Although the storage plane 10 is independent in the above description, the storage plane 20 is practically used.
It is preferable to form the independent region on the substrate.

(Effects of the Invention) As described in detail above, according to the present invention, at least each address in the first row including the address 0 is formed of a static memory cell, and write data can be immediately read out together with input of read access. Since it is in a state of being ready, it is possible to easily provide a read reset function capable of quickly returning from any address to address 0. Further, since the dynamic cell region occupying most of the storage plane is composed of the three-transistor storage cell having a simple structure, not only the occupied area of the memory can be greatly reduced but also the number of digit lines is reduced. Since the structure of the control system for the read-ahead preparation is simplified, the read speed can be improved and the reliability can be further enhanced.

[Brief description of drawings]

1 and 2 are a block diagram of a data write plane and a connection circuit diagram of its dynamic memory cell array showing an embodiment of the present invention, respectively. 100 ... data write storage plane, 10 ... static storage cell array storage plane, 20 , 30 ... 3-transistor dynamic storage cell array storage plane, 1 ... write digit line, 2 ... read digit line 3 ... Write selection line, 4
...... Read selection line, 5,6 …… Write pointer signal line, 7 ……
AND circuit, 8 ... Write data bus, A , B , C , D
...... 3-transistor dynamic memory cell, Q ₁ …… Write transistor, Q ₂ …… Sensing transistor, Q ₃ ……
Read transistor, Q ₀ ... write load transistor.

 ─────────────────────────────────────────────────── --- Continuation of front page (72) Inventor Hiroaki Ikeda 5-7-15 Shiba, Minato-ku, Tokyo NEC Electric microcomputer system Co., Ltd. (56) Reference JP-A-51-47328 (JP, A) JP-A-53-123627 (JP, A) JP-A-58-23373 (JP, A) JP-A-48-9641 (JP, A)

Claims (1)

[Claims] 1. A data storage cell plane for serially writing and reading data to be written and a static storage cell array of a partial area including address 0 and a dynamic storage cell of a read-ahead read-out configuration occupying the remaining address area. The dynamic memory cell array comprises a write transistor sensing transistor, a read transistor, and write transistor drive control means for performing gate control by a logical product output of a write selection signal and a write pointer signal. A semiconductor memory device, each of which is configured by a 3-transistor dynamic memory cell including the same.