JPH0814982B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic serial memory device having a read reset function from an arbitrary address to an address 0.

(Prior Art) A serial storage device (hereinafter referred to as a serial memory) is a memory that is being rapidly developed with the development of digital processing technology for video signals. In other words, since the input / output format of this memory, which enables serial writing and reading asynchronously, is extremely suitable for digital processing of video signals, it is actively used in this technical field today.

Currently developed memory structures of this type usually consist of a matrix storage plane of semiconductor storage cells. Here, the external data is sequentially arranged in the memory cells arranged one by one from the address 0 in the first row and the first column to the final address in the last row and the last column attached to each intersection of this matrix. It is sequentially written according to the order of the array addresses and is immediately read out in this order. Therefore, when one data is composed of 7 to 11 bits like a digital code signal of a video signal, the same number of matrix storage planes as the number of bits are prepared.

By the way, in order to serially read the written external data from this storage plane, first, the respective address write data in the first row are read at once and then sequentially output in the column number order.
While this read operation is being performed, the next data is written in each address memory cell on the second row, and when the read preparation is completed, the same operation is continued to read each address on the second row. Be done. External data is sequentially written and read in this manner in the address storage cells up to the final end row and the end column in this manner sequentially according to the control system of the storage device.

At this time, a static semiconductor memory cell is usually used for each address memory cell, but a dynamic semiconductor memory cell is used for the purpose of configuring a large capacity memory. However, since a dynamic semiconductor memory cell generally has a slower reading speed than a writing speed, when a memory cell of this type is used, the speed is usually increased by using a special read control means called a preceding read method. . That is, all addresses are divided into two blocks and accommodated in respective storage planes, and while one row of one block is being read, one row of the other block is prepared for reading. The method of leaving is adopted. Using this read-ahead method apparently eliminates the delay in the read speed of the dynamic semiconductor memory cell, so that a high-speed and large-capacity dynamic serial memory having a constant delay bit number can be realized.

(Problems to be Solved by the Invention) In a normal use state, the entire storage plane is activated, and writing and reading from address 0 to the final address are repeatedly executed. However, it is often the case that only a partial area of the storage plane should be used for this serial memory. For example, a case where another video signal is inserted into a part of one video signal and a small screen is simultaneously displayed on the television receiving surface corresponds to this. In such a case, the serial memory on the video signal side to be inserted is limited to a partial area of the storage plane, so that 0 is different from the normal case.
Writing and reading from an address to an arbitrary address must be repeatedly executed. In other words, it is required to have a read reset function capable of quickly returning from an arbitrary address whose required time and location cannot be specified to address 0.

However, each address storage cell is static
If all of the cells including the rabbit corner and the address 0 are formed by dynamic cells if they are formed by cells, even if the provisional read-ahead method is adopted, it is not possible to add such a strict reset function. Can not. The reason is that a reset request from an arbitrary address to address 0 occurs at an indefinite time, as is apparent even when considering a scene of inserting a small screen on the television receiving surface. Therefore, when this reset request occurs, the pre-reading preparation operation for the memory cells after the arbitrary designated address is completely invalid, but for the memory cell on the first row including the 0th address to be urgently read. The situation occurs that the read-ahead preparation is not performed at all. As a result, the leading read method of the corner cannot be effective for the writing and reading of the first row including the address 0, and a significant access delay occurs, and the address can be quickly returned to the address 0. Realization of the read reset function is essentially impossible.

(Object of the Invention) In view of the above situation, an object of the present invention is to provide a semiconductor memory device having a dynamic serial memory configuration having a read reset function capable of quickly returning from any address to address 0. .

(Means for Solving Problems) A semiconductor device of the present invention is a semiconductor memory device having a plurality of consecutive addresses and serially reading data in the order of consecutive addresses, and a predetermined address from a top address. A first region corresponding to consecutive addresses up to and a second region corresponding to another address following the predetermined address, wherein the memory cells in the first region are static memory cells, The memory cells in the second area are dynamic memory cells.

(Operation) In this way, if each address is formed in a hybrid matrix with different types of memory cells, 0
Even if the read reset request to the address is unexpectedly generated, the read function of the static cell can quickly respond and immediately output the write data at addresses 0 and below without causing access delay. At this time, in the dynamic cell area, the read-ahead preparation for memory cells after an arbitrary designated address is completely invalid as in the conventional case, but the static cell is set to 0.
While the first line including the address is being read out, the second
Since the writing for the rows and below and the preparation for the read-ahead are successively completed again, it is possible to immediately shift to the normal serial memory operation.
Hereinafter, the present invention will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 and FIG. 2 are a configuration diagram of a data write storage plane and a connection circuit diagram of its dynamic storage cell array, respectively, showing an embodiment of the present invention.

According to this embodiment, the data write storage plane 100 is a storage plane 10 consisting of a static storage cell array from address 0 to address a, and addresses (a + 1) to b and (b +).
1) Includes storage planes 20 and 30 each consisting of a three-transistor dynamic storage array divided into two blocks, starting from addresses c to c, where k is the final address. The read-ahead method is applied to all the dynamic memory cells as in the conventional case. This 3-transistor dynamic memory cell is a write transistor
Q _1, sensing transistors Q _2, is the circuit connected as FIG. 2 is constituted respectively comprise an inverter N is inserted between the read transistors Q ₃ and write digit lines 1 and read digit line 2. Here, 3 and 4 are write select lines and read select lines, 5, 6 and 7 are write pointer potential lines and write data buses, respectively, and Q ₀ is a write load transistor.

Although this memory cell does not have a refresh circuit, its write / read operation is exactly the same as a normal three-transistor dynamic memory cell. That is, each storage cell connected to one selected write selection line 3 fetches external data into the sense transistor Q ₂ via the write transistor Q ₁ when the respective write digit line 1 is selected, Further, the external data in the sense transistor Q _{2 taken} in when the read selection line 4 and the read digit line 2 are simultaneously selected are output through the read transistor Q ₃ . Write digit line 1 is selectively driven by each pointer potential input to write pointer potential lines 5 and 6. That is, when each storage cell in the upper stage is selected, the write data is written in the storage cell A by the pointer potential of the write pointer potential line 5 and in the storage cell B by the pointer potential of the write pointer potential line 6. External data is serially written from the bus 7 via the write load transistor Q ₀ . In addition, the memory cells C and D in the lower stage
With respect to, all writing is performed serially by the same procedure. However, when writing to the memory cell B or D, the potential of the read digit line 2 on the memory cell A or C side is raised before the potential of the respective write select line 3 is raised to temporarily read the stored data. Inverter N
Must be made to re-populate at that level of inversion via. By this rewriting operation, the memory cell A
Alternatively, the preceding write data stored in C is not destroyed and the rest is protected. Therefore, the dynamic storage cell having such a configuration temporarily occupies the read digit line even during writing, and therefore reading is prohibited during writing. This write / read characteristic causes a slight delay in access when there is a read reset request from a relatively young address to the 0th address, but normally such a request is extremely rare, so there is no practical problem. , It is possible to easily construct a dynamic cell storage plane with a very small read access delay by effectively utilizing the storage retention time of about 1 ms and the read-ahead method.

This is sufficient to understand the write / read operation, where only the storage plane for one bit is shown in this embodiment.
That is, since one data is all written in the same address, no matter how many bits this data consists of, the leading input data is all stored in the address 0 memory cell in FIG.
It does not matter if it is considered that the next input data is serially written in the address 1 storage cell and the kth input data is serially written in the address k storage cell.

In the normal use state, the operation returns from the last address k, and when the read reset is applied at an arbitrary time, for example, from address i to read the address 0 write data as indicated by arrows. However, since the memory plane 100 is composed of memory cells of different types and the memory plane 10 including at least the first row from address 0 to address a is composed of all static cells, the dynamic memory planes 20 and 30 are Regardless of the address from which the reset is unexpectedly performed, the write data of the addresses 0 and below are output promptly. Further, while the read operation is being performed, the read preparations for the dynamic storage plane are all completed, so that the serial memory operation can be continued without causing an access delay.

Although the storage plane 10 is independent in the above description, it is usually formed in the storage plane 20 in practical use.

(Effect of the Invention) As described in detail above, according to the present invention, at least the first row from address 0 to address a is made up of static memory cells, and write data can be immediately read out at the same time as input of read access. Since it is in a state of being ready, it is possible to easily provide a reset function capable of quickly returning from any address to address 0. Further, since the dynamic cell region occupying most of the storage plane is composed of the three-transistor storage cell having a simple structure, not only the occupied area of the memory can be greatly reduced but also the number of digit lines is reduced. Since the structure of the control system for the read-ahead preparation is simplified, the read speed can be improved and the reliability can be further enhanced.

[Brief description of drawings]

1 and 2 are a block diagram of a data write storage plane and a connection circuit diagram of its dynamic storage cell array, respectively, showing an embodiment of the present invention. 100 ... data write storage plane, 10 ... static storage cell array storage plane, 20 , 30 ... 3-transistor dynamic storage cell array storage plane, 1 ... write digit line, 2 ... read digit line 3 ... Write selection line, 4
...... Read selection line, 5,6 …… Write pointer potential line, 7 ……
Write data bus, A , B , C , D ... 3-transistor dynamic storage cell, Q ₁ ... Write transistor, Q ₂
…… Sense transistor, Q ₃ …… Read transistor,
Q ₀ ... write load transistor, N ... inverter.

Front page continued (72) Inventor Hiroaki Ikeda 5-7-15 Shiba, Minato-ku, Tokyo NEC Electric microcomputer system Co., Ltd. (56) Reference JP-A-53-136924 (JP, A) JP-A-SHO 58-75078 (JP, A) JP 51-47328 (JP, A) JP 53-123627 (JP, A) JP 58-23373 (JP, A) JP 48-9641 (JP, A)

Claims (1)

[Claims] 1. A semiconductor memory device having a plurality of consecutive addresses, in which data is serially read in the order of consecutive addresses, the first area corresponding to consecutive addresses from a start address to a predetermined address. And a second region corresponding to another address following the predetermined address, the memory cells in the first region are static memory cells, and the memory cells in the second region are prepared for pre-reading. A dynamic memory cell having a configuration is provided, and in response to a reset, reading from the first address of the first area is started, and at the same time, pre-reading preparation for another address following the predetermined address of the second area is performed. A semiconductor memory device characterized by the above.