JPH0746518B2 - Semiconductor memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] When displaying an error address in a semiconductor memory test, the address causing the error and the address (one or more) accessed before the error are displayed simultaneously. With this configuration, it is possible to facilitate the analysis of defects and the like.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus, and more particularly to a method of displaying an address in which an error has occurred in a test.

[Prior Art] When a memory error occurs in a semiconductor memory test, the address is displayed in the form of a fail bit map. Conventionally, only the address causing the error is displayed. Was to be displayed.

Fig. 3 shows the conventional error in semiconductor memory test.
It is a block diagram which shows the concept of an address display system.

In FIG. 3, UTM represents a device under test and FAM represents a fail address memory.

The fail address memory FAM is a memory provided in the memory test system and having the same address capacity as the device under test UTM, and stores information at the same address as the device UTM under error. .

For example, "1" is stored when an error occurs, and "0" is stored otherwise.

After the test is completed, the contents of this fail address memory FAM are read out, and as in the display example shown in the display DSP, for example, the memory cells are arranged in a matrix and the error address is displayed as "F". It was either done or printed out.

[Problems to be Solved by the Invention] In a semiconductor memory test, when the failure mode causing an error is a fixed failure, the conventional error address display method described above is sufficient.

However, in the case of an intermittent error (soft error), it is necessary to know the address history for defect analysis and characteristic evaluation. Also, by knowing the history of addresses, it is possible to know the error mode (whether an error that should be "1" is "0" or an error that should be "0" is "1"). , The number of tests can be reduced.

The present invention introduces a new error
It is intended to provide an address display method.

[Means for Solving Problems] FIG. 1 is a block diagram showing the principle of the memory test apparatus of the present invention.

In FIG. 1, the same symbols as those in FIG. 3 indicate the same objects.

The ASK is an address stack newly provided in the memory test apparatus of the present invention, and is an N-stack shift register that stores the address of the test cycle every time.

The address stack ASK always stores the latest N cycles of addresses for each test cycle.

If an error occurs in the device under test UTM,
The address memory FAM is read and the address is displayed on the display DSP, and the address of the previous (N-1) cycle is read from the address stack ASK and the address is also displayed.

[Operation] FIG. 1 shows that when an error occurs in the device under test UTM,
Error Bit Map Display This shows one of the display examples of the address history displayed on the DSP.

In the example of the error / address display in FIG. 1, "F" is displayed at the address that actually caused the error, and "B" is displayed at the address accessed before the error occurred.
In the figure, Indicates.

Looking at the display example in FIG. 1, the address of “F” is 0101 and the address of “B” accessed immediately before is “1010”.
And it turns out that this is the "bar" address of the "F" address.

[Example] The gist of the present invention will be described more specifically with reference to an example shown in FIG.

The display example of the address history shown in FIG. 1 shows an address in which an error has occurred and an address accessed immediately before that. That is, it is the minimum address history display.

Generally, it is sufficient to know the history of four to eight addresses for defect analysis and characterization.

FIG. 2 shows an embodiment of the present invention displaying four address histories.

FIG. 2A is a diagram showing an example of an address sequence pattern in a memory having 4 × 4 = 16 addresses, and the numbers indicate the access order.

As shown by, it is assumed that an error has occurred in the n = 8th cycle.

FIG. 2 (c) shows the state of the address stack ASK having four stacks at n = 8 cycles.
The address of n-1 = 7 cycles is stored in the second stack,
An address of n-2 = 6 cycles is stored in the third stack, and an address of n-3 = 5 cycles is stored in the fourth stack.

FIG. 2 (b) shows an example of displaying four address histories in the above situation.

In FIG. 2 (b), "F" indicates the address that caused the error, "1",
"2" and "3" indicate addresses in n-1, n-2, and n-3 cycles, respectively. (The arrow in the figure is not displayed.) By the display in FIG. 2 (b), 3 → 2 as shown by the arrow
It is easy to see that the sequence was performed in the order of → 1 → F.

[Effect of the Invention] As described above, according to the present invention, the address history when an error occurs can be displayed, and the effect of improving the quality of the semiconductor memory test and reducing the number of steps is extremely large.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram for explaining an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. In the drawing, UTM is a memory device under test, FAM is a fail address memory, DSP is a display, and ASK is an address stack.

Claims (1)

[Claims] 1. A semiconductor memory test apparatus for testing the quality of a semiconductor memory, which has the same address configuration as that of a device under test (UTM), and when an error occurs in the device under test (UTM), the error occurs. A fail address memory (FAM) that stores information indicating an error at the same address as the stored address, an address stack (ASK) that stores a plurality of addresses most recently accessed in the test cycle, Reads the data in the address memory (FAM) and the address stack (ASK), and displays the address in which the error occurred, the address accessed before that and stored in the address stack (ASK), and the access sequence. A semiconductor memory configured so as to include a display control circuit that performs control for simultaneously displaying the indicated information. Test equipment.