JPH0690880B2 - Error address display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A method of displaying an error address in a semiconductor memory test or the like, which is configured to simultaneously display an address causing an error and information of a cell in the background. This facilitates characterization and failure analysis.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of displaying an address in which an error has occurred in a semiconductor memory test or the like.

[Prior Art] In a semiconductor memory test, when an element under test causes an error, its address is displayed in the form of a "fail bit map".

Fig. 4 shows the conventional error in semiconductor memory test.
It is a block diagram which shows an address display system.

In FIG. 4, UTM indicates the device under test, and MTS indicates the memory test device. In the memory test equipment MTS, there is a fail address memory FAM.

As shown in FIG. 5, the fail address memory FAM has a capacity equal to or higher than that of the device under test UTM, and when the device under test UTM causes an error, information is stored in the same address as that address. Write.

After the test, this fail address memory FAM
The address is sequentially read from the address "0" by +1 and displayed on the display as shown in DSP.
Or print it out.

In this case, conventionally, only the address that caused the error was displayed.

[Problems to be Solved by the Invention] The above-mentioned "fail bit map" is often used in fields such as semiconductor memory characteristic evaluation and failure analysis.

However, in the conventional method, only the address causing the error can be known, and the state of the so-called background cell around the address causing the error cannot be known.

For this reason, when an error occurs due to pattern dependency such as an intermittent error (soft error), it is necessary to compare with the information of the test pattern to determine the cell data of the address other than the fail address. There was a problem.

The present invention is intended to provide a novel error address display system that solves the above problems.

[Means for Solving Problems] FIG. 1 is a block diagram showing the principle of the error address display system according to the present invention.

In FIG. 1, the same symbols as those in FIG. 3 indicate the same objects.

DM is a data memory, has a capacity equal to or greater than that of the device under test UTM, and stores the data content of the device under test UTM.

The device under test UTM, the fail address memory FAM, and the data memory DM have exactly the same addresses, and the hardware configuration is relatively simple.

After one test, fail address memory FAM
Are sequentially read for all addresses. If “1”, for example, “F” is displayed on the display DSP, and if not “1”, the data memory DM is read and the data “0” or “1” is read. "Is displayed.

[Operation] In the semiconductor memory test, not only the error address but also the information of the cells around the error address are displayed at the same time, so that the address of the error and the information of the background cell can be easily known. It is possible,
It can be useful for checking for pattern dependencies.

[Examples] The present invention will be described in more detail with reference to the examples shown in Figs. 2 and 3.

FIG. 2 is a flow chart showing a method of displaying an error address according to the present invention.

Start with address AD = 0.

The fail address memory FAM and the data memory DM are read simultaneously.

It is determined whether or not the data in the fail address memory FAM is "1". If "1", the process proceeds to step. If "0", the process proceeds to step.

Write "F" to display data memory or printout data memory.

Read data “0” from data memory DM to display data memory or print data memory
Or write "1".

Add 1 to address AD.

It is determined whether or not the address AD =, and if NO, the process returns to the step, and if AD = n, the process proceeds to the step.

This process ends.

FIG. 3 shows a display example of error addresses according to the present invention.

In Figure 3, "F" indicates the address in error,
“0” and “1” indicate the information of the cell of the address that has no error.

FIG. 3 (a) shows the entire background, and FIG. 3 (b) shows only the information of the adjacent cells above, below, left and right of the address in error.

Normally, the information of adjacent cells above, below, left and right of the address in error as shown in FIG. 3 (b) is sufficient, but as a display method, the same row address as that of the error and the column address are used. An address that is ± 1 and an address that has the same column address as the error address and has a row address of ± 1 are selected and displayed.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily know the information of the cell of the background as well as the address in which the error has occurred, and it is possible to check the presence or absence of the pattern dependence and evaluate the characteristics and It can be used for failure analysis, and its practical effect is great.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a flowchart of an embodiment of the present invention, FIG. 3 is a display example according to the present invention, FIG. 4 is a block diagram of a conventional example, and FIG. It is a display pattern figure. In the figure, UTM is the device under test, FAM is the fail address memory, DM is the data memory, and DSP is the display.

Claims (1)

[Claims] 1. In a semiconductor memory test or the like, when the device under test (UTM) has a capacity equal to or greater than that of the device under test (UTM), and the device under test (UTM) causes an error, the same address as the address causing the error is measured. A fail address memory (FAM) that stores information at an address, and a data memory that has the same or larger capacity as the device under test (UTM) and stores the same information as the device under test (UTM) (DM) is provided, and the error-causing address and the information of cells around it are configured to be displayed at the same time.
Address display method.