JPH0746703B2 - Method for manufacturing ROM semiconductor device - Google Patents

Description

The present invention relates to a ROM semiconductor device, and more particularly to a ROM semiconductor device using two-layer wiring.

(B) Conventional technology The following three types are often used in ROM semiconductor devices.

The ROM semiconductor device shown in FIG. 5 is called a contact ROM and stores information depending on the presence or absence of a contact. In the figure, (31) is a data line for reading data, and (32) is an address line for each bit, which constitutes the gate of each MOS transistor in the ROM. (33)
Is a contact hole, and a MOS transistor is formed where the contact hole (33) is provided. (34) is a diffusion layer that forms the source region of the MOS transistor, and (35) is MO
It is a diffusion layer that forms the drain region of the S transistor.

The ROM semiconductor device shown in FIG. 6 is called a field ROM, and stores information depending on the presence or absence of a field oxide film of a MOS transistor. In the figure, (41) is a data line for reading data, and (42) is an address line for each bit, which constitutes the gate of each MOS transistor in the ROM. (43) is a contact hole. (44)
Is a diffusion layer forming the source region of the MOS transistor, and (45) is a diffusion layer forming the drain region of the MOS transistor.

The ROM semiconductor device shown in FIG. 7 is called a depletion ROM, and stores information depending on whether or not an impurity is injected into the channel region of a MOS transistor. (51) is a data line for reading data, and (52) is an address line for each bit, which constitutes the gate of each MOS transistor in the ROM. (53) is a diffusion region that forms the source / drain regions of the MOS transistor in the ROM.
Reference numeral (54) shows an impurity implantation region into the channel region of a MOS transistor for storing data. MOS transistors without implantation are normally off, and transistors with implantation are normally on.

The ROM semiconductor device has, for example, an AND-OR configuration as shown in FIG. 1 of USP 3,541,543, the series connection circuit is configured by using the depletion ROM shown in FIG. 7, and the parallel connection circuit is the fifth connection circuit. Contact ROM shown in Figures and 6
And field ROM. Such ROM
The semiconductor device is incorporated in the same chip as a part of the microcomputer, and the ROM is rewritten according to the function of the microcomputer. Generally, in semiconductors such as microcomputers, ROM semiconductor devices are NAND
-NOR configuration, NOR configuration is P-channel MOS transistor series connection or N-channel MOS transistor parallel connection, NAND configuration is N-channel MOS transistor
The transistors are connected in series or the P-channel MOS transistors are connected in parallel.

(C) Problems to be Solved by the Invention When rewriting the ROM semiconductor device as described above, it is necessary to perform rewriting by selecting the MOS transistor of the series connection circuit and rewriting by selecting the MOS transistor of the parallel connection circuit. However, since the serial connection circuit and the parallel connection circuit have different ROM configurations, it is necessary to change the mask and rewrite in a two-step process. Therefore, there is a drawback that it takes a long time to rewrite the ROM.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and a ROM semiconductor device is formed by using two-layer wiring, and a series connection circuit is formed by switching the first electrode layer to form a MOS transistor. By selecting, the parallel connection circuit forms the data line in the second electrode layer and selects the MOS transistor depending on the presence or absence of the drain electrode of the MOS transistor up to the contact hole, which greatly improves the conventional defects and facilitates switching. It realizes a ROM semiconductor device.

(E) Operation According to the present invention, the contents of the ROM can be switched only by changing the first electrode layer of the two-layer wiring in both the series connection circuit and the parallel connection circuit of the ROM semiconductor device. It was improved by changing the masks on one sheet.

(F) Embodiment A ROM semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 to 4.

1 and 2 are a circuit diagram and a sectional view for explaining a series connection circuit of a ROM semiconductor device of the present invention. The serial connection circuit is formed by serially connecting the MOS transistors (1) ... (1) formed at the intersections of the data lines and the address lines, and it is not necessary to select the presence or absence of the MOS transistors (1) ... (1). This is done by shorting the source and drain of the MOS transistor (1) with a wiring. FIG. 2 shows the structure, in which a diffusion layer (3) serving as a source or drain region is provided on the surface of the semiconductor substrate (2) at a distance from the diffusion layer (3).
An address line serving as a gate electrode (6) made of polysilicon is provided on the channel region (4) between them via the gate oxide film (5) to cover the surface of the substrate (2).
A first electrode layer (8) made of aluminum is provided on the insulating film (7) of the above, and a second insulating film (9) for performing interlayer insulation is provided on the first electrode layer (8). A second electrode layer (10) made of aluminum is provided on the insulating film (9).
Therefore, the first MOS transistor unnecessary in the series connection circuit is
Information is stored by short-circuiting the source and drain of the electrode layer (8).

FIG. 3 and FIG. 4 are a circuit diagram and a sectional view for explaining a series connection circuit of the ROM semiconductor device of the present invention. The parallel connection circuit is formed by connecting in parallel each MOS transistor (11) ... (11) formed at the intersection of the data line and the address line, and the selection of the presence or absence of each MOS transistor (11). It is assumed that the MOS transistor (11) is formed by the presence or absence of the drain electrode of each MOS transistor (11) formed of the first electrode layer (19) up to the contact hole of the data line of the electrode layer (21). At this time, the drain electrode formed of the first electrode layer (19) is extended and connected to the data line of the second electrode layer (21). FIG. 4 shows the structure, in which a source region (13) and a drain region (14) are provided by diffusion on the surface of a semiconductor substrate (12) so as to be spaced apart from each other, and a channel region (15) between both regions (13) and (14) is provided. ) On which an address line serving as a gate electrode (17) made of polysilicon is provided via a gate oxide film (16) and made of aluminum on the first insulating film (18) covering the surface of the substrate (12). The first electrode layer (19) is provided in ohmic contact with the drain region (14) of each MOS transistor, and the second insulating film (20) for performing interlayer insulation is provided on the first electrode layer (19). Data lines are provided on the second insulating layer (20) by a second electrode layer (21) made of aluminum. The source region (13) is adjacent to the MOS transistor (1
Shared in 1). Data line contact holes are MOS
A first electrode layer (19) is provided in an island shape on the first insulating film (18) below the contact hole (22), which is formed on the source region (13) of the transistor. Therefore, in parallel connection circuit, MO
When the S transistor (11) is provided, the first electrode layer (1
In 9), the drain electrode (23) of the MOS transistor (11) is extended to the contact hole (22) and the data line is connected to the drain electrode (23) of the MOS transistor (11) to store information. There is.

In the above-described ROM semiconductor device of the present invention, when the contents of the ROM are rewritten, when the pattern of the first electrode layer (8) is changed in the series connection circuit and the MOS transistor (1) is provided, When the one electrode layer (8) is removed and the MOS transistor (1) is not present, the source / drain is short-circuited in the first electrode layer (8) to rewrite information. On the other hand, in the parallel connection circuit, if the pattern of the first electrode layer (19) is changed and the MOS transistor (11) is provided, the drain electrode (23) formed by the first electrode layer (19) is connected to the contact hole (22). When the MOS transistor (11) is extended and connected to the data line, the first electrode layer (19) between the drain electrode (23) and the contact hole (22) is removed to rewrite information.
Therefore, in the present invention, the rewriting of information in the series connection circuit and the parallel connection circuit can be realized only by changing the pattern of the first electrode layers (8) and (19).

(G) Effect of the invention According to the present invention, the ROM is realized by utilizing the two-layer wiring structure.
There is an advantage that the series connection circuit and the parallel connection circuit of the semiconductor device can be rewritten only by changing the pattern of the first electrode layers (8) and (19). Therefore, if it is applied to a microcomputer or the like, it is sufficient to rewrite the contents of the ROM for each customer by changing the mask of the first electrode layer (8) (19), and the development period of the customer product can be greatly shortened.

[Brief description of drawings]

1 and 2 are circuit diagrams and cross-sectional views illustrating a series connection circuit of a ROM semiconductor device of the present invention, and FIGS. 3 and 4 are circuit diagrams illustrating a parallel connection circuit of a ROM semiconductor device of the present invention. And the cross-sectional view and FIG. 5 are conventional contact ROMs.
FIG. 6 is a top view illustrating a conventional field ROM, and FIG. 7 is a top view illustrating a conventional depletion ROM. Description of main figure numbers (1) and (11) are MOS transistors, (2) and (12) are semiconductor substrates, (6) and (17) are gate electrodes, (8) and (19) are first electrode layers, and (10) ) (21) is a second electrode layer, and (22) is a contact hole.

Claims (1)

[Claims] 1. A ROM having a series connection circuit and a parallel connection circuit.
In the method of manufacturing a semiconductor device, the pattern of the first electrode layer in the series connection circuit is changed so that the first electrode layer is eliminated when a MOS transistor is present, and the first electrode layer is eliminated when the MOS transistor is absent. In the parallel connection circuit, the pattern of the first electrode layer is changed so that the source / drain is short-circuited between the source and the drain in the layer, and when the MOS transistor is provided, the drain electrode formed in the first electrode layer. Connected to the data line formed by the second electrode layer extending to the contact hole, and when there is no MOS transistor, the first electrode layer between the drain electrode and the contact hole is removed to rewrite information. A method for manufacturing a ROM semiconductor device, comprising: