JPH0746813B2 - Synchronous phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a synchronous phase detection circuit used for detecting multi-valued information in a transmission system.

(Prior Art) There is a four-phase phase modulation system as a system for transmitting multi-valued information. The phase vector of the phase modulation signal is shown in FIG.
FIG. 6 shows a synchronous detection circuit for this phase modulation signal. In Fig. 5, A, B, C, D indicate four phases in the four-phase phase modulation method, and the circumference including A, B, C, D indicates the locus of the values that analog phase modulation can take. ing. Further, the I axis shows the carrier phase in phase with the reference phase, and the Q axis shows the carrier phase orthogonal to the I axis.

FIG. 6 shows a synchronous detection circuit for the time division signals of the four-phase phase modulation and the analog modulation. The time division modulated signal input from the input terminal 1 is a band filter (BPF in the figure).
After the band is limited by (2), the phase detection circuit 3,4
Is supplied to. The phase detection circuits 3 and 4 are reproduced carrier waves (I-CW) (Q having phases corresponding to the I axis and the Q axis in FIG. 5).
-CW) is used to synchronously detect the time-division modulation signals input to each. The outputs of the phase detection circuits 3 and 4 are supplied to analog-digital converters (denoted as A / D in the figure) 5 and 6 and quantized into m-bit digital signals. MSB output (5MSB) (6MSB) of each analog-digital converter 5,6
Are supplied to the 4-phase detector 11. This MSB output (5MSB)
(6MSB) is exactly the same as the binarized output obtained using a normal comparator. The 4-phase detector 11 has two inputs “0”, “1”
The phase information is derived to the output terminal 13 by the combination of.

On the other hand, the outputs 5D and 6D of the analog-digital converters 5 and 6 are
Respect analog phase theta, cos [theta], because it is sinθ becomes value, TAN is the tan ^-11 circuit (Fig having these tan ^-1 properties
^-1 ) 12 to obtain the value of θ, which is output to the output terminal 14. The carrier wave is reproduced as follows. For example, the possible values of the 4-phase signal are
Using the fact that it is fixed at 90 ° intervals, the phase-locked loop (PLL) is used so that the output of the tan ^-1 circuit 12 becomes the phase that the four-phase modulation signal should take at the time of four-phase modulation.
Is achieved by operating. That is, tan ^-1 circuit 1
The output of 2 is supplied to the gate circuit 15, and the output is sampled by the 4-phase phase modulation timing signal (TCK) in this gate circuit 15 so that the phase to be taken by the 4-phase phase modulation signal is actually detected synchronously. The error of the obtained phase is obtained. By supplying this error component to the voltage controlled oscillator 18 via the digital-analog converter (denoted as D / A in the figure) 17, the phase of the reproduced carrier wave (I-CW) (Q-CW) becomes a desired phase. Can be matched. Reference numeral 19 is a 90 ° phase shifter for obtaining a regenerated carrier (Q-CW) having a Q-axis phase.

(Problems to be Solved by the Invention) Here, the phase difference between the I-axis and the Q-axis shown in FIG.
Considering the case where the angle is not 90 °, the reproduced carrier becomes like the I ′ axis and the Q ′ axis in FIG. FIG. 3 shows the case where the phase difference between the I ′ axis and the Q ′ axis is 90 ° or less. The detection of the 4-phase phase modulation signal leads to an increase in bit error. There is a demand for improved demodulator performance, and an accurate 90 ° phase shifter is required so that the phase difference between the I and Q axes is exactly 90 °. Furthermore, it is required to obtain an accurate detection output even when the ambient temperature changes. Therefore, it may be necessary to adjust the 90 ° phase shifter,
Also, an expensive 90 ° phase shifter with high accuracy and high stability was required.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronous phase detection circuit which can make a 90 ° phase shifter inexpensive and can eliminate the need for adjustment work.

(Means for Solving the Problems) In the present invention, the detected carrier outputs having different phases but having the same detection level are compared with each other to detect the magnitude relationship, and reproduced carrier waves (I-CW) which should be in quadrature phase with each other are detected. ), (Q-
The phase shift amount control means detects that CW) deviates from the angular interval of 90 °. Based on the information obtained by this detection processing, the amount of phase shift of the 90 ° variable phase shifter is controlled and corrected so that the reproduced carrier waves (I-CW) (Q-CW) are in quadrature phase. is there.

(Operation) As described above, by providing the phase shift amount control means and the 90 ° variable phase shifter, the quadrature state of the reproduced carrier waves (I-CW) and (Q-CW) is detected, and this detection is performed. Depending on the result
The phase shift amount of the 90 ° variable phase shifter is controlled, and the reproduced carrier wave (I-
The quadrature state of (CW) and (Q-CW) is always kept stable.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is an embodiment of the present invention, and the basic configuration is the sixth embodiment.
Although it is the same as the conventional one described in the figure, in the case of this embodiment, the reproduced carrier wave (I-
CW) is shifted by 90 ° to obtain a regenerated carrier (Q-CW)
The feature is that the phase shift amount control means 40 is connected to the 90 ° variable phase shifter 25. The circuit of FIG. 1 will be described below.

The time division modulation signal input from the input terminal 1 is band-limited by the band filter 2 and then supplied to the phase detection circuits 3 and 4. The phase detection circuits 3 and 4 basically have a reproduced carrier wave (I-) having a phase corresponding to the I axis and Q axis in FIG.
CW) and (Q-CW) are used to synchronously detect the time-division modulation signals input to each. Then, each phase detection circuit 3, 4
Is supplied to the analog-digital converters 5 and 6 and quantized into an m-bit digital signal. The MSB output (5MSB) (6MSB) of each of the analog-digital converters 5 and 6 is exactly the same as the output obtained by binarizing the four-phase signal using a normal comparator.

Therefore, the MSB output (5MS
B) is 0,1 above or below the I axis as the boundary in FIG.
Distinguish by the sign of. In addition, analog-digital converter 6
The MSB output (6 MSB) is distinguished from the left or right in FIG. These MSB outputs are 4
It is supplied to the phase detector 11. In the 4-phase detector 11, the 4-phase phase is identified by the combination of the signs of the MSB outputs from the analog-digital converters 5 and 6, and the output is
It is led to the output terminal 13.

On the other hand, the outputs 5D and 6D of the analog-digital converters 5 and 6 are
Respect analog phase theta, cos [theta], because it is sinθ becomes a value, if supply them to the tan ^-1 circuit 12 having a tan ^-1 characteristics, it is possible to obtain the value of the theta. This value θ is guided to the output terminal 14. Thereby, the transmitted information can be grasped by the quadrant information of the output terminal 13 and the angle information of the output terminal 14.

Next, a reproduced carrier wave (I
-CW) and (Q-CW) are created as follows. tan ^-1
The output (value of θ) of the circuit 12 is supplied to the gate circuit 15. A timing signal (TCK) serving as a reference for four-phase phase modulation is supplied to the gate circuit 15 from an input terminal 16.
This is because the possible values of the 4-phase phase signal are fixed at 90 ° intervals. At the time of 4-phase phase modulation, the output of the tan ^-1 circuit 12 is a predetermined value (phase θ). This is what is used. Therefore, in the gate circuit 15, the output of the tan ⁻¹ circuit 12 is sampled by the timing signal, and an error amount between the phase actually obtained by synchronous detection and the predetermined phase to be taken by the 4-phase phase modulation signal is obtained. . This error component is converted into a DC control voltage by the digital-analog converter 17 and supplied to the frequency control terminal of the voltage controlled oscillator 18. As a result, the oscillation output frequency of the voltage controlled oscillator 18 is controlled so that the output of the tan ⁻¹ circuit 12 becomes a predetermined value which the four-phase modulation signal should take.

Here, the direct output of the voltage controlled oscillator 18 is used as a regenerated carrier (I-CW), and the 90 ° phase shifter 25 90 ° phase-shifted this is used as a regenerated carrier (Q-CW). .

By the way, in this embodiment, the 90 ° variable phase shifter 25 is connected with a phase shift amount control means 40 capable of finely adjusting the phase shift amount. The phase shift amount control means 40 includes a comparison circuit 22, a low-pass filter 23, and a digital-analog converter.
It consists of 24. The operation will be described below with reference to FIG.

Now, as shown in FIG. 3, when the phase difference between the I axis and the Q axis is deviated from 90 °, the carrier wave for synchronous detection is operated by the function of the phase lock loop like the I ′ axis and the Q ′ axis in the figure. Is obtained. A, B, C,
Carriers I'and Q'are reproduced so that the four phases of D are always 45 ° in each phase quadrant. At this time, for example, assuming that A, B, C, D projected on the I'axis are a, b, c, d, respectively, as shown in the figure, when a = d, b = c It can be seen that the I'and Q'axes coincide with the I and Q axes.

Therefore, if the phase shift amount of the 90 ° phase shifter 25 is controlled so that a = d and b = c, the I ′ axis and the Q ′ axis have an interval of 90 °, and the I ′ axis and the Q ′ axis have a phase locked loop. It will coincide with the axis and the Q axis. Therefore, in the comparison circuit 22, the values corresponding to A, B, C and D included in the I ′ axis detection output 5D are set.
a, b, c, d are fetched, and a and d and c and b are compared. A latch pulse for taking in a, b, c, d is given from the terminal 38. This latch pulse is created based on the quadrant information obtained at the terminal 13, and a and d and c and b are taken into the latch circuit described later. The comparison result of the comparison circuit 22 is supplied to the digital-analog converter 24 via the low-pass filter 23 and becomes an analog control signal.
It is supplied to the phase shift amount control terminal of the phase shifter 25. As a result, the Q'axis coincides with the Q axis, and the I'axis also coincides with the I axis.

FIG. 2 shows a part of the phase shift amount control means 40 in more detail. Of the m-bit output of the analog-digital converter 5, the lower (m-1) bit 5D is supplied to the input terminal 26. The latch circuit 28 latches the value of a and the latch circuit 29 latches the value of d. Similarly, the lower (m-1) bit 5D is sign-inverted by the inverter 27 and then supplied to the latch circuits 30 and 31. The latch circuit 30 latches the value of c, and the latch circuit 31 stores the value of b. Latch the value. The comparator 32 compares the values of a and d, and the comparator 33 compares the values of c and b. The comparison result is input to the selector 34,
Only the person who needs it is taken out, and the adder 35 and the delay circuit 36
Is supplied to the low-pass filter 23 constituted by and smoothed, and then led to the output terminal 37.

The latch circuits 28 and 29, 30 and 31 are respectively assigned a and d, and c and b. This is because the latch pulse applied to the terminal 38 is actually logic information and includes quadrant information, and the desired latch This is because the circuit can be specified.

In the above embodiment, in order to detect the quadrature state of the I-axis and the Q-axis, which are the reference phases, the magnitude relationship between the phase detection output levels of 45 ° and 315 ° or 135 ° and 225 ° is compared, and 90 ° A phase shift amount control signal for the variable phase shifter 25 is produced. However, the present invention is not limited to this, and the phase shift output control signal may be generated by comparing the phase detection output levels of 45 ° and 135 ° or 225 ° and 315 °.

Now, regarding the detection of the analog phase modulation signal, this detection requires a more accurate 90 ° phase difference between the I axis and the Q axis than the detection of the four phase modulation signal. That is, the detection output of the analog phase modulation signal is
Even if there is a slight orthogonal shift as shown in FIG. 4, the detection linearity deteriorates as shown by the broken line with respect to the solid line.
According to the present embodiment, by detecting the shift of the quadrature phase of the reproduced carrier wave for synchronous detection and adjusting the 90 ° phase shift amount, it is possible to obtain an analog phase detection output with extremely good linearity.

In the above embodiment, the time-division signals of four-phase phase modulation and analog modulation are targeted as the signals to be synchronously detected, but the present invention is not limited to the above embodiment.
It can be applied to a signal having a four-phase modulation component, including a case of only a phase-modulation signal.

〔The invention's effect〕

According to the above-described invention, the quadrature phase shift of the reproduced carrier wave for synchronous detection can be detected by a simple means, and the 90 ° phase shift amount can be automatically and accurately adjusted. In the past, a high-precision, highly stable and expensive 90 ° phase shifter was required, but an inexpensive one may be used according to the present invention.
Furthermore, even if an inexpensive 90 ° variable phase shifter is used, there is a means to automatically control the amount of phase shift, so it operates so that an accurate detection output can be obtained even when the ambient temperature changes. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the circuit of FIG. 1 in more detail, and FIG. 3 is shown for explaining the circuit operation of the present invention. Explanatory diagram of phase axis, FIG. 4 is a diagram showing a characteristic example of analog phase detection output,
FIG. 5 is an explanatory view showing a vector of the 4-phase phase modulation system, and FIG. 6 is a view showing a conventional synchronous phase detection circuit. 3,4 ... Phase detection circuit, 5,6 ... Analog-digital converter, 11 ... 4-phase detection circuit, 12 ... Tan- ¹ circuit, 15 ...
Gate circuit, 17 ... Digital-to-analog converter, 18 ...
… Voltage controlled oscillator, 25 …… 90 ° variable phase shifter, 40 …… Phase shift amount control means.

Claims (1)

[Claims] 1. A first phase detection circuit and a second phase detection circuit, each of which is supplied with a signal containing a four-phase phase modulation component and performs synchronous detection on mutually orthogonal reproduced carrier waves, and the first and second phase detection circuits. An analog-digital converter for quantizing each output, a means for obtaining quadrant information of the input signal by using upper bits of the output of the analog-digital converter, and a tan using the output of the analog-digital converter
^-1 for obtaining the angle information and the detection information depending on the timing of the four-phase modulation in the angle information is obtained, and the difference between the detection information and the predetermined reference information is obtained. Means for controlling the oscillating frequency of the voltage controlled oscillator generating the first reproduced carrier wave based on the above, and a 90 ° variable phase shift for phase-shifting the first reproduced carrier wave to derive the second reproduced carrier wave Of the output of the first analog-digital converter and the output of the first analog-to-digital converter, the outputs that should be equal in detection level but different in phase are respectively latched, the magnitudes of them are compared, and the outputs are to be equal to each other using the difference. And a means for controlling the phase amount of the 90 ° variable phase shifter so that the synchronous phase detection circuit.