JPH0748144B2 - Driving method of display device - Google Patents

Abstract

PURPOSE:To make a gradational display of excellent display quality with simple circuit constitution even when the number of gradations of the gradational display increases by employing a thinning-out system in addition to a voltage modulation system. CONSTITUTION:A data thinning-out circuit 34a cuts two fields of an input signal during a period of three fields when display data signals D3 - D0 inputted to an encoder 33 specify brightness levels 1 - 3. Further, a 2nd data thinning-out circuit 34b cuts one field of the input signal during a period of three fields when the element data signals D3 - D0 specify brightness levels 4 - 7. Namely, display data is cut off in several fields of former and latter (m) fields to display brightness lower than in the case of the voltage modulation system in addition to brightness displayed by the voltage modulation system. Consequently, control can be performed by the simple circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a display device such as an AC-driven capacitive flat matrix display panel (hereinafter referred to as a thin film EL display device) such as an electroluminescence display device. Regarding

2. Description of the Related Art FIG. 6 is a block diagram schematically showing the configuration of a general thin film EL display device. In the figure, the display panel 1 is a thin film
It consists of an EL (electroluminescence) element.
When this thin film EL element is, for example, a double insulation type thin film EL element, strip-shaped transparent electrodes are arranged in parallel on a glass substrate, a dielectric substance is laminated on this, and an EL layer is further laminated thereon. Then, a dielectric material is further laminated thereon to form a three-layer structure, and a strip-shaped back electrode extending in a direction orthogonal to the transparent electrode is arranged in parallel thereon.

In the display panel 1, the transparent electrodes of the thin film EL element are the data side electrodes D1 to D8, and the back electrodes of the thin film EL element are the scan side electrodes S1 to S4. Data side switching circuit 2 is a circuit for applying the individually modulated voltage V _M to the respective data side electrodes D1 to D8, individually connected data side output port group to each of the data side electrodes D1 to D8 3 and each data side electrode D1 ~
A logic circuit 4 which receives display data corresponding to D8 and turns on / off the data side output port group 3 according to the display data.

The scanning-side switching circuit 5 applies write voltages V _W1 , −V _W2 (V _W1 = V _W2 + V _{M to} each scanning-side electrode S ₁ to S 4 according to the line order thereof.
And a scanning-side output port group 6 individually connected to the scanning-side electrodes S1 to S4.
And a logic circuit 7 for turning on / off the scan side output port group 6 according to the line order of the scan side electrodes S1 to S4. The drive circuit 8 is a circuit for generating a high voltage for driving the display panel 1 from a constant reference voltage V _D , and a modulation drive circuit 9 for providing a modulation voltage V _M to the data side output port group 3.
And a write drive circuit 10 for supplying the write voltage V _W1 , -V _W2 to the scan side output port group 6.

The drive logic circuit 11 generates various timing signals necessary for driving the display panel 1 based on input signals such as the display data signal D, the data transfer clock CK, the horizontal synchronizing signal H, and the vertical synchronizing signal V. Circuit.

The basic display drive of the above-mentioned thin film EL display device is
While the section over the second of the two fields as one cycle, the data-side electrodes D1~D8 provide modulation voltage V _M corresponding to the display data which determines the emission and non-emission, the scanning side electrodes S1~S4
The write voltage V _W1 is applied in the first field and the write voltage −V _W2 is applied in the second field in a line sequential manner. By this display drive, the data side electrodes D1 to
In the portion corresponding to the pixel A where D8 and the scanning-side electrodes S1 to S4 intersect, a superimposing effect or a canceling effect of the write voltages V _W1 , -V _W2 and the modulation voltage V _M occurs, and the pixel A emits light as an effective voltage. Threshold voltage V _th or higher voltage V _W1 or light emission threshold voltage
A voltage V _W2 equal to or lower than V _th is applied, whereby each pixel A is in a light emitting / non-light emitting state and a predetermined display is obtained. Therefore, to one pixel A, the effective voltages whose polarities are inverted are alternately applied in the first field and the second field, and the two fields are set as one cycle to form the thin film EL.
AC driving is performed in which the waveform is symmetrical in time within one cycle that is ideal for the device.

Conventionally, in such a thin film EL display device, a pulse width of the modulation voltage V _M applied to the data electrodes D1 to D8 has been used as a driving method for changing the brightness of each pixel A in a plurality of steps, that is, a driving method for gradation display. , A pulse width modulation method for controlling the area intensity of the effective voltage applied to the pixel A, and an amplitude modulation method for controlling the amplitude of the modulation voltage V _M are known.

In this case, among the input signals input to the drive logic circuit 11, as the display data signal D, a signal having the number of bits corresponding to the number of steps of the luminance gradation is used, and the data side switching circuit 2 also displays the display data. A dedicated circuit corresponding to the number of bits of the signal D and the gradation display method is used.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, when gradation display is performed by the above-described conventional driving method, when the number of gradation steps increases, the number of bits of the display data signal D increases in accordance with the number of gradation steps. Therefore, it is necessary to control the pulse width and amplitude of the modulation voltage V _M very finely, and there is a problem that the circuit configuration is complicated and the cost is increased in order to perform the control accurately.

In order to solve these problems of the conventional driving method,
The applicant of the present application has previously proposed a driving method that uses a pulse width modulation or amplitude modulation method and a thinning method that cuts display data in one of two fields.

That is, this driving method accepts display data for each field and obtains brightness according to the display data, as well as accepting display data for every other field,
The number of brightness steps is increased by performing an operation for obtaining a low brightness that is about half the brightness according to the display data.

However, in the case of this driving method, the display data is cut in one of the first field and the second field in order to obtain a low brightness, and therefore the writing voltage of one polarity is applied to the pixel to emit light. Light is emitted only in the field, the symmetry of the effective voltage applied to the pixel is lost, and a burn-in phenomenon occurs when light emission display is performed for a long time.

FIG. 7 shows the applied voltage to the pixel in which such burn-in occurs-
Luminance characteristics (B curve in the figure) and applied voltage of normal pixel −
It is a graph which compares and shows a brightness characteristic (A curve in a figure). As is clear from the figure, in the pixel with burn-in,
The luminance of the light emission start voltage range (constant voltage range of V _th B or higher) becomes larger than the luminance of the light emission start voltage range (constant voltage range of V _th A or higher) in a normal pixel, and the higher brightness voltage range correspondingly. The luminance in the pixel is lower than that in a normal pixel.

Therefore, it is an object of the present invention to perform gradation display with good display quality by a simple circuit configuration without the need to finely control the pulse width and amplitude of the modulation voltage even when the number of gradation display steps increases. It is an object of the present invention to provide a driving method of a display device capable of performing a stable AC drive without causing image sticking to a pixel.

Means for Solving the Problems According to the present invention, a dielectric layer is interposed between a plurality of scanning side electrodes and a plurality of data side electrodes arranged in directions intersecting with each other, and a modulation voltage according to display data is applied to the data side electrode. On the other hand, the writing voltage is applied to the scanning-side electrode, and one frame of display voltage is completed by the first field having the one polarity of the writing voltage and the second field having the other polarity. In a method of driving a display device for displaying a plurality of levels of brightness according to display data, one screen is displayed by m (m is an odd number of 3 or more) frames, and the pulse width or amplitude of the modulation voltage is displayed according to the display data. The predetermined level of the multiple levels of brightness to be displayed is displayed only by the voltage modulation method that changes the The display of the luminance in steps uses the display data in the voltage modulation method, and sets each period for each m field in the first half and the latter half of the period of the m frame as one cycle, and displays within the cycle. It is a driving method of a display device, which is performed by blocking acceptance of the display data in a field of a predetermined order in one or a plurality of sections defined in association with luminance to be displayed.

Operation According to the present invention, in addition to the luminance displayed only by the voltage modulation method, the luminance is lower than that of the voltage modulation method by cutting off the display data in some fields of the first half and second half m fields. Since the brightness is also displayed, even if the number of gradation display steps increases and the number of bits of display data increases, it is not necessary to finely control the pulse width and amplitude of the modulation voltage, and the circuit configuration is simple. Can be done by Further, when the display data is selectively cut off to display the luminance, the display data of the same order and the same number of fields in the first half m (odd number of 3 or more) field and the second half m field of the m frame. Since the blocking is performed, the waveform of the effective voltage applied to the pixel has symmetry in the first half and the second half of the m frame, and stable AC driving is performed.

Embodiment FIG. 1 is a block diagram showing a schematic structure of a thin film EL display device to which a driving method according to an embodiment of the present invention is applied.

The thin film EL display device shown in FIG. 1 is a display device which is driven by the above-mentioned symmetrical driving method, and its schematic configuration is almost the same as that of the general thin film EL display device shown in FIG. It is the same. That is, the display panel 21 is composed of a double-insulation type thin film EL element. This thin film EL element has strip-shaped transparent electrodes arranged in parallel on a glass substrate, and a dielectric material is laminated thereon, and further on top of that. An EL layer is laminated, a dielectric material is further laminated thereon to form a three-layer structure, and a strip-shaped back electrode extending in a direction orthogonal to the transparent electrode is arranged in parallel on the EL layer.

In the display panel 21, the transparent electrodes of the thin film EL element are the data side electrodes D1 to Dx, and the back electrodes of the thin film EL element are the scanning side electrodes S1 to Sy. The data side switching circuit 22 is a circuit for individually applying the modulation voltage V _M to each data side electrode D1 to Dx, and a data side output port group individually connected to each data side electrode D1 to D8. 23 and each data side electrode D1 ~
A logic circuit 24 which receives display data corresponding to Dx and turns on / off the data-side output port group 23 according to the display data.

The scanning side switching circuit 25 applies the writing voltage V _W1 , −V _W2 (V _W1 = V _W2 + V _{M to} each scanning side electrode S1 to Sy according to the line sequence.
And a scanning side output port group 26 individually connected to each scanning side electrode S1 to Sy.
And a logic circuit 27 for turning on / off the scan side output port group 26 in line order of the scan side electrodes S1 to Sy. The drive circuit 28 is a circuit for generating a high voltage for driving the display panel 21 from a constant reference voltage V _D , and a modulation drive circuit 29 for supplying a modulation voltage V _M to the data side output port group 23.
And a write drive circuit 30 for supplying write voltages V _W1 and −V _W2 to the scan side output port group 26.

The drive circuit 31 uses a 4-bit display data signal [D3, D2, D1, D
0], a data transfer clock CK, a horizontal period signal H, a vertical synchronization signal V, and other input signals to generate various timing signals necessary for driving the display panel 21. The drive logic circuit 31 includes a data signal processing circuit 32 for processing the above-mentioned 4-bit display data signal [D3, D2, D1, D0], which is similar to the thin film EL display device shown in FIG. different. 4-bit display data signal [D3, D2, D1, D
0] are associated with each other so as to specify the luminance level of 16 gradations as shown in Table 1 according to the state.

FIG. 2 is a block diagram showing the configuration of the data signal processing circuit 32. In FIG. 2, the encoder 33 receives the display data signals [D3, D2, D1, D0] shown in Table 1 as input.
Among them, the signals designating the brightness levels 1 to 7 are converted into the display data signals [D3, D2, D1, D0] corresponding to any of the brightness levels 8 to 15 according to the rule described later, while the brightness levels 0, 8 The signal that specifies ~ 15 is a circuit that has a function of passing it without converting it.The next stage of this encoder 33 is the data that selectively cuts the input display data [D3, D2, D1, D0]. The thinning circuits 34a and 34b are connected to a gate circuit 34c which allows the thinning circuits 34a and 34b to pass without being cut.

Among them, the first data thinning circuit 34a is the encoder 3
Circuit for cutting the input signal in 2 fields in the period of 3 fields when the display data signal [D3, D2, D1, D0] input to 3 is a signal designating luminance levels 1 to 3 And the second data thinning circuit 34b
Is a display data signal [D3, D2,
D1, D0] is a signal for designating the luminance levels 4 to 7, and is a circuit for cutting the input signal in one field in the period of three fields. These data thinning circuits 34a, 34b are arranged such that the display data signals [D3, D2, D1, D0] input to the encoder 33 have luminance levels 0, 8 to 15
The operation is stopped by the encoder 33 at the time of the signal designating, and the display data signal [D3, D2, D1, D0] input to the encoder 33 causes the gate circuit 34c to change the brightness level from 0 to 8 to 15. It is enabled when the signal is specified.

The data thinning circuit 34a includes an inverter 35 that inverts the horizontal cycle signal H, an AND gate 36 that receives the inverted signal and the vertical synchronization signal V as two inputs, an inverter 37 that inverts the vertical synchronization signal V, and its inversion. An OR gate 38 that receives a signal and the output of the AND gate 36 as two inputs, a counter 39 that inputs the output of the OR gate 38 as a clock, and this counter
Four AND gates 40a to 40d each having a second-order bit output QB of 39 as one input and each bit of a display data signal [D3, D2, D1, D0] as another one input,
A NAND gate that generates a clear signal for the counter 39 by using the first and second bit outputs QA and QB of the counter 39 as two inputs
It is composed of 41 and.

Further, although the configuration of the other data thinning circuit 34b is not shown, the second-order bit output QB of the counter 39 is inverted in the data thinning circuit 34a described above, and the inversion ▼ is performed by four AND gates 40a to 40d. The only difference is that each input is one input, and other configurations are the same as those of the data thinning circuit 34a.

FIG. 3 shows that the display data [D3, D2, D1, D0] for designating the brightness levels of 1 to 3 as the brightness level of each pixel arranged on any one data side electrode is the data signal processing circuit. 32
6 is a timing chart showing the operation when the signals are sequentially input to the. In FIG. 3, (1) shows the waveform of the horizontal cycle signal H, (2) shows the waveform of the vertical synchronizing signal V, (3) shows the waveform of the clock CK input to the binary counter 39, (4). ，
(5) shows the waveforms of the first and second bit outputs QA and QB of the binary counter 39, and (6) shows the data signal processing circuit 32.
Display data D (= [D3, D2, D1, D0]) input to
(7) is a signal D '(= [D3', D2 ', D1', D0 ']) which is data-cut by the data signal processing circuit 32 and is output.
(8) is the write voltage V _W1 , − applied to the scanning side electrode.
The polarities of V _W2 are shown respectively. In addition, in FIGS. 3 (6) and 3 (7), l1 to l5 represent scanning lines intersecting with the pixels corresponding to the display data with the reference numerals, that is, the line sequence of the scanning side electrodes.

FIG. 4 shows the waveform of the effective voltage applied to each pixel corresponding to the scanning lines l1 to l4 when driven according to the timing chart shown in FIG.

Further, FIG. 5 shows that the display data [D3, D2, D1, D0] for designating the luminance levels of 4 to 7 as the luminance level of each pixel arranged on any one data side electrode is the data signal processing circuit. 3
2 shows the waveform of the effective voltage applied to each pixel corresponding to the scanning lines l1 to l4 when sequentially input to 2.

Next, the timing chart of FIG. 3 and FIGS.
The operation when the thin film EL display device of FIG. 1 is driven by the symmetrical driving method will be described with reference to the waveform diagram of the drawing.

Each time the scanning line is switched as shown in FIG. 3 (6), the display data signal [D3, D2, D1, D0] of the pixel corresponding to the scanning line (here, the display for designating the brightness levels 1 to 3) Data signal) is a sequential data signal processing circuit
When input to 32, encoder 33 turns data thinning circuit 34
Only output a. For example, when the display data signal [D3, D2, D1, D0] input to the data processing circuit 32 is the signal [0, 0, 1, 1] designating the brightness level 3, the encoder 33 determines the highest order of the signals. The bit data D3 is inverted and converted into a signal [1,0,1,1]. This signal is a signal that specifies the brightness level 11 as is apparent from Table 1.

The signal thus converted is selectively cut by the data thinning circuit 34a as shown in FIG. 3 (7). That is, when attention is paid to the pixel of the scanning line l1, the F _j
Not cut in the field, cut in the next F _{j + 1} field and further in the next F _{j + 2} field,
The above thinning process is repeated every three fields.
That is, the display data signals [D3, D2, D1, D0] corresponding to the pixels on the scan line 11 are not cut in the first one field of the three fields, but are cut in the second two fields.

The display data signals [D3 ', D2', D obtained in this way
1 ', D0'] is sent to the data side switching circuit 22, and in the uncut field of the display data signal [1,0,1,1], the data corresponding to the modulation voltage of the pulse width or amplitude corresponding to the signal While being applied to the side electrode, a positive writing voltage V _W1 is applied to the scanning side electrode corresponding to the scanning line 11 as shown in FIG. 3 (8), and the corresponding pixel is shown in FIG. As described above, since the effective voltage equal to or higher than the light emission threshold voltage V _th is applied, the corresponding pixel has the brightness level 11
It emits light with a brightness corresponding to (Brightness 24 in Table 1). At this time, the polarity of the effective voltage applied to the pixel is the write voltage V _W1
Corresponding to the polarity of, the positive polarity is obtained as shown in FIG.

On the other hand, in the two fields after the display data signal [1,0,1,1] is cut, the modulation voltage of the pulse width or amplitude corresponding to non-light emission is applied to the corresponding data side electrode. , The scanning side electrode corresponding to the scanning line l1,
In a F _{j + 1} field, as shown in FIG. 3 (8) negative write voltage -V _W2 is in the F _{j + 2} field write voltage V _W1 of the positive polarity is applied, respectively, to the corresponding pixel As shown in FIG. 4, since an effective voltage equal to or less than the light emission threshold voltage −V _th , V _th is applied, light emission is not performed.

That is, the scan line l1 in these three fields
The upper pixel emits light at a brightness 8 which is 1/3 of the brightness 24 of the brightness level 11, that is, the brightness level 3. Similar thinning-out processing is performed in the _third field after the _{Fj + 3th} field, and light emission of brightness 3 which is 1/3 of brightness 24 of brightness level 11 is also performed. At this time, since the polarities of the write voltages V _W1 and −V _W2 are reversed every other field, the polarity of the write voltage in each field from the F _{j -th} field to the F _{j +2 -th} field and since opposite each other to the polarity of the write voltage in the F _{j + 3} field following three fields corresponding one to one to each field, 6 field from the F _j field until the F _{j + 5} field, i.e. 3 During the frame, the effective voltage applied to the pixel has symmetry between the first half 3 field period and the second half 3 field period.

Then, one brightness level (here, brightness level 3) is displayed during the period of these three frames.

The luminance levels are displayed in the same manner for the pixels on the lines below the scan line l2, but in this embodiment, as shown in FIG. 3 (7), the display data signals corresponding to the pixels on the scan line l2 are cut off. It is not the F _{j + 1} field, and the display data signal corresponding to the pixel on the scan line l3 is not cut at the F _{j + 2} field, and between three consecutive scan lines. Then, the fields that cut the signal are different from each other. Therefore, as shown in FIG. 3, pixels between adjacent scan lines do not emit light simultaneously in the same field. The light emission time of a pixel is about several hundred microseconds, and when the number of scanning lines is about 400, it takes about 40 to drive one scanning line.
Since it takes about μ seconds, if the fields that emit light are synchronized between the front and rear scanning lines, flicker will be noticeable in the case of a screen such as full-face emission, but in this embodiment, the fields that emit light will be different between scanning lines. Therefore, the above-mentioned flicker is reduced.

Display data signal [D3, D2, D1, D
When [0] is input, it is designated in the same manner as described above, and the brightness levels 1 and 2 are displayed. At this time,
In the case of the display data signal [0,0,0,1] designating the brightness level 1, the encoder 33 shown in FIG.
0,1] That is, it is converted into a signal that specifies the brightness level 9,
Since the signal is cut over 2 out of 3 fields, a brightness of 1/3 of the brightness 20 of the brightness level 9, that is, a brightness almost equal to the brightness 6 of the brightness level 1 is obtained. Also in the case of the display data [0,0,1,1] designating the brightness level 2, the encoder 33 converts the signal [1,0,1,0], that is, the signal designating the brightness level 10, and the signal is converted. Since it is cut over 2 fields out of 3 fields, the brightness of 1/3 of the brightness 22 of the brightness level 10, that is, the brightness almost equal to the brightness level 7 is obtained.

On the other hand, when the display data signal [D3, D2, D1, D0] input to the data signal processing circuit 32 is a signal designating the luminance levels 4 to 7, the encoder 33 puts the data thinning circuit 34b into the output-enabled state. To do. For example, the data signal processing circuit 32
When the display data signal [D3, D2, D1, D0] input to is a signal [0,1,1,1] designating the brightness level 7, the encoder 3
3 is the data D of the most significant bit and the next most significant bit of the signal
Inverts 3, D2 and converts it to the signal [1,0,1,1]. This signal is a signal that specifies the brightness level 11 as is apparent from Table 1. The signal thus converted is cut by one of three fields by the data thinning circuit 34b. That is, focusing on the scanning line l1, the third
In the operation described above in FIG. 7A, the signal is not cut in the field that has not been cut, that is, in the _Fjth field, and is not cut in the other two fields. Similar thinning processing is performed in the following three fields, and the pixels on the scanning line l1 have a brightness level 2 of 2 at a brightness level of 11
A brightness of 3 is obtained, that is, a brightness equal to the brightness 16 of the brightness level 7. Also in this case, as shown in FIG. 5, the waveform of the effective voltage in the first three fields of the three-frame period,
It has symmetry with the waveform of the effective voltage in the latter three fields. Similar to the case of the above-described operation, the fields for cutting signals are different between the three adjacent scanning lines.

Display data signal [D3, D2, D1,
When D0] is input, the designated brightness levels 4, 5 and 6 are displayed in the same manner as in the above case. At this time, the display data signal [0, 1, 0,
0] is converted into a signal [1,0,0,0], that is, a signal designating the brightness level 8 by the encoder 33 shown in FIG. 2, and the signal is cut in one field out of three fields. , 2/3 of the brightness 18 of the brightness level 8, that is, a brightness equal to the brightness of the brightness level 4 is obtained. Even in the case of the display data signal [0,1,0,1] designating the brightness level 5, the encoder 33 converts the signal into a signal [1,0,0,1], that is, a signal designating the brightness level 9, and the signal Is cut in one of the three fields, so that a brightness of 2/3 of the brightness 20 of the brightness level 9, that is, a brightness 13 substantially equal to the brightness 13 of the brightness level 5 is obtained. Also in the case of the display data signal [0,1,1,0] designating the brightness level 6, it is converted by the encoder 33 into a signal [1,0,1,0], that is, a signal designating the brightness level 10, and the signal Is 1 of 3 fields
Since it is cut in the field, the brightness of brightness level 10 is 22
2/3 of the luminance, that is, a luminance almost equal to the luminance 14 of the luminance level 6 is obtained.

Display data signal [D3, D2, D that specifies brightness level 8 to 15
1, D0] is input to the data signal processing circuit 32,
While the two data thinning circuits 34a and 34b are both stopped, the gate circuit 34c becomes operable and the encoder 3
Since the display data signal [D3, D2, D1, D0] input to 3 is not converted, it is directly sent to the data side switching circuit 22 via the gate circuit 34c, and the modulation voltage V _M corresponding to the signal is sent to the data side. Applied to the electrodes. That is, a display data signal [D3, D2, D1, D0] designating the brightness levels 8 to 15
Is not subjected to thinning processing, and the brightness level according to the data is obtained for each field.

The display data signal [0,0,0,0] designating the brightness level 0 is also directly passed through the gate circuit 34c to the data side switching circuit 22.
And a modulation voltage V _M corresponding to non-light emission is applied to the data side electrode. That is, the display data signal [0,0,0,
The pixel corresponding to [0] does not emit light in each field.

In the above embodiment, three frames are set as a period for one screen display, three fields before and after that are set as one cycle, and the display data signal is thinned out for some fields in the cycle to obtain a low luminance. However, the setting of the above period is not limited to that. That is, a plurality of frames of three frames or more is set as a period for displaying one pixel, and each period of the first half and the latter half is set as one cycle, and low luminance can be displayed by performing similar thinning processing, and application to pixels is possible. It is also possible to secure the symmetry of the effective voltage waveform.

Further, not only the EL display device but also other display devices such as a liquid crystal display device to which a symmetrical driving method is applied can be similarly used.

EFFECTS OF THE INVENTION As described above, in addition to the luminance displayed only by the voltage modulation method, by using the thinning method for cutting the display data in some fields together, the luminance lower than that of the voltage modulation method alone can be obtained. Since the display is performed, even if the number of gradation display steps increases and the number of bits of display data increases, it is not necessary to finely control the pulse width and amplitude of the modulation voltage. It can be done by configuration.

In addition, in the odd fields of the first half and the odd fields of the latter half of the odd frames of 3 or more, the display data is cut in the same order and the same number of fields so that the low brightness display is performed. Since the symmetrical drive is not impaired, image sticking can be avoided and the display quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a thin film EL display device to which a driving method according to an embodiment of the present invention is applied.
FIG. 4 is a block diagram showing the configuration of the data signal processing circuit of the thin film EL display device, FIG. 3 is a timing chart showing the operation of the data signal processing circuit, and FIG. 4 is a display data cut in 2 fields out of 3 fields. Thin film EL when doing
FIG. 5 is a waveform diagram showing the waveform of the effective voltage applied to the pixels on each scanning line of the display device. FIG. 5 is on each scanning line of the thin film EL display device when the display data is cut in one field out of three fields. FIG. 6 is a waveform diagram showing a waveform of an effective voltage applied to a pixel, FIG. 6 is a block diagram showing a schematic configuration of a conventional thin film EL display device, and FIG. 7 is an applied voltage-luminance characteristic of a pixel with burn-in. 6 is a graph showing a comparison between an applied voltage and a luminance characteristic of a normal pixel. 21 …… Display panel, 22 …… Data side switching circuit,
25 ... Scanning side switching circuit, 28 ... Driving circuit, 31 ...
… Drive logic circuit, 32… Data signal processing circuit, D1 to Dx…
… Data side electrode, S1 to Sy …… scanning side electrode

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hiroshi Kishishita 22-22 Nagaike-cho, Abeno-ku, Osaka, Osaka Within Sharp Corporation

Claims (1)

[Claims] 1. A dielectric layer is interposed between a plurality of scanning-side electrodes and a plurality of data-side electrodes arranged in directions intersecting with each other,
A modulation voltage according to display data is applied to the data side electrode, while a writing voltage is applied to the scanning side electrode, and the writing voltage has a first field having one polarity and a second field having the other polarity. In a method of driving a display device in which display of one frame is completed by and the brightness of a pixel is displayed in a plurality of levels according to display data, one screen is displayed by m (m is an odd number of 3 or more) frames, and Only the voltage modulation method that changes the pulse width or amplitude of the modulation voltage according to the data is used to display a predetermined step out of the plurality of levels of brightness to be displayed, while the remaining of the brightness to be displayed The display of the luminance at the stage is performed by using the display data in the voltage modulation method, and the first half and the second half of the m frame period are used. Each period for each minute is set as one cycle, and the reception of the display data is blocked in one or a plurality of sections defined in correspondence with the brightness to be displayed within the cycle and in a field of a predetermined order. A method for driving a display device, comprising: