JPH0748206B2 - Integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an integrated circuit device for easily obtaining a transposed matrix of a square matrix.

[Conventional technology]

Conventionally, when a general-purpose memory is used to obtain a transposed matrix for an n × n matrix, it is necessary to read / write the memory n ² times, and the processing time increases as the number of matrix elements increases. There was a problem that it would be very long.

That is, for a certain matrix, when a transposed matrix is generated using a general-purpose memory, the work of saving each element of the matrix in the memory for temporary store, changing the order, and writing again in the memory This is to do it.

[Problems to be Solved by the Invention]

As described above, when the transposed matrix is generated using the conventional general-purpose memory, the work is complicated, and therefore, there is a problem that the processing time becomes longer as the number of matrix elements increases.

The present invention has been made to solve the above problems, and an object thereof is to obtain an integrated circuit device that can easily generate a transposed matrix in a short time.

[Means for Solving the Problems]

The integrated circuit device according to the present invention has n rows and n columns (n: natural number).
A first storage unit having a structure capable of shifting data in both the row direction and the column direction, and a plurality of storage elements. The second storage means arranged in the same matrix as the plurality of storage elements of the first storage means and the storage elements at the same array position of the first storage means and the second storage means are arranged. A data transfer line to be connected, and a transfer control means for controlling the transfer of data from the storage element of the first storage means to the storage element of the second storage means by the data transfer line.

[Action]

In the present invention, after the row shift and the column shift of the data are sequentially performed in the first storage means, the operation cycle for transferring the data between the first storage means and the second storage means is repeatedly executed. Thus, the transposed matrix can be easily generated.

〔Example〕

FIG. 1 shows a semiconductor integrated circuit device for generating a transposed matrix of a square matrix of 4 rows and 4 columns according to an embodiment of the present invention.

Now the matrix [A] And the transposed matrix [A] ^T is Becomes In this embodiment, 1) to 2) are obtained,
The hardware configuration is as follows.

In FIG. 1, 1 is a first surface that is a portion that stores each element of [A], and 2 is a second surface that is a portion that stores a result of a transposed matrix. _{Reference numeral} 3 is a data transfer line connecting each element a ¹ _ij on the first surface and each element a ² _ij on the second surface, and reference _numeral 4 is a switch for controlling data transfer by the data transfer line 3.

Next, the operation of this embodiment will be described.

1. In the initial state, the above 3) among the elements on the 1st surface 1)
Only the elements marked with a circle in the formula turn on the switch 3.
, The data is transferred to the second surface 2, and the others are set to “off” and the data is not transferred.

2. Next, shift the elements on the first surface in the row direction to obtain the matrix of the following equation.

3. Next, this is shifted in the column direction, and only the elements marked with circles are transferred to the second surface 2 to obtain the matrix of the following equation.

4. Perform row-wise shift and column-wise shift to transfer the required elements, and obtain the matrix of the following equation.

5. Repeat row-wise shift and column-wise shift to transfer the required elements and obtain the matrix of the following equation.

As described above, the transposed matrix is obtained by repeating the row shift, the column shift, and the transfer.

FIG. 2 is a diagram showing a part of the storage elements of the first storage surface 1 or the second storage surface 2 of the apparatus of the above embodiment, in which 21 is an inverter and 22 is transfer of matrix elements in each storage surface. , Switches for φx1, φx2, φy1, φy2 are clocks for in-plane transfer, 23 is two inverters 21 and two switches 22
It is a memory element for one element consisting of.

The physical arrangement of the first surface and the second surface is not particularly limited, but a three-dimensional structure in which active layers (transistors) are laminated, that is, a three-dimensional circuit element is used and is shown in FIG. By arranging the second surface under the first surface as described above, the line connecting the elements can be shortened, and the device can be downsized.

As described above, according to the integrated circuit device of the present invention,
It is composed of a plurality of storage elements for storing each element of data arranged in a two-dimensional matrix of n rows and n columns (n: natural number), in the row direction,
First storage means having a structure capable of shifting data in the column direction, and second storage means having a plurality of storage elements arranged in the same matrix as the plurality of storage elements of the first storage means A data transfer line connecting between the storage elements of the first storage means and the storage elements of the second storage means at the same array position, and the storage element of the first storage means by the data transfer line to the second storage means. Since the transfer control means for controlling the transfer of data to the storage element of the storage means is provided, the processing speed for generating the transposed matrix can be significantly improved compared to the conventional one, and the transposed matrix can be generated in a short time. There is an effect that can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows a part of a memory element on a first memory surface or a second memory surface of the above embodiment. FIG. In the figure, 1 is a first storage surface, 2 is a second storage surface, 11, 21
Is a matrix element, 3 is a data transfer line connecting elements on both storage surfaces, 4 is a switch (transfer control means) for controlling data transfer, 11 is an inverter, 12 is a switch, and 13 is a storage element for one element. is there.

Claims (1)

[Claims] 1. A structure comprising a plurality of storage elements for storing respective elements of data arranged in a two-dimensional matrix of n rows and n columns (n: natural number), and having a structure capable of shifting data in both the row and column directions. A first storage means having the same; a second storage means having a plurality of storage elements arranged in the same matrix state as the plurality of storage elements of the first storage means; the first storage means and the second storage means. And a data transfer line connecting the storage elements at the same array position of the storage means, and the transfer of data from the storage element of the first storage means to the storage element of the second storage means by the data transfer line. An integrated circuit device comprising: transfer control means for controlling.