JPH0748312B2 - Shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a circuit configuration of a static shift register which can be constructed by reducing the number of constituent elements.

<Prior Art> FIG. 7 shows a general circuit configuration of a static shift register conventionally used. 1 to 4 are clock φ
Switch to turn on / off with or, switch 1
It is assumed that switches 4 and 4 are turned on when the level is high, and switches 2 and 3 are turned on when φ is high. Reference numerals 5 to 8 are inverters. FIG. 8 shows the waveforms of the clock φ and the data output Dout. FIG. 9 shows a configuration example of the switches 1 to 4, and FIG. 9 (a) shows a PMOS transistor or
In this example, only one of the NMOS transistors is used. FIG. 9B shows an example in which a PMOS transistor and an NMOS transistor are connected in parallel. In this case, the gate signals of the respective MOS transistors are given potentials of opposite levels.

<Problems to be Solved by the Invention> When a 1-bit static shift register is configured by the above-described conventional technique, four switches and four inverters are required, and 16 switches when configured in CMOS. MOS transistor is required.

If the functions are the same, it is natural that the simpler the circuit is and the smaller the number of constituent elements is, the better.

In the prior art, the duty ratio of the clock φ of the shift register is generally 50% or about 50%. On the other hand, in the present invention, the duty ratio of the clocks φ, is changed and one clock width is set within the range in which the dynamic operation of the shift register is completely possible, whereby the number of constituent elements of the shift register can be reduced. .

<Means for Solving the Problems> The data input is input to the first inverter through the first switch, the output is input to the second inverter through the second switch, and the inverter output becomes the data output, First
In the circuit configuration in which the output of the third inverter whose input is the inverter output is connected to the input of the first inverter through the third switch to form the latch circuit, the first switch is turned on at one signal level of the clock, The second and third switches are turned on when the other signal level of the clock is set, and the second duty is changed by changing the duty ratio of the clock.
The period during which the switch (and hence the third switch) is off is made sufficiently short, and during that period the second inverter (7)
The shift register is configured so that the data output does not change due to the action of the charges stored in the capacitance at the input.

Further, the data input is input to the first inverter via the first switch, the output is input to the second inverter via the second switch, the inverter output becomes the data output, and the second inverter output becomes the input. In the circuit configuration in which the output of the fourth inverter is connected to the input of the second inverter via the fourth switch to form the latch circuit, the first switch and the fourth switch are turned on at one signal level of the clock, and the second switch is turned on. The switch is configured to be turned on at the other signal level of the clock, and the duty ratio of the clock is changed to sufficiently shorten the period during which the first switch (and therefore the fourth switch) is turned off, and the first period is set during that period. A shift register is configured so that the data output is not changed by the action of the electric charge stored in the capacitance at the input of the inverter.

<Operation> The duty ratio of the clock is changed to shorten the period during which the switch is turned off, and the previous state can be stably held by the easily held charge during the off period. As a result
Since the Dout state can be held stably, the feedback circuits (4 and 8 in FIG. 7), which were required in the conventional technique, are not required.

<Embodiment> FIG. 1 shows an embodiment of the present invention, which is the same as the prior art shown in FIG.
Latch circuit that existed individually, that is, switch 2 and inverter 5
In the former stage latch circuit composed of 6 and 6, the switch 4 and the latter stage latch circuit composed of the inverters 7 and 8, only the inverter 7 is constituted instead of the latter stage latch circuit. Instead, as shown in the timing chart of FIG. 2, the period during which the transfer switch 3 is turned off is interposed so that the state of Dout does not change due to the action of the capacitor 9 during the off period of the switch 3.

FIG. 3 shows another embodiment of the present invention, in which the latch circuit (the switch 2 in FIG. 7 in the preceding stage in the prior art in FIG. 7 is used.
And the inverter 5 alone is used instead of the inverters 5 and 6). In this example, a clock in which the OFF period of the transfer switch 1 is sandwiched is used, and even if the switch 1 is in the OFF period, the output state of the inverter 5 is not changed by the action of the capacitor 10. Figure 4 is the third
FIG. 6 is a timing diagram of the figure.

FIGS. 5 and 6 show an example of a clock generation circuit for generating the clock .phi. As shown in FIG. 2 and FIG.

FIG. 5 is composed of an oscillation circuit 20 and a counter 21, and the timing relationship between the input signal CK to the counter 21 and the carry signal CY when the standard IC74161 of hexadecimal counter is used as the counter 21 is also shown in FIG. It was shown to. As a result, it can be seen that φ in FIG. 4 in FIG. 2 can be easily obtained. Each reverse phase clock can be easily realized by creating its inverted signal.

FIG. 6 shows an oscillator circuit 30 and a one-shot multivibrator.
A timing diagram is also shown in the example of the case where the standard IC 74123 is used as the one-shot multivibrator 31 in the clock generation circuit configured by 31. The pulse width τ at the output Q of the one-shot multivibrator 31 is determined by the values of the capacitance C _× 32 and the resistance R _× 33.

In the example of FIG. 5, the output frequency CK of the oscillator circuit 20 must be set higher than the frequency of CY used as a clock by the amount counted by the counter 21.

On the other hand, in the example of FIG. 6, the output frequency of the oscillator circuit 30 and the output Q of the one-shot multivibrator 31 are the same.

Each of FIG. 5 and FIG. 6 has its own characteristics, and it suffices to use the one that is easy to use.
Of course, it does not matter if you configure the.

Although the capacitors 9 and 10 are shown in FIGS. 1 and 3, in the case of actual implementation, the input capacitors of the inverters 7 and 5 may be substituted instead of adding the capacitors.

<Effect> As described above, according to the present invention, the shortening of the switch off period by changing the clock duty ratio is compensated for by the charge held in the capacitance of the circuit, thereby making a circuit component of the static shift register. The number can be reduced to simplify the circuit, and a shift register suitable for being incorporated in an integrated circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing diagram thereof, and FIG. 3 is a circuit diagram of another embodiment of the present invention.
FIGS. 5 (a) and 5 (b) and FIGS. 6 (a) and 6 (b) are circuit diagrams and signal waveform diagrams showing an embodiment of the clock φ, φ generation circuit, and FIG. FIG. 8 is a circuit diagram of a static shift register in the prior art, FIG. 8 is a timing diagram of FIG. 7, FIG. 9 (a) is a configuration example of a switch using one MOS transistor, and FIG. 9 (b) is
It is a configuration example of a switch configured by connecting a PMOS transistor and an NMOS transistor in parallel. 1,2,3: Switch, 5,6,7: Inverter, 9: Capacity

Claims (1)

[Claims] 1. An input terminal, a first switch connected to the input terminal and supplied with an inverted clock, a second switch supplied with a non-inverted clock φ, and between the first switch and the second switch. A first inverter provided, an output terminal, a second inverter provided between the second switch and the output terminal, and either one of the first inverter or the second inverter for forming a latch circuit. A series circuit of a third inverter and a third switch inserted between the output and the input of the inverter, wherein when inserted between the output and the input of the first inverter, the third switch has the non-inverted clock. When φ is given and inserted between the output and the input of the second inverter, the inverted clock is given to the third switch, and the inverted clock is given to the third inverter and the third switch. A serial circuit and a capacitor provided at an input part of the other inverter of the first inverter or the second inverter, and a duty ratio of the clock for controlling the switch, a switch connected to the capacitor, and the latch. The switch included in the circuit is set to be turned off for a sufficiently shorter period than the other switches are turned off.
A shift register characterized in that a data output is held by the action of an electric charge stored in the capacitance.