JPH0748493B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0748493B2 JPH0748493B2 JP62155752A JP15575287A JPH0748493B2 JP H0748493 B2 JPH0748493 B2 JP H0748493B2 JP 62155752 A JP62155752 A JP 62155752A JP 15575287 A JP15575287 A JP 15575287A JP H0748493 B2 JPH0748493 B2 JP H0748493B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive
- interlayer insulating
- opening
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 8
- 239000010408 film Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置及びその製造方法に関し、特に素子
間接続のための配線の構造及びその製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of wiring for connecting elements and a method for manufacturing the same.
従来、半導体装置の基板，電極層等と、Al配線との接続
は、コンタクト用開孔部形後後に、基板の導電層と同一
タイプの不純物をイオン注入法で打込んで、この開孔部
に、新たな不純物層を形成した後に、Si入りのAl膜をス
パッタ法等で形成していた。Conventionally, the connection between the substrate, electrode layer, etc. of the semiconductor device and the Al wiring is made by forming an opening for contact and then implanting an impurity of the same type as the conductive layer of the substrate by an ion implantation method. In addition, after forming a new impurity layer, an Al-containing Si film was formed by a sputtering method or the like.
上述した従来の半導体装置のコンタクト用開孔部の構造
では、開孔部形成後の不純物のイオン注入時には、この
開孔部以外は、絶縁層でおおわれている。このため、開
孔部以外の絶縁層上には、イオン注入によって導入され
る電荷と、絶縁層表面のリークによって散逃する電荷と
の差の分の電荷が蓄積されることになる。In the structure of the contact opening portion of the conventional semiconductor device described above, at the time of ion implantation of impurities after the formation of the opening portion, the insulating layer covers the portions other than the opening portion. For this reason, on the insulating layer other than the opening portion, the charge corresponding to the difference between the charge introduced by the ion implantation and the charge dissipated by the leak on the surface of the insulating layer is accumulated.
この蓄積電荷量がある許容量を越えると、一気に近接し
た開孔部に流れ込もうとし、この時に流れる大電流の発
するジュール熱により開孔部は損傷を受ける。この損傷
は半導体素子のジャンクション特性を悪化させ、半導体
装置のリーク電流の原因となり、信頼性及び歩留を低下
させるという欠点があった。When this accumulated charge amount exceeds a certain allowable amount, it tries to flow into the opening portions that are close to each other at once, and the opening portions are damaged by the Joule heat generated by the large current flowing at this time. This damage deteriorates the junction characteristics of the semiconductor element, causes a leak current of the semiconductor device, and has a drawback of lowering reliability and yield.
本発明の目的は、層間絶縁膜に蓄積される電荷によるコ
ンタクト用開孔部の損傷をなくし、信頼性及び歩留の向
上した半導体装置及びその製造方法を提供することにあ
る。It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, in which damage to a contact opening portion due to charges accumulated in an interlayer insulating film is eliminated and reliability and yield are improved.
第１の発明の半導体装置は、半導体基板上に形成された
層間絶縁膜と、該層間絶縁膜に形成されたコンタクト用
開孔部と、該開孔部を含む前記層間絶縁膜上に形成され
開孔部下に露出した前記基板に接しかつ前記基板表面と
同一導電型の不純物を有する導電性膜を少なくとも含ん
で構成される配線とを有するものである。第２の発明の
半導体装置の製造方法は、半導体基板上の層間絶縁膜に
コンタクト用開孔部を形成する工程と、前記開孔部内に
露出した前記基板表面上および前記開孔部を含む前記層
間絶縁膜上に導電性または半導電性膜を形成する工程
と、前記導電性または半導電性膜上より該導電性または
半導電性膜下に達する条件で前記開孔部下の前記基板表
面と同一導電型の不純物をイオン注入する工程と、少な
くとも前記導電性または半導電性膜を含む配線を形成す
る工程とを含んで構成される。A semiconductor device according to a first aspect of the present invention is formed on an interlayer insulating film formed on a semiconductor substrate, a contact opening formed in the interlayer insulating film, and the interlayer insulating film including the opening. And a wiring that is in contact with the substrate exposed under the opening and that includes at least a conductive film having impurities of the same conductivity type as the surface of the substrate. A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a contact opening portion in an interlayer insulating film on a semiconductor substrate, and the step of forming the contact opening portion on the substrate surface exposed in the opening portion and the opening portion. A step of forming a conductive or semi-conductive film on the interlayer insulating film, and the substrate surface under the opening under the condition of reaching the conductive or semi-conductive film below the conductive or semi-conductive film It is configured to include a step of ion-implanting impurities of the same conductivity type and a step of forming a wiring including at least the conductive or semiconductive film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は、本発明の一実施例の半導体装
置の製造方法を説明するための工程順に示した半導体チ
ップの断面図である。1 (a) to 1 (e) are cross-sectional views of a semiconductor chip showing the order of steps for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
まず第１図（ａ）に示すように、Ｐ型シリコン基板101
上にＰ型ウェル102,N型ウェル103,厚さ約6000Åのフィ
ールド酸化膜104,厚さ約250Åのゲート酸化膜105,多結
晶シリコン等からなるゲート電極106,N型ソース・ドレ
イン107,P型ソース・ドレイン108及びPSG膜等からなる
層間絶縁膜109を周知の方法で形成する。First, as shown in FIG. 1A, a P-type silicon substrate 101
A P-type well 102, an N-type well 103, a field oxide film 104 having a thickness of about 6000Å, a gate oxide film 105 having a thickness of about 250Å, a gate electrode 106 made of polycrystalline silicon or the like, an N-type source / drain 107, P An interlayer insulating film 109 made of a mold source / drain 108 and a PSG film or the like is formed by a known method.
次に、第１図（ｂ）に示すように、周知の方法にて、ソ
ース・ドレインに達するコンタクト用開孔部110,111を
形成後、厚さ約500Åの多結晶シリコン膜112を開孔部11
0,111を含む層間絶縁膜109上全面に形成する。Next, as shown in FIG. 1B, after forming contact openings 110 and 111 reaching the source / drain by a known method, a polycrystalline silicon film 112 having a thickness of about 500 Å is formed into the openings 11.
It is formed on the entire surface of the interlayer insulating film 109 including 0,111.
次に、第１図（ｃ）に示すように、フォトレジストから
なるマスク113Aを用い、Ｎ型ソース・ドレインの開孔部
110には、P+イオン114を、100KeV,ドーズ量５×1015cm
-2の条件で注入する。Next, as shown in FIG. 1C, a mask 113A made of a photoresist is used to open the N-type source / drain holes.
110 is P + ion 114, 100 KeV, dose 5 × 10 15 cm
Inject under -2 condition.
次いで第１図（ｄ）に示すように、他のマスク113Bを用
い、Ｐ型ソース・ドレインの開孔部111には、B+イオン1
16を、50KeV,ドーズ量１×1014cm-2の条件で注入する。Then, as shown in FIG. 1 (d), another mask 113B is used, and B + ions 1 are formed in the openings 111 of the P-type source / drain.
16 is implanted under the conditions of 50 KeV and a dose of 1 × 10 14 cm -2 .
次に、第１図（ｅ）に示すように、厚さ1.0μｍのAl膜
をスパッタリング法で形成した後、周知の方法でパター
ニングを行い、Al膜と多結晶シリコン膜112よりなる配
線118を形成する。Next, as shown in FIG. 1 (e), an Al film having a thickness of 1.0 μm is formed by a sputtering method, and then patterning is performed by a known method to form a wiring 118 composed of the Al film and the polycrystalline silicon film 112. Form.
以下、常法に従ってカバー膜を形成し、ボンディング部
のみ開孔して半導体装置を完成させる。Then, a cover film is formed according to a conventional method, and only the bonding portion is opened to complete the semiconductor device.
このように、本実施例による半導体装置は、コンタクト
用開孔部へのイオン注入時には、ウェハー上全面が、半
導電性膜である多結晶シリコン膜112でおおわれている
ため、イオン注入による電荷の蓄積が防止され、従来の
構造による半導体装置に比べ良好な素子特性と歩留を得
ることができる。As described above, in the semiconductor device according to the present embodiment, since the entire surface of the wafer is covered with the polycrystalline silicon film 112 that is a semiconductive film at the time of ion implantation into the contact openings, the charge due to the ion implantation is Accumulation is prevented, and good element characteristics and yield can be obtained as compared with a semiconductor device having a conventional structure.
尚、上記実施例においては電荷蓄積防止用の膜とし、半
導電性膜である多結晶シリコン膜を用いた場合について
説明したが、導電性のシリサイド膜等を用いてもよい。In the above embodiments, the case of using a polycrystalline silicon film which is a semi-conductive film as the film for preventing charge accumulation has been described, but a conductive silicide film or the like may be used.
すなわち、第１図（ｂ）に示した多結晶シリコン膜112
の代わりに、厚さ約3000Åのタングステンシリサイド膜
を形成し、この上から、実施例と同様に、フォトレジス
トをマスクとして、Ｐ型ソース・ドレイン上の開孔部に
はB+を、150KeV,ドーズ量３×1013cm-2の条件で、また
Ｎ型ソース・ドレイン上の開孔部には、P+を、150KeV,
ドーズ量１×1016cm-2の条件で注入する。次いで、900
℃のN2雰囲気中で、熱処理を行ったのち、周知の方法に
てタンクズテンシリサイド膜をパターニングして配線と
して利用する。That is, the polycrystalline silicon film 112 shown in FIG.
Instead of this, a tungsten silicide film having a thickness of about 3000 Å is formed, and B + and 150 KeV are formed in the openings on the P-type source / drain from above, using the photoresist as a mask, similarly to the embodiment. Under the condition that the dose amount is 3 × 10 13 cm -2 , P + is added to the openings on the N-type source / drain at 150 KeV,
Implant at a dose of 1 × 10 16 cm -2 . Then 900
After performing a heat treatment in a N 2 atmosphere at ℃, the tanksten silicide film is patterned by a known method to be used as a wiring.
この場合も、導電膜であるタングステンシリサイド膜が
イオン注入による電荷の蓄積を防止し、製造された半導
体装置は良好な特性を示す。Also in this case, the tungsten silicide film, which is a conductive film, prevents charge accumulation due to ion implantation, and the manufactured semiconductor device exhibits good characteristics.
以上説明したように本発明は、コンタクト用の開孔部に
不純物をイオン注入するに際し、導電性又は半導電性の
被膜を開孔部を含む層間絶縁膜上に形成しておくことに
より、イオン注入による電荷の蓄積が防止され、この電
荷の蓄積に起因する接合のリーク不良，コンタクト部の
破壊を防止することができ、特性及び歩留の良い半導体
装置を製造できるという効果がある。As described above, according to the present invention, when the impurities are ion-implanted into the opening for contact, by forming a conductive or semi-conductive film on the interlayer insulating film including the opening, It is possible to prevent the accumulation of electric charges due to the injection, prevent the leakage failure of the junction and the destruction of the contact portion due to the accumulation of the electric charges, and it is possible to manufacture a semiconductor device having excellent characteristics and yield.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。 101…Ｐ型シリコン基板、102…Ｐ型ウェル、103…Ｎ型
ウェル、104…フィールド酸化膜、105…ゲート酸化膜、
106…ゲート電極、107…Ｎ型ソース・ドレイン、108…
Ｐ型ソース・ドレイン、109…層間絶縁膜、110,111…開
孔部、112…多結晶シリコン膜、113A,113B…マスク、11
4…P+イオン、116…B+イオン、118…配線。1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 101 ... P-type silicon substrate, 102 ... P-type well, 103 ... N-type well, 104 ... Field oxide film, 105 ... Gate oxide film,
106 ... Gate electrode, 107 ... N-type source / drain, 108 ...
P-type source / drain, 109 ... Interlayer insulating film, 110, 111 ... Opening, 112 ... Polycrystalline silicon film, 113A, 113B ... Mask, 11
4… P + ions, 116… B + ions, 118… wiring.
Claims (2)
該層間絶縁膜に形成されたコンタクト用開孔部と、該開
孔部を含む前記層間絶縁膜上に形成され開孔部下に露出
した前記基板に接しかつ前記基板表面と同一導電型の不
純物を有する導電性膜を少なくとも含んで構成される配
線とを有することを特徴とする半導体装置。1. An interlayer insulating film formed on a semiconductor substrate,
A contact opening formed in the interlayer insulating film and an impurity of the same conductivity type as the surface of the substrate that is in contact with the substrate formed on the interlayer insulating film including the opening and exposed under the opening are contacted. And a wiring including at least the conductive film.
開孔部を形成する工程と、前記開孔部内に露出した前記
基板表面上および前記開孔部を含む前記層間絶縁膜上に
導電性または半導電性膜を形成する工程と、前記導電性
または半導電性膜上より該導電性または半導電性膜下に
達する条件で前記開孔部下の前記基板表面と同一導電型
の不純物をイオン注入する工程と、少なくとも前記導電
性または半導電性膜を含む配線を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。2. A step of forming a contact opening portion in an interlayer insulating film on a semiconductor substrate, and a conductive property on the substrate surface exposed in the opening portion and on the interlayer insulating film including the opening portion. Or a step of forming a semi-conductive film, and ion-implanting an impurity of the same conductivity type as that of the substrate surface under the opening under the condition of reaching from the conductive or semi-conductive film to below the conductive or semi-conductive film. A method of manufacturing a semiconductor device, comprising: an implanting step; and a step of forming a wiring including at least the conductive or semi-conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62155752A JPH0748493B2 (en) | 1987-06-22 | 1987-06-22 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62155752A JPH0748493B2 (en) | 1987-06-22 | 1987-06-22 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63318753A JPS63318753A (en) | 1988-12-27 |
| JPH0748493B2 true JPH0748493B2 (en) | 1995-05-24 |
Family
ID=15612642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62155752A Expired - Lifetime JPH0748493B2 (en) | 1987-06-22 | 1987-06-22 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748493B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4224733A (en) * | 1977-10-11 | 1980-09-30 | Fujitsu Limited | Ion implantation method |
| JPS5583268A (en) * | 1978-12-19 | 1980-06-23 | Nec Corp | Complementary mos semiconductor device and method of fabricating the same |
| JPS55166958A (en) * | 1979-06-15 | 1980-12-26 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5658229A (en) * | 1979-10-16 | 1981-05-21 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
-
1987
- 1987-06-22 JP JP62155752A patent/JPH0748493B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63318753A (en) | 1988-12-27 |
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