JPH0748633B2 - Amplitude and group delay adjustment device for audio - Google Patents

Description

The present invention relates to an audio amplitude and group delay adjusting device, for example, for an audio signal such as a PCM audio signal, the amplitude and group delay amount for each frequency band are changed. The present invention relates to an amplitude and group delay adjusting device capable of being taken out.

(Prior art) The level difference and time difference (phase difference) of the sound given to the listener's both ears are greatly related to the sense of direction of the listener in the stereoscopic sound field and the localization of the sound image. Is well-known, and in order to change the stereoscopic effect and the localization of the sound image that a listener feels in a stereoscopic sound field that is conventionally formed using an electroacoustic converter, an audio signal supplied to the electroacoustic converter is used. Although it has been attempted to change the amplitude and phase, analog circuits are used by a phase shifter composed of a combination of circuit elements such as resistors, capacitors and coils that have been most commonly used in the past. Since it is necessary to use a phase shifter with an expensive and complicated structure in order to finely change the phase of an audio signal in a signal form, such means should be adopted in a consumer device. Is troubled It's difficult.

(Problems to be Solved by the Invention) As one means for solving the above problems, for example, a digital filter capable of performing amplitude / phase control may be used, but amplitude / phase control is performed. A digital filter that is conventionally known as a digital filter that can be used, for example, that having the configuration disclosed in Japanese Patent Laid-Open No. 59-112715 has a real number in order to independently control the amplitude and the phase. Part and imaginary part are calculated separately and the FIR digital filter operation is performed using the filter coefficient to construct the FIR digital filter with the desired characteristics. Therefore, there are many problems that the configuration becomes complicated and real-time calculation is difficult.

(Means for Solving Problems) The present invention is directed to a characteristic input section for designating a desired frequency characteristic and a desired group delay characteristic, and an FIR digital signal corresponding to frequency characteristic information designated by the characteristic input section. Filter operation,
Digital filter operation means for performing all-pass IIR digital filter operation according to the group delay information specified by the characteristic input section, and frequency characteristic information and group delay information specified by the characteristic input section According to the above, each filter coefficient is independently given, and the FIR digital filter and the group delay amount in each divided pass band in all bands divided into a plurality of bands are controlled to be equal in all bands. All-pass IIR with constant group delay
An audio amplitude and group delay adjusting device comprising a digital filter and a control means for operating the digital filter in cascade.

(Embodiment) Hereinafter, specific contents of the audio amplitude and group delay adjusting device of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram of an embodiment of an audio amplitude and group delay adjusting device of the present invention, and FIG. 2 is a diagram showing a plurality of frequency bands for which the amplitude and the group delay amount are to be adjusted. Characteristic input section CID provided with a plurality of characteristic variable selection switches for adjusting the amplitude and group delay amount, and the amplitude adjustment state and group delay amount state are displayed for each frequency band in multiple frequency bands. FIG. 4 is a front view of the display unit DPA configured as described above, FIG. 3 is a block diagram showing an example configuration of a digital signal processor DSP, and FIG.
FIG. 12 and FIG. 12 are block diagrams showing the configuration of a filter to be obtained by the operation of the DSP, and FIG. 5 is a timing chart used for explaining the operation of the audio amplitude and group delay adjusting apparatus of the present invention. Fig. 7 is a flow chart for explaining the operation of the central processing unit (CPU), Fig. 7 is a diagram for explaining the characteristics of the all-pass IIR digital filter, and Fig. 8 is the pole and zero ( FIG. 9 shows an example of a memory map in the coefficient setting unit and the coefficient memory.
FIG. 10 is a block diagram showing a specific configuration of the multiplexer and the transmitter.

In FIG. 1, which shows a block diagram of an embodiment of an audio amplitude and group delay adjusting apparatus of the present invention, 1 is an input terminal of a digital signal, and this input terminal 1 is provided with an audio amplitude and group delay. In the adjusting device, an audio signal (hereinafter simply referred to as a digital signal) which is a digital signal of a predetermined format to which a predetermined amount of amplitude change and a predetermined amount of group delay should be given is supplied.

The digital signal supplied to the above-mentioned input terminal 1 is a receiving unit.
Demodulated by RD. The PLL is a phase locked loop and this phase locked loop PLL is
It is used to synchronize the phase of the clock in the digital data obtained by demodulation with the clock generated in the receiving unit RD. It goes without saying that the input signal may be a serial signal or a parallel signal depending on the configuration of the device.

The signal demodulated by the receiving unit RD, for example, the NRZ signal,
Supplied to digital signal processors DSP1 and DSPr1. Digital signal processor DSP described above
As 1, DSPr1 and digital signal processors DSPl2 and DSPr2 described later, for example, those having a configuration as shown in FIG. 3 can be used.

The digital signal processors DSP1, DSPl2, DSPr1, DSPr2 shown in FIG. 1 and the digital signal processor (DSP) specifically shown in FIG.
l, DSPr), so that the correspondence between the two becomes clear,
Corresponding input / output terminals in both cases are given the same symbols a to h.

The digital signal processor DSP1 described above is
Performs an operation that functions as a FIR digital filter by performing FIR digital filter operation to realize the frequency characteristic set in the characteristic input section CID for the left channel signal in the stereo signal, and also the digital signal processor The DSPr1 performs FIR digital filter calculation to realize the frequency characteristic set in the characteristic input section CID for the right channel signal in the stereo signal, and then FIR
It acts to act as a digital filter, while the digital signal processor DSPl2
Controls the group delay amount equally in each divided pass band in all bands divided into a plurality of bands to realize the group delay characteristic set in the characteristic input section CID for the left channel signal in the stereo signal. Then, the all-pass IIR digital filter operation in which the group delay amount in the entire band is constant is performed to perform an operation that functions as an all-pass IIR digital filter, and the digital signal processor DSPr2 , Performs an all-pass IIR digital filter operation to realize the group delay characteristic set in the characteristic input section CID for the right channel signal in the stereo signal, and operates so as to function as an all-pass IIR digital filter. However, the above digital signal processors DSP1, DSPl2, DSPr1, DSPr2, etc. have the same configuration and use the same operation mode. Therefore, in the following description, when describing common items to each of the digital signal processors DSP1.DSPl2, DSPr1, DSPr2, etc. described above, the digital signal processor DSP will be referred to without distinguishing between them. The explanation is given with the subscripts 1, l2, r1, r2 omitted.

In order to specify the desired frequency characteristic and group delay characteristic, the characteristic input unit CID is provided with the amplitude and group delay amount of each frequency band in a plurality of frequency bands as shown in (a) of FIG. Multiple selection switches S1 for adjusting characteristics
To S4 and amplitude / delay changeover switches S5 to S8 are provided.

In the display unit DPA shown in FIG. 2B, for example, as shown in the figure, a plurality of display elements (for example, light emitting diodes) are provided for each of a plurality of frequency bands.
Are arranged, and the amplitude and group delay amount for each frequency band set in the characteristic input section CID can be easily known by the operating state of the display element (for example, the blinking state of the light emitting diode). Has been made possible.

In FIG. 2 (b), f1, f2 ... Fn represent center frequency values in a plurality of different frequency bands, and the center frequency values f1, f2.
The circles vertically arranged above n are display elements. Then, in FIG. 2B, when the display element is a light emitting diode, those indicated by black circles indicate a light emitting state, and those indicated by white circles indicate an off state. Although illustrated in such a display mode, the display unit DPA shows the amplitude and group delay amount for each frequency band set in the characteristic input unit CID as illustrated in FIG. 2B. Can be displayed.

The central processing unit CPU includes a read-only memory ROM and a random access memory RAM, and the group delay amount corresponding to the amplitude of each frequency band set in the characteristic input unit CID and the group delay amount, A digital signal processor DS as described above for producing an input digital signal supplied to an audio amplitude and group delay adjuster.
It controls so that a predetermined digital filter operation in P is performed, makes a predetermined display on the display unit DPA, and controls the operation of each unit of the audio amplitude and group delay adjustment device. .

Further, in FIG. 1, STD is a serial code transfer unit, S
CG is a clock signal generation circuit, MPX is a multiplexer, T
D is a transmitter, and 2 is an output terminal.

In FIG. 3 showing a concrete configuration example of the digital signal processor DSP, SDI is an input circuit for serial data, IB is an input buffer, NC-RAM is a coefficient RAM, TB.
Is a transfer buffer, PCD is a parameter controller, P-RAM is a program RAM, SDO is a serial data output circuit, SCI is a serial code interface, and D-RAM is data R.
AM.

FN-ROM is a constant memory ROM, MUL is a multiplier, ACC
Is an accumulator, REG is a shift register, and OB is an output buffer.

The digital signal processor DS shown in FIG.
ROM for constant memory in P (FN-ROM) and multiplier MUL
Since the components including the accumulator ACC, the register REG with shifter, and the output buffer OB are well-known circuit configurations and are not directly related to the description of the present invention, a detailed description thereof will be omitted. Omit it.

The program RAM (P-RAM) described above stores in advance a program to be executed by the digital signal processor DSP, and stores a data such as the multiplication coefficients a10 to bn2 to function as a coefficient memory ( NC-RAM)
To the multiplier MUL of these data.

The serial code interface SCI is provided with a serial code input terminal c and a serial code output terminal d, and the serial code input terminal c is supplied with a clock signal and a synchronization signal (LRCK, LRCK bar) supplied from the serial code timing input terminal e. Data (SD, SD ′)
From the reserial code output terminal d
D, SD ') is output.

The parameter control unit PCD described above stores the data from the serial code interface SCI in the program RAM (P-
RAM) and transfer buffer TB are identified and sent,
The control signals Ts and Tw that specify the transfer timing and the number of transfers are output from the transfer buffer TB. g is the parameter control unit PCD
This is the trigger input terminal of.

When the trigger (synchronization signal) input is supplied to the trigger input terminal g from the outside, the parameter control unit PCD can generate the control signal Ts whose transfer timing is determined by the trigger input. Although it is configured as described above, the parameter control unit PCD does not have to supply the trigger input from the outside to the above-mentioned terminal g.
It has a function that can be triggered by data (SD, SD ').

The two digital signal processors DSPl, DSPr used in the audio amplitude and group delay adjusting device shown in FIG. ), The above-mentioned terminal g is not used.

The serial data input circuit SDI converts the audio input data from the serial data input terminal a from serial to parallel,
The data is supplied to the data RAM (D-RAM) via the input buffer IB. In the figure, f is a data clock signal BCLK and a channel identification signal LR supplied to the serial data input circuit SDI and the serial data output circuit SDO to determine the timing of serial data input and serial data output.
Input terminal for CK.

FIG. 4 is a digital signal diagram of the audio amplitude and group delay adjusting apparatus of the present invention shown in FIG.
An IIR digital signal that obtains the filter characteristics that are to be obtained by the arithmetic operation of the processor DSPl2 and the arithmetic operation of the digital signal processor DSPr2.
It is a diagram showing a filter in the form of a specific circuit configuration,
Further, FIG. 12 shows the arithmetic operation of the digital signal processor DSP1 and the arithmetic operation of the digital signal processor DSPr1 in the audio amplitude and group delay adjusting apparatus of the present invention shown in FIG. FIG. 3 is a diagram showing in a concrete circuit configuration the FIR digital filter capable of obtaining the filter characteristic to be obtained, and in FIG. 4 and FIG. 12, 3 is an input terminal and 4 is a unit delay. An operator, 5 is a multiplication circuit, 6 is an addition circuit, and 7 is an output terminal.

The filters shown in FIG. 4 described above have the same structure.
The biquad filter units FLT1 to FLTn are cascade-connected in n stages to form an all-pass IIR filter configuration.

By the way, the transfer function HA (Z) of the all-pass IIR digital filter as shown in FIG. 4 is expressed by the following equation as well known.

In the case of the all-pass type IIR digital filter, the coefficient ai2 among the coefficients of the digital filter can be set to 1. Also, in the all-pass type IIR digital filter, it is shown in FIG. As shown in P on the Z plan
Pole of 1, P, 2, P3 ... Pn−1, Pn respectively overlaps with zero (mirror), and as shown in FIG. It is known that each biquad filter unit (unit filter) monotonically decreases with respect to (normalized frequency ω), and the group delay characteristic τg (ω) described above is τg (ω) = − dθ (ω ) / Dω, it is defined as Gd1, Gd2 ... Gdn in (a) of FIG.
The group delay characteristics shown by are for each biquad filter FLT1
~ Obtained for FLTn.

That is, the angular frequency θp1 of the pole P1 of the biquad filter unit FLT1 can be made to correspond to the center frequency f1 of the first band frequency of the group delay characteristic shown in (a) of FIG. Similarly, each bike quad filter section FLT2 to FLTn
The angular frequencies θp2 to θpn of the respective poles P2 to Pn can be made to correspond to the center frequencies f2 to fn of the second to nth band frequencies.

Now, the central angular frequencies θp1 and θp2 in multiple frequency bands
[Theta] pn so that the difference between adjacent angular frequencies becomes equal, that is, the following equation (1) [theta] p2- [theta] p1 = [theta] p3- [theta] p2 = [theta] p4- [theta] p3 = ... = [theta] pn- [theta] p (n-1) ... Selection is made to satisfy (1) and each pole P1, P2 ...
… The distances r1, r2… rn connecting Pn to the center are all made equal as shown in the following equation (2) r1 ＝ r2 ＝ r3 ＝ …… ＝ rn… (2), and each pole P1, P2… … Pn
Setting the digital filter coefficients in all the all-pass IIR digital filters so that the group delay amounts of all the all-pass IIR digital filters are all the same while keeping the , The group delay amount τg becomes a constant state like τgt in FIG. 7,
The total group delay characteristics of the N number of all-pass IIR digital filters are made substantially flat, and the group delay characteristics having no unevenness are obtained over the entire frequency band.

Regarding the all-pass type IIR digital filter configured as shown in the fourth diagram, as described above, each of the biquad filter units FLT1 to FLTn that can obtain the group delay characteristic in the state without unevenness over the entire frequency band. As an example of the filter coefficient, the case where n = 10 is shown as follows.

FLT filter coefficient 1.a10 = 0.2279777008 a11 = -0.9435036489 a12 = 1.0000000000 b11 = 0.9435036489 b12 = -0.2279777008 2.a20 = 0.2279540615 a21 = -0.8539270229 a22 = 1.0000000000 b21 = 0.8539270229 b22 = -0.2279540615 3.a30 = 0.22868416307 a31 = -0.6 a32 = 1.0000000000 b31 = 0.6855207745 b32 = -0.2286841630 4.a40 = 0.2309500374 a41 = -0.4528444485 a42 = 1.0000000000 b41 = 0.4528444485 b42 = -0.2309500374 5.a50 = 0.2332873199 a51 = -0.1723049176 a52 = 1.0000000000 b51 = 0.1723049176 b52 = -0.23333 a60 = 0.2355608216 a61 = 0.1265036337 a62 = 1.0000000000 b61 = -0.1265036337 b62 = -0.2355608216 7.a70 = 0.2399302297 a71 = 0.4180445346 a72 = 1.0000000000 b71 = -0.4180445346 b72 = -0.2399302297 :: 10.a10,0 = 0.2566032823 a10,1 = 0.99913427. a10,2 = 1.000000000 b10,1 = −0.9991342740 b10,2 = −0.2566032823 FIR digital filters represented as a concrete configuration as shown in FIG. 12 are well known. As described above, it is possible to variably control the frequency characteristics (amplitude) in a linear phase. FIR filter digital filter coefficients a1 to a
p is stored in advance in the read-only memory ROM,
It is adapted to be changed according to the designation in the above-mentioned characteristic input unit CID.

In the audio amplitude and group delay adjusting apparatus of the present invention, the signal amplitude adjustment and the group delay characteristic switching are performed by switching a program of a filter which substantially constitutes the digital signal processor DSP, or The control can be performed by switching the coefficient data corresponding to the coefficients a10 to bn2 and a1 to ap of the filter that substantially constitutes the signal processor DSP, and the control and amplitude of the switching operation of the group delay characteristics described above. The switching operation is controlled by the central processing unit CPU, but in the following description, the group delay characteristics and the switching of the amplitude are controlled by the coefficients a10 to bn2, a1 of the filter which substantially constitutes the digital signal processor DSP. The description is given by taking as an example the case where the coefficient data corresponding to ~ ap is changed.

Now, in the central processing unit CPU described above, based on the control signals from the read-only memory ROM and the random access memory RAM, the program and / or all the filter coefficient data are sent to switch the group delay characteristics and the amplitude, or It is possible to send the filter coefficient data for each single frequency band to switch the group delay characteristics and amplitudes described above, and finally to switch the group delay characteristics and amplitudes for all frequency bands. This method is suitable for forming a FIR digital filter by FIR digital filter operation, and the switching method like the latter mentioned above is suitable for forming an IIR digital filter by IIR digital filter operation. .

Next, the operation when the IIR digital filter is constructed by the IIR digital filter operation performed by the digital signal processors DSPl2 and DSPr2 according to the flowchart shown in FIG. 6 by the latter switching method described above will be described. It is as follows. First, the characteristic changing routine is started at the start, and the band counter I is set (step 100 in FIG. 6). Band
The set value of I is read (step 101), it is judged whether or not the change is made (step 102), and if YES, the characteristic coefficient is selected (step 103) and written in the coefficient setting section (step 104). , Switching pulse is generated (step 105)
If NO, the subcode output from the receiving unit RD is read, sent to the transmitting unit TD as necessary, and the sampling frequency is displayed on the display unit {code de in (b) of FIG. 2} of the display unit DPA. fs, presence / absence of emphasis, phase-locked loop PL
Information such as loss of synchronization of L is displayed (step 106).

Then, the band counter I is incremented (step 10
7) If the number of bands does not exceed N, the process returns to step 101, and if the number of bands exceeds N, the process returns to step 100 (step 1).
07 YES).

In this way, the coefficient of the digital filter is rewritten for each unit filter provided for each frequency band. When the characteristic variable selection switch in the characteristic input section CID is not selected, the corresponding unit filter FLTi
The digital filter coefficient of ai0 = 1, ai1 = 0, ai2 = 0, b
i1 = 0, bi2 = 0, and the unit filter has filter characteristics such that the group delay amounts at the input and output are equal.

As a result, one digital signal processor DS
The group delay amount in multiple all-pass IIR digital filters configured by the operation of P (each of DSPl2 and DSPr2) is the group delay amount in each frequency band It can be calculated as something that smoothly connects to the group delay amount in.

A more specific description is as follows. That is, when the central processing unit CPU sends the coefficient data of the digital filter from the serial code input terminal c of the digital signal processor DSPl2 via the serial transfer unit STD of FIG. The filter coefficient data is sent to the transfer buffer TB via the serial code interface SCI and the parameter control unit PCD shown in FIG.

FIG. 9A shows an example of the map of the transfer buffer TB. In FIG. 9A, the coefficient data a10 of the digital filter is stored in the storage parts of addresses 0 to 3, and , The coefficient data a11 of the digital filter is stored in the memory portions of the addresses 4 to 7, the coefficient data of the digital filter is sequentially stored in the memory portions designated by the sequential addresses, and the address {4 × (5n
−1)} to {4 × (5n−1) +3} indicates an example in which the coefficient data bn2 of the digital filter is stored in the storage portion specified.

Further, FIG. 9B shows an example of the map of the coefficient RAM (NC-RAM). In FIG. 9B, the coefficient data a1 of the digital filter is stored in the storage portion of addresses 0 to 1.
0 is stored, and the coefficient data a11 of the digital filter is stored in the memory portions of the addresses 2 to 3, so that the coefficient data of the digital filter is sequentially stored in the memory portion specified by the sequential addresses. The coefficient data bn2 of the digital filter is stored in the storage portion designated by the addresses {2 × (5n−1)} to {2 × (5n−1) +1}.
Shows an example in which is stored.

A map of the transfer buffer TB illustrated in FIG. 9A and the coefficient RAM (NC-RAM) illustrated in FIG. 9B.
The address of the memory part where the coefficient data of the same digital filter should be stored is different from that of the map in that the transfer is performed when the coefficient data of each digital filter is 32 bits (8 bits x 4). This is because the buffer TB is shown as an example, assuming that the buffer TB has a storage capacity of 8 bits per address and the coefficient RAM (NC-RAM) has a storage capacity of 16 bits per address.

The above-mentioned address is designated by the third serial data of the 4-byte instruction set as shown in (i) of FIG. 5, and the coefficient data of the above-mentioned digital filter is shown in (i) of FIG. It is designated by the fourth serial data of the 4-byte instruction set as shown in.

When the word length of the coefficient data of the digital filter is 32 bits as in the above example, the coefficient data of the digital filter is sent every 8 bits in four times. In addition,
The first code 1 and the second code 2 of the serial data of the 4-byte instruction set as shown in FIG. 5 (i) are for chip enable. It is used to distinguish whether the signal processor DSP is selected or not.

The CRS bar in (h) of FIG. 5 is a start signal indicating the start of serial code transfer. The start signal CRS bar for starting the serial code transfer is from the serial code transfer section STD to the input terminal of the serial code interface SCI. applied to h.

The serial code interface of the digital signal processor DSPl2 for the left channel that performs the IIR operation described above is connected to the output terminal d of the SCI at the serial code interface of the digital signal processor DSPr2 for the right channel that performs the IIR operation. Since the input terminal c of the SCI is connected, the filter coefficient data is also sent to the digital signal processor DSPr2 for the right channel which performs IIR operation.

The coefficient data of the digital filter sent to the transfer buffer TB of the digital signal processor DSPl2, DSPr2, along with the coefficient data of the digital filter already sent by then, is triggered by the external synchronization signal to generate the coefficient RAM ( Each word is sent to the NC-RAM) in units of 5 words. Then, write the coefficient data of the digital filter into the coefficient RAM (NC-RAM), step 10 in FIG.
Next to 4, the sync signal is coded from the serial transfer unit STD.
1 and code 2 are supplied in the encoded state (step 105).

In addition, the digital signal processor DSPl2,
The clock signal that determines the program instruction cycle of the DSPr2 is a clock signal fg {fifth (fifth) that is 128 times the frequency of the sampling pulse generated in the receiving unit RD.
(G) in the figure is used, and its clock signal fg is supplied to the clock input terminal f of the digital signal processors DSPl2 and DSPr2.

SCG in FIG. 1 is a clock signal generation circuit that generates a clock signal having a frequency corresponding to the transfer speed of the serial transfer unit STD. The clock signal generated by the clock signal generation circuit SCG described above is a digital signal. It is supplied to the input terminal e of the serial code timing signal of the serial code interface SCI of the processor DSP.

Now, in FIG. 5 showing the timing chart of the audio amplitude and group delay adjusting apparatus (system) shown in FIG. 1, the digital signal processor DSPl2 takes in the coefficient data of the digital filter at the time t1 and Outputs the calculation result of the coefficient data of the previous digital filter, and outputs it from the digital signal processor DSPr2 together with the multiplexer MPX in FIG. 1 for time division signals of the left and right two channels {the format of (a) in FIG. 5). }, The transmission unit TD is converted to a digital audio interface format in the transmission unit TD having the audio data modulation function and the transmission function, and then sent to the output terminal 2.

The digital data transmitted from the input terminal 1 in the digital audio interface format is
The serial digital audio data demodulated into NRZ by the receiving unit RD ((a) in FIG. 5) is applied to each input terminal a of the digital signal processors DSP1 and DSPr1 that perform FIR arithmetic operation, and In the receiving unit RD described above, the timing signals such as the channel identification signals LRCK and WCK are demodulated, and the demodulated signals are sent to the respective digital signal processors DS.
By supplying the components P1 to DSPl2, DSPr1 to DSPr2 and the transmission unit TD, the above-mentioned components can operate in synchronization with each other.

Digital signal processor DSP for FIR operation
1, DSPr1 also has a digital
As with the signal processors DSPl2 and DSPr2, the FIR
Digital signal for the left channel that performs arithmetic operation
The output terminal d of the serial code interface SCI of the processor DSP1 is connected to the input terminal c of the serial code interface SCI of the digital signal processor DSPr1 for the right channel that performs the FIR arithmetic operation. The filter coefficient data is also sent to the digital signal processor DSPr1 for the right channel which performs the calculation.

FIG. 10 shows a specific configuration example of the multiplexer MPX and the transmission unit TD. The changeover switches SWl and SWr in the multiplexer MPX are sequentially turned on and off in response to the channel identification signal LRCK, so that the left channel The signal and the signal of the right channel are sequentially and alternately supplied to the transmission unit TD on the time axis. INV in the figure is an inverter.

In the above description of the embodiments, the all-pass IIR digital filter has been described as having a configuration in which n biquad filter sections having the same configuration as shown in FIG. 4 are connected in cascade. In carrying out the invention, as an all-pass IIR digital filter, a configuration in which n biquad filter sections having the same configuration are connected in parallel may be used, and as described above, n biquad filter sections having the same configuration may be used. When the biquad filter units are connected in parallel, an all-pass IIR digital filter can be realized by scaling the digital filter coefficient data while paying attention to overflow.

Further, in the description of the embodiments so far, the all-pass IIR digital filter in which the second-order IIR is configured as a unit filter has been described as an example, but the present invention is not limited to this. A pass-type IIR digital filter may be used, or a mixed configuration using a first-order IIR and a second-order IIR as a unit filter may be used. It goes without saying that the configuration mode can be modified and used.

Furthermore, the digital signal processor to be used
The DSP is not limited to the configuration as described above, and the digital signal processor DSP is merely one embodiment of the programmable digital signal arithmetic means. Further, in the above embodiments, the system of digital signal input and digital signal output has been described, but the implementation of the present invention is not limited to such a system form, for example, an AD converter at the input end, It goes without saying that the present invention can be applied to a system in which a DA converter is used on the output side and analog signal input and analog signal output are performed.

FIG. 11 is a flow chart when the group delay characteristics are switched in a group delay characteristic switching mode different from the group delay characteristic switching mode already described with reference to FIG. Referring to the flow chart shown in Fig. 11,
The switching operation performed under the control of the central processing unit CPU will be described. First, the characteristic changing routine is started at the start, and the band counter I is set (step 200 in FIG. 11). The set value of the band I is read (step 201), the band counter I is incremented (step 202), and if the value of the band counter I does not exceed N, the process returns to step 201 like NO in step 203, The set value of the band I is read, and when the value of the band counter I exceeds N (YES in step 203), it is determined whether the change is made (step 204). If YES, the output data is gradually output. Filter coefficients that level down to ano, an1, an
2 is sent to the final stage filter FLTn in FIG. 4 several tens of times. The filter coefficient is a constant damping ratio (eg 0.9)
Multiply by to get.

Next, the optimum characteristic program for the above change is selected (step 206) and sent to the digital signal processor DSP (step 207) to start the coefficient switching (step 208), and the output data is gradually leveled. The filter coefficients ano, an1, an2 that increase, that is, the filter coefficients obtained by multiplying the default value by a constant damping ratio (for example, 0.9) one after another are applied to the final stage filter FLTn in FIG. Send (step 209). When the fade-in is completed and the preset value is restored, the process returns to step 200.

If there is no characteristic change (NO in step 204), the same display as in step 106 in the flowchart shown in FIG. 6 is performed (step 210) and the process returns to step 200.

When the fade-in and fade-out operations are performed when adjusting the amplitude, switching noise is less likely to occur. Further, by using a part of the all-pass IIR digital filter as an attenuator, the calculation step for the attenuator can be omitted, so that the speed can be increased.

Referring to FIG. 1 showing an embodiment of the audio amplitude and group delay adjusting apparatus of the present invention, a component portion FIRl for adjusting the amplitude, that is, a FIR filter is constructed by performing FIR calculation. The operating digital signal processor DSP1 and the component IIRl for adjusting the amount of group delay, that is, the digital signal processor DSPl2 that operates to perform an IIR operation to form an IIR filter are cascaded. And a component part FIRl for adjusting the amplitude, that is, a digital signal processor DSPr1 that operates to perform an FIR operation to form an FIR filter, and an amount of group delay adjustment. IIRr, that is, the digital signal processor DSPr2 that operates to perform IIR operation and configure an IIR filter is cascaded. Since the adjustment of the amplitude and the adjustment of the phase (group delay amount) are controlled by completely different components, the amplitude and the group delay amount can be adjusted by any combination with a small number of filter coefficients. By using the FIR filter for adjusting the amplitude as described above, and using the IIR filter for adjusting the group delay amount, for example, only the IIR filter is obtained. Therefore, the problem of the limitation of the degree of freedom of the characteristic change, which occurs when both the amplitude and the group delay amount are adjusted, does not occur.

In the embodiment shown in FIG. 1, the component FIR for adjusting the amplitude is followed by the component IIR for adjusting the group delay amount. In the implementation of the present invention, an audio amplitude and group delay adjusting device is configured such that a component IIR for adjusting a group delay amount is followed by a component FIR for adjusting an amplitude. Of course, it may be configured.

(Effects of the Invention) As is clear from the above description, the audio amplitude and group delay adjusting apparatus of the present invention includes a characteristic input unit for designating a desired frequency characteristic and a desired group delay characteristic. , A digital filter that performs FIR digital filter operation according to the frequency characteristic information specified by the characteristic input section and all-pass IIR digital filter operation according to the group delay information specified by the characteristic input section. The filter operation means, and the FIR digital filter and the all-pass IIR digital filter described above by independently providing filter coefficients in accordance with the frequency characteristic information and the group delay information designated by the characteristic input section. And an audio amplitude and group delay adjusting device for controlling audio amplitude and group delay according to the present invention. On the other hand, the FIR filter for variably adjusting the amplitude and the all-pass IIR for variably adjusting the group delay amount.
The digital filter and the digital filter are connected in cascade, and the program for the FIR filter configuration and / or the filter coefficient data is rewritten to adjust the amplitude, and the all-pass filter is used to adjust the group delay amount. Since the program and / or the filter coefficient data for the configuration of the type IIR digital filter is rewritten, the signal amplitude and the group delay amount can be variably controlled independently by a device having a simple configuration. In addition, all-pass type IIR
By setting the digital filter coefficient in the digital filter, the group delay characteristics of the multiple all-pass IIR digital filters are made to be almost flat, and the group delay characteristics in the state where there is no unevenness over the entire frequency band. When the characteristic variable selection switch in the characteristic input section is not selected, the digital filter coefficient of the corresponding unit filter FLTi is aio = 1, ai1 = 0, ai2 = 0, bi1. = 0, bi2 = 0 so that the unit filter has filter characteristics such that the group delay amounts at the input and output are equal, the group delay amount at the all-pass IIR digital filter is , The group delay amount in each frequency band does not have ripples and can be calculated as a smooth connection to the group delay amount in the adjacent frequency band. Does not produce the ripple that would occur when rewriting everything that was designed with equiripple approximation, and the connection between adjacent frequency bands is smooth, thus making the localization of the sound image natural. Various advantages such as being easy to obtain are obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an audio amplitude and group delay adjusting device of the present invention, FIG. 2 is a front view of a characteristic input section and a display section, and FIG. 3 is an example of a digital signal processor DSP. FIG. 4 is a block diagram showing the configuration, FIG. 4 and FIG. 12 are block diagrams showing the configuration of a filter to be obtained by the operation of the digital signal processor DSP, and FIG. 5 is an operation explanation of the audio group delay adjusting apparatus of the present invention. 6 and 11 are flowcharts for explaining the operation of the central processing unit (CPU), FIG. 7 is a diagram for explaining the characteristics of the all-pass IIR digital filter, and FIG. FIG. 9 is a Z plan view for explaining an all-pass IIR digital filter, poles and zeros (mirrors), and FIG. 9 is an example of a memory map in a coefficient setting unit and a coefficient memory.
FIG. 10 is a block diagram showing a specific configuration of the multiplexer and the transmitter. 1 ... Digital signal input terminal, 2 ... Output terminal, 3 ... Input terminal, 4 ... Unit delay operator, 5 ... Multiplication circuit, 6 ... Addition circuit, 7 ... Output terminal, RD ... Receiving section, PLL ... Phase locked・ Loop, DSP1, DSPl2, DSPr1, DSPr2… Digital
Signal processor, CID ... Characteristic input section, DPA ... Display section, CPU ... Central processing unit, ROM ... Read only memory, RAM ... Random access memory, STD ... Serial code transfer section, SCG ... Clock signal generation circuit, MPX ... Multiplexer, TD ... Transmitter, SDI ... Serial data input circuit, IB ... Input buffer, NC-RAM ... Coefficient RAM, TB ... Transfer buffer, PCD ... Parameter controller, P-RAM ... Program RAM, SDO ... Serial data output circuit, SCI ... Serial code interface, D-RAM ... Data RAM,
FN-ROM ... Constant memory ROM, MUL ... Multiplier, ACC ... Accumulator, REG ... Register with shifter, OB ... Output buffer, BCLK ... Data clock signal, LRCK ... Channel identification signal, FLT1 to FLTn ... n of the same configuration Bike quad filter section,

Continuation of front page (56) Reference JP-A-63-220613 (JP, A) JP-A-63-224513 (JP, A) JP-A-60-198911 (JP, A) JP-A-60-241314 (JP , A) JP 60-244111 (JP, A) JP 62-264712 (JP, A) JP 59-112715 (JP, A) JP 1-19292 (JP, B2) JP 2-47891 (JP, B2) Japanese Patent Publication 3-35848 (JP, B2)

Claims (1)

[Claims] 1. A characteristic input section for designating a desired frequency characteristic and a desired group delay characteristic, an FIR digital filter operation according to frequency characteristic information designated by the characteristic input section, and the characteristic input. According to the group characteristic information and the frequency characteristic information designated by the characteristic input section, a digital filter computing means for performing an all-pass IIR digital filter computing according to the group delay information designated by the section, The filter coefficient is independently given to the above-mentioned FIR digital filter and the group delay amount in each divided pass band in all bands divided into a plurality of bands are controlled to be equal to each other, and the group delay amount in all bands is Fixed all-pass type
Audio amplitude and group delay adjusting device comprising control means for operating IIR digital filters in cascade