JPH0748663B2 - Digital level adjustment circuit - Google Patents

Description

The present invention relates to a digital level adjustment circuit that performs level adjustment such as volume adjustment by digital processing, and particularly uses a delta-sigma modulator. The present invention relates to a configuration using an oversampling type digital-analog converter.

(Prior Art) As is well known, in the field of digital audio equipment, level adjustment such as volume adjustment is considered to be performed by digital processing before digital / analog conversion. If the level adjustment is performed digitally in this way, not only can problems such as signal distortion and aging deterioration caused by using a variable resistor be solved as in the past, but also miniaturization can be promoted and the economy can be improved. It can also be advantageous.

FIG. 6 shows such a conventional digital level adjusting circuit. That is, this is a constant k ′ (1 ≧ 1) applied to the digital data supplied to the input terminal 11 by the multiplication circuit 12.
It is obtained by multiplying by k'≥0) and taken out from the output terminal 13, and the level is adjusted by controlling this constant k'by a control signal supplied to the control terminal 14.

However, such a conventional digital level adjusting circuit has the following problems. First, the digital multiplication circuit 12 has a remarkably complicated configuration and tends to have a large circuit scale as compared with a digital addition circuit or the like. Also, by multiplying by the constant k ', the bit length of the digital data handled increases. For example, k '= 1 /
Considering the case of 4 (attenuation rate 12 dB), as shown in FIG. 7, 16-bit digital data increases by 2 bits to 18 bits. Furthermore, when the attenuation rate is multiplied by a fraction such as 1 dB (= 0.891), the number of bits will increase.

On the other hand, in a digital audio device, digital data is finally converted from digital to analog, but increasing the number of bits of this digital to analog converter by 1 bit causes a considerable economic disadvantage, and further Increasing more than a few bits becomes technically difficult. Further, however, if the increased number of bits is rounded down or rounded down, there is an inconvenience that the low-level signal is distorted or disappears.

(Problems to be Solved by the Invention) As described above, the conventional digital level adjusting circuit has a problem that the circuit configuration is complicated and large, and that the performance is deteriorated and the economical disadvantage is caused by the increase in the bit length. is doing.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to perform high-performance level adjustment with a simple configuration without increasing the bit length, which is economically advantageous and is extremely favorable digital level adjustment. The purpose is to provide a circuit.

[Structure of the Invention] (Means for Solving the Problem) A digital level adjusting circuit according to the present invention binary-quantizes an adding means for adding input digital data and feedback data and output data of the adding means. Quantization means, subtraction means for calculating the difference between the output data of the quantization means and output data of the addition means, and filter means for digitally processing the output data of the subtraction means to generate feedback data Intended for delta-sigma modulation circuits.

Then, a predetermined constant k (≧
The present invention is provided with multiplication means for multiplying 1) and supplying it to the subtraction means, and is configured to adjust the level of output data of the quantization means by controlling the value of the constant k.

(Operation) According to the above configuration, the output data of the quantizing means is multiplied by a predetermined constant k (≧ 1) and supplied to the subtracting means, thereby increasing the full-scale level of the delta-sigma modulation circuit. Then, the level of the input digital data can be lowered equivalently to adjust the level of the output data from the quantizing means. Also, considering that the output data of the quantizing means is only binary, the multiplying means for multiplying this output data by k can be configured by a simple logic circuit, and the circuit scale can be reduced. .

Furthermore, the number of bits increases by multiplying the output data of the quantizing means by k, but originally, in a delta-sigma modulation circuit of the second or higher order, the operation in the loop is made considerably larger than the number of bits of the input digital data. Therefore, unless the value of the constant k becomes extremely large, problems such as increase in circuit scale and truncation of bits do not occur.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 15 is an input terminal to which digital data is supplied. The digital data supplied to the input terminal 15 is supplied to the filter circuit 17 by the adder circuit 16.
It is added with the feedback data output from. The data y output from the addition circuit 16 is a binary quantization circuit.
Supplied to 18. As shown in FIG. 2, the binary quantizing circuit 18 corresponds to, for example, a 16-bit + side full-scale value when the input data y is positive, and a 16-bit − side full-scale value when the input data y is negative. Output data y '.

Then, the data y ′ output from the binary quantization circuit 18 is multiplied by a predetermined constant k (≧ 1) in the multiplication circuit 19 and then the subtraction circuit 20 outputs the data y ′ to the output data y of the addition circuit 16. The difference data e is calculated and supplied to the filter circuit 17. The constant k of the multiplication circuit 19 can be changed by the control signal supplied to the control terminal 21. Then, the filter circuit 17 reduces the power of the quantization noise of the quantization circuit 18 in the low frequency region,
The feedback data is generated by digitally processing the data e. The binary quantization circuit 18
The data y'outputted from is converted into an analog signal by the 1-bit D / A (digital / analog) conversion circuit 22 and is taken out from the output terminal 23.

Here, the addition circuit 16, the filter circuit 17, the binary quantization circuit 18, and the subtraction circuit 20 excluding the multiplication circuit 19 constitute a delta-sigma modulation circuit. In this case, the number of bits of the adder circuit 16 may be the same as the number of bits of the input digital data in the first-order delta-sigma modulation, but 20 bits or more are required in the second-order or higher delta-sigma modulation. Therefore, if the 16-bit full scale value output from the binary quantization circuit 18 is expressed in 20 bits, the 16-bit plus side full scale value is 00000111111111111111 and the 16-bit minus side full scale value is 11111000000000000001.

By the way, if the value is used as it is, the multiplication circuit 19 needs a bit length of 20 bits or more.
Therefore, if the full-scale value is expanded by 1 LSB on both the positive and negative sides, the 16-bit + side full-scale value will be 00001000000000000000 and the 16-bit-side full-scale value will be 11111000000000000000.

The upper 5 bits of data are supplied to the multiplication circuit 19. Since the multiplication circuit 19 has only two inputs, it can be realized with a very simple configuration. That is, the third
FIG. 4 and FIG. 4 show the value of the constant k and the multiplication result y ′ when the attenuation rate is set to 0 to 15 dB. As you can see, the multiplication circuit 19 is a simple logic circuit or ROM.
(Read-only memory) or the like can be used. It should be noted that FIGS. 3 and 4 differ only in the number of operation bits from 12 bits and 8 bits, and there is no essential difference.
The number of operation bits is determined by how accurate the attenuation rate is. In practice, it is sufficient to take the number of bits as shown in FIG.

Then, the multiplication circuit 19 outputs the output of the binary quantization circuit 18 to k
By multiplying, the signal component of the output of the binary quantization circuit 18 is attenuated to 1 / k, and the output signal of the 1-bit D / A conversion circuit 22 to which this data is input is also attenuated to 1 / k.

Thereafter, the subtraction circuit 20 subtracts the output data y ′ of the multiplication circuit 19 from the output data y of the addition circuit 16. If the values shown in FIG. 4 are used, the number of bits of the subtraction circuit 20 will be 8 bits. Then, the output data e of the subtraction circuit 20 is supplied to the filter circuit 17 to generate feedback data. The characteristic H (Z) of the filter circuit 17 is H (Z) = 1- (1-Z ^-1 ) ^{n in} the case of nth-order delta sigma modulation.

FIG. 5 shows another embodiment of the present invention. That is, the output of the subtraction circuit 20 is added to the addition circuit via the delay circuit 24.
16 to the adder circuit 25, the filter circuit 26, 2
The value is supplied to a delta-sigma modulation circuit including a value quantization circuit 27, a multiplication circuit 28 and a subtraction circuit 29. Then, the subtraction circuit 30
Thus, from the output of the binary quantization circuit 27, the data obtained by delaying the output by the delay circuit 31 is subtracted, and the subtraction output is added to the output of the binary quantization circuit 18 by the addition circuit 32 to obtain 1
The bit D / A conversion circuit 22 is supplied.

The circuit shown in FIG. 5 is called a multi-stage noise shaping (MASH) type digital / analog conversion circuit except for the multiplication circuits 19 and 28. By connecting the delta-sigma modulation circuit in cascade, This is to reduce the quantization noise. And this type of digital /
Similarly to the above-described embodiment, the analog conversion circuit outputs each output of the plurality of binary quantization circuits 18 and 27,
High-performance digital level adjustment can be performed by multiplying by k in the multiplication circuits 19 and 28 and then supplying it to the subtraction circuits 20 and 29.

The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to perform high-performance level adjustment with a simple configuration without increasing the bit length, and it is economically advantageous to achieve an extremely good digital level. A regulation circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital level adjusting circuit according to the present invention, FIG. 2 is a characteristic diagram of a binary quantization circuit of the same embodiment, and FIGS. FIG. 5 is a diagram showing an example of an attenuation rate, a constant k, and a multiplication result in the example, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing a conventional digital level adjusting circuit. FIG. 7 is a diagram for explaining the problems of the conventional circuit. 11 ... Input terminal, 12 ... Multiplication circuit, 13 ... Output terminal, 14 ... Control terminal, 15 ... Input terminal, 16 ... Addition circuit, 17 ... Filter circuit, 18 ... Binary quantization circuit, 19 ... Multiplication circuit, 20 ... Subtraction circuit, 21 ... Control terminal, 22 ... 1-bit D / A conversion circuit, 23 ... Output terminal, 24 ... Delay circuit, 25 ... Addition circuit, 26 ... Filter circuit, 27 ... Binary quantization circuit, 28 ... Multiplication circuit , 29, 30 ... Subtraction circuit, 31 ... Delay circuit, 32 ... Addition circuit.

Claims (1)

[Claims] 1. An adding means for adding input digital data and feedback data, a quantizing means for binary quantizing the output data of the adding means, an output data of the quantizing means and an output data of the adding means. Subtraction means for calculating the difference between
In a delta-sigma modulation circuit including a filter means for digitally processing the output data of the subtraction means to generate the feedback data, the output data of the quantization means is multiplied by a predetermined constant k (≧ 1). A digital level adjusting circuit comprising a multiplying means for supplying to the subtracting means, and adjusting the level of the output data of the quantizing means by controlling the value of the constant k. .