JPH0748941B2 - Phase control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for phase-controlling electric power supplied from an AC power source to a load.

Conventional Technology FIG. 6 shows an electrical configuration of a conventional phase control circuit,
A waveform diagram for explaining the operation is shown in FIG. The power supplied from the AC power supply 51 to the load 52 is a bidirectional three-terminal thyristor connected in series to the AC power supply 51 and the load 52.
The phase is controlled by 53.

To control the phase of the bidirectional three-terminal thyristor 53, a sawtooth wave generation circuit 54, a comparison circuit 55 and a photocoupler 56 are provided. The sawtooth wave generation circuit 54 is shown in FIG. 7 (1).
In synchronization with the voltage waveform of the AC power supply 51, as shown in
A sawtooth wave as shown by line l61 in Fig. 2B is generated. The generated sawtooth wave sharply rises near the zero-cross points θ50 and θ60 of the AC power supply 51 and linearly falls to the next zero-cross points θ60 and θ70. This sawtooth wave is given to one input terminal of the comparison circuit 55 through the line l51. An input signal for controlling the phase of the bidirectional three-terminal thyristor 53 is applied to the other input terminal of the comparison circuit 55 via the line l52. The comparator circuit 55 compares the level of the sawtooth wave with the level of the input signal for phase control, and when the level of the sawtooth wave becomes equal to or lower than the level of the input signal, derives a low level output. Comparison circuit
When 55 derives a low level output, the light emitting diode 57 included in the photocoupler 56 emits light, and the photothyristor 58 of the photocoupler 56 is activated. When the photothyristor 58 is activated, a trigger current for firing the bidirectional three-terminal thyristor 53 flows through the resistor 59 and the photothyristor 58 to the gate of the bidirectional three-terminal thyristor 53.

For example, when an input signal for phase control as shown by the line l62 in FIG. 7 (2) is given, in the period from the phase angle θ52 where the level of the sawtooth wave becomes less than the level shown by the line l61 to the next zero cross point θ60. , Bidirectional three-terminal thyristor 53
Fires. The period during which the bidirectional three-terminal thyristor 53 is fired in this manner is shown by hatching in FIG. 7 (1).

In the conventional phase control circuit, the zero-cross point θ5
In the vicinity of 0, θ60, the output of the comparison circuit 55 is forcibly set to the high level, and the signal for firing the bidirectional three-terminal thyristor 53 is not generated. That is, the phase control is possible only within the period shown by W52 in FIG. 7 (2) in the period from θ51 to θ53 in FIG. 7 (1). However, θ in FIG. 7 (1)
Bidirectional thyristor with phase angle θ52 between 51 and θ53
When 53 is ignited, the ignition state continues until the next zero crossing point θ60. This is a bidirectional three-terminal thyristor 53
This is because once the ignition state has been established, the ignition state is self-maintained until the voltage across both ends becomes zero.

When the signal for firing the gate of the bidirectional three-terminal thyristor 53 passes through the zero-cross points θ50 and θ60 and is connected to the next half cycle of the power supply voltage waveform, in the next half cycle, the ignition is started from the beginning. As a result, the phase control cannot be performed. Therefore, in the vicinity of the zero cross points θ50 and θ60, generation of a signal for firing the bidirectional three-terminal thyristor 53 is prohibited by the signal from the line l53. This range W
51 is set to be relatively large in order to avoid variations in circuit constants and the influence of power supply noise. Therefore, although the half cycle of the AC power supply 51 is originally represented by a phase angle of 180 °,
It can only fire a range of up to 145 °. When the RMS voltage of AC power supply 51 is 100V, load 52
The effective value voltage supplied to is about 97 to 98V. That is, the electric power effectively supplied to the load 52 from the AC power supply 51 decreases.

An object of the present invention is to provide a phase control circuit that can effectively supply power to a load from an AC power supply.

Means for Solving the Problem The present invention forms a closed loop by an AC power supply 1, a load 2, and a bidirectional three-terminal thyristor 3, and a resistor is provided between one terminal and a gate of the bidirectional three-terminal thyristor 3. A series circuit consisting of 11 and a photothyristor 10 is connected to form a photocoupler 8 together with the photothyristor 10, and a light emitting diode 9 to which a one-level potential is applied to one terminal
, And is connected between both terminals of the AC power supply 1 and synchronized with the voltage waveform of the AC power supply 1 in the vicinity of the zero-cross points θ30, θ40, reaching one level before and after the zero-cross points θ30, θ40, and remaining time Then, the power supply synchronization circuit 12 that derives the synchronization signal l8 that is the other level, the means l7 that generates the phase control input signal, the clock circuit 14 that generates the clock signal at a cycle of less than half the cycle of the AC power supply 1, and the power supply synchronization. In response to the output from the circuit 12 and the phase control input signal generating means l7, the phase control input signal is set as a preset value of the count value, and the synchronization signal from the other level of the synchronization signal from the power supply synchronization circuit 12 is set to the synchronization signal. Of the clock signal from the clock circuit 14 from the time when the clock signal changes to the one level, and the counter 13 that counts by decrementing the count value every time the clock signal from the clock circuit 14 and the synchronization signal l8 from the power supply synchronization circuit 12 When the count value of the counter 13 becomes zero during the period when the level is the level, the output is reset from one level of the output to the other level of the output, and the output is output during the period of less than a half cycle of the AC power supply 1. In response to the outputs of the monostable circuit 15 that returns from the other level of the output to the one level of the output, the counter 13 and the monostable circuit 15,
When the count value of 13 is zero, the other terminal of the light emitting diode 9 is applied with the potential of the other level to cause the light emitting diode 9 to emit light, and the output of the monostable circuit 15 changes from the one level of the output to the output of the output. The phase control circuit is characterized in that the other terminal of the light emitting diode 9 includes a latch circuit 17 for applying a potential to turn off the light emitting diode 9 when the light emitting diode 9 changes to the other level.

According to the present invention, the photothyristor 10 forming the photocoupler 8 is connected to the gate of the bidirectional three-terminal thyristor 3 which is connected in series with the AC power supply 1 and the load 2 to form a closed loop. The light from the light emitting diode 9 is applied to the counter 13, and the counter 13 receives the phase control input signal, for example, a digital signal as the phase control input signal generating means.
The clock signal from the clock circuit 14 is counted from the time when the other level L of the power supply synchronizing signal from the power supply synchronizing signal generating circuit 12 changes from the other level L to the one level H, which is given from l7 and is set as a preset value. When the counter 13 counts down and the count value of the counter 13 is zero, the fourth
In the period of time t1 to t1a and t2 to t2a in the figure (3), the other level potential is applied to the other terminal of the light emitting diode 9 in which one level potential is applied to one terminal to cause the light emitting diode to emit light. The photo thyristor 10, and thus the bidirectional three-terminal thyristor 3, is conducted to perform phase control, and when the output of the monostable circuit 15 changes to the other level of the output, the light emitting diode 19 is turned off. Therefore, even if such a light emitting diode 9 is turned off, the photothyristor
10 and the bidirectional three-terminal thyristor 3 remain conductive. Thereby, the phase can be controlled with the maximum phase angle, and the power can be effectively supplied from the AC power supply 1 to the load 2.

Embodiment FIG. 1 is a block diagram showing an electrical structure showing a structure on which the present invention is based, and FIG. 2 is a waveform diagram for explaining the operation of the structure shown in FIG. The AC power supply 1, the load 2, and the bidirectional three-terminal thyristor 3, which is a semiconductor switching element, are connected in series to form a closed loop. The electric power supplied from the AC power supply 1 to the load 2 is phase-controlled by the bidirectional three-terminal thyristor 3.

In relation to the gate circuit of the bidirectional three-terminal thyristor 3,
Sawtooth wave generation circuit 4, first and second comparison circuits 5, 6,
A latch circuit 7 and a photo coupler 8 are provided. The sawtooth wave generation circuit 4 synchronizes with the voltage waveform of the AC power supply 1 shown in FIG.
Generates a sawtooth wave. This sawtooth wave is applied to one input terminal of the first comparison circuit 5 via the line 1. At the other input terminal of the first comparison circuit 5,
An input signal for controlling the phase of the bidirectional three-terminal thyristor 3 is given via the line l2. This input signal is
Levels in the range 0-10V represent 0-100% dimming levels. In the vicinity of the zero-cross points θ0, θ10, θ20 of the voltage waveform shown in Fig. 2 (1) of the AC power supply 1, W shown in Fig. 2 (2)
During the period of 1, a signal for forcing the output from the first comparison circuit 5 to the high level is derived via the line l3. A signal for detecting whether or not the level of the input signal is within the range of the level of the sawtooth wave applied to one input terminal of the first comparison circuit 5 is also derived from the sawtooth wave generation circuit 4. This signal is sent to the second line via line l4.
It is applied to one input terminal of the comparison circuit 6. This signal is
When the signal through the line l3 forces the output level of the first comparison circuit 5 to be high level, it has a level exceeding the maximum level of the input signal, and when the first comparison circuit 5 is activated, the saw This is the signal that has the maximum voltage level of the wave.
An input signal is applied to the other input terminal of the second comparison circuit 6 via the line l2. Therefore, when the level of the input signal exceeds the maximum output level of the sawtooth wave, the second comparison circuit 6 derives a latch signal which is a detection signal to be latched by the latch circuit 7 through the line l6.

When a signal is applied to the control input terminal via the line l6, the latch circuit 7 stores the data input signal at the time when the signal is applied and continuously derives it as a data output signal. When no signal is applied to the control input terminal of the latch circuit 7, the signal applied to the data input terminal is directly derived from the output terminal. When a signal for latching the latch circuit 7 is derived via the line l6, a low level signal is derived from the first comparison circuit 5. Therefore, the latch circuit 7 is latched at the low level, and the low-level output for causing the light emitting diode 9 of the photocoupler 8 to continuously emit light is derived. When the light emitting diode 9 emits light continuously, the photothyristor 10 causes resistance in each half cycle of the AC power supply 1.
A current is supplied to the gate of the bidirectional three-terminal thyristor 3 via 11 to ignite the bidirectional three-terminal thyristor 3. In this way, as shown by hatching in FIG. 2A, the bidirectional three-terminal thyristor 3 is fired every half cycle after being fired once at the phase angle θ1.

FIG. 3 is a block diagram showing the electrical construction of an embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. This embodiment is similar to the configuration shown in FIG.
Corresponding parts are given the same reference numerals. It should be noted that the input signal for phase control is the line l7 as the digital signal.
Is to give through.

In relation to the gate circuit of the bidirectional three-terminal thyristor 3,
A power supply synchronizing circuit 12, a counter 13, a clock circuit 14, a monostable circuit 15, a latch circuit 17 and a photocoupler 8 are provided. The power supply synchronizing circuit 12 derives the signal shown in FIG. 4 (2) via the line 18 in synchronization with the voltage waveform of the AC power supply 1 shown in FIG. 4 (1). The signal shown in FIG. 4 (2) is a signal indicating that the voltage waveform of the AC power supply 1 shown in FIG. 4 (1) is level-discriminated and is in the vicinity of the zero cross points θ30 and θ40. This signal is sent to counter 13 via line l8.
And to the monostable circuit 15.

The counter 13 latches when an input signal given through the line l7 is used as a preset value of the count value and a signal is given through the line l8, and the count value decreases in accordance with the signal given from the clock circuit 14. Count to. When the count value of the counter 13 becomes zero, a signal is derived from the counter 13 via the line l9 as shown in FIG. 4 (3). The synchronization signal shown in FIG. 4 (2) becomes high level in the vicinity of the zero cross points θ30 and θ40 in synchronization with the voltage waveform of the AC power supply 1 and before and after the zero cross points θ30 and θ40. Low level for the rest of the time. The clock signal from the clock circuit 14 is generated in a cycle less than a half cycle of the AC power supply 1 as described later, and 100 pulses, for example, are generated. The output of the counter 13 counts by decreasing the count value every time the clock signal changes from the low level to the high level, and the period when the count value is zero is shown in FIG. 4 (3). Are times t1 to t1a and t2 to t2a.

The monostable circuit 15 is reset from the high level to the low level when the count value of the counter 13 becomes zero while the synchronizing signal is at the high level, and the output of the monostable circuit 15 is a half cycle of the AC power supply 1. Time t2 in Fig. 4 (4) during the period less than
It is a monostable circuit that returns from a low level to a high level at b, and its time constant is set between times t2 and t2b, which is clear from FIG. 4 (4).

The monostable circuit 15 responds to the signals transmitted through the lines l8 and l9, and when the output from the counter 13 rises during the period when the output from the power supply synchronizing circuit 12 is at the high level, as shown in FIG. 4 (4). A low level output is applied to the control input terminal of the latch circuit 17. Since the latch circuit 17 latches the low level signal from the counter 13 via the line l9, the output of the latch circuit 17 becomes low level.
Thus, as shown in FIG. 4 (5), the output of the latch circuit 17 becomes low level after the time t2. The reason why the output of the latch circuit 17 instantaneously becomes high level around time t3 is that the counter 13 instantaneously derives a low level output. That is, the signal supplied from the counter 13 to the monostable circuit 15 through the line l9 is, for example, a standard product 74HC123 (trade name: Texas.
(Insertment Co., Ltd.) and the like, which is applied to the reset terminal of a monostable circuit and is connected to the power supply synchronization circuit 12 via line l8.
The input given from is given to the B input terminal. The output level of the latch circuit 17 is a logical inversion of the input level. That is, a low level input is a high level output, and a high level input is a low level output. When the low level output is derived from the latch circuit 17, the light emitting diode 9 is turned on and the bidirectional three-terminal thyristor 3 is ignited.

Once the bidirectional three-terminal thyristor 3 is ignited, the ignited state continues until the voltage between the pair of output terminals becomes zero. Therefore, in FIG. 4 (5), the bidirectional three-terminal thyristor 3 maintains the ignition state even if the light from the light emitting diode 9 is not given to the photodiode 10 momentarily around the time t3.

The clock circuit 14 generates a predetermined number, for example, 100 pulses within a half cycle of the power supply voltage of the AC power supply 1. As an input signal for phase control, for example, 100%
A value of 1 is given to count one pulse in order to perform the phase control of. Given a value of zero, the counter 13
Will count up to the maximum count value, so 1 is given as the minimum count value. When the value of the phase angle to be phase controlled is small, a large number is given as the input signal. Such conversion of the input signal to the complement can be performed by a simple arithmetic process in a dimmer that gives the input signal.

FIG. 5 shows the voltage applied to the cathodes of the light emitting diodes 57 and 9 in the conventional phase control circuit and the phase control circuits according to the above-described embodiments. As shown in FIG. 5 (1), in the conventional phase control circuit, there is a long period in which the light emitting diode 57 cannot be lit even if the phase angle to be phase controlled is maximized. Therefore, the electric power supplied from the AC power supply 51 to the load 52 decreases. Fig. 5 (2)
Shows outputs from the latch circuit 7 shown in FIG. 1 and the latch circuit 17 in the embodiment shown in FIG. When the phase angle is maximized, the outputs from the latch circuits 7 and 17 may be continuously at the low level and may instantaneously be at the high level.

According to the present invention, even if the phase control input signal from the phase control input signal generating means l7 has a value exceeding a half cycle of the AC power supply 1, the synchronization signal changes from the other level to the one level. The counting operation of the countdown of the counter 13 is started at the time of the change, and if the count value of the counter 13 becomes zero during the one-level period of this synchronizing signal, the light emitting diode 9 emits light, and the photothyristor 10 and the bidirectional Since the three-terminal thyristor 3 becomes conductive, the bidirectional three-terminal thyristor 3 can be kept conductive throughout the entire half cycle of the AC power supply 1, which allows the AC power supply 1 to operate.
Can effectively supply electric power to the load 2.

Further, according to the present invention, when the phase control is performed at the maximum phase angle, the phase control of the bidirectional three-terminal thyristor 3 is started when the amplitude of the power supply voltage of the AC power supply 1 is small. Power is not suddenly supplied to the power supply 2, and the occurrence of high frequency noise and the like can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electrical structure showing a structure on which the present invention is based, FIG. 2 is a waveform diagram for explaining the operation of the structure shown in FIG. 1, and FIG. Is a block diagram showing the electrical construction of one embodiment of the present invention, FIG. 4 is a waveform diagram for explaining the operation in the embodiment shown in FIG. 3, and FIG. 5 is a graph showing the effect of the embodiment shown in FIG. 6 is a block diagram showing the electrical configuration of the conventional phase control device, and FIG. 7 is a waveform diagram for explaining the operation of the conventional phase control device. 1 ... AC power supply, 2 ... Load, 3 ... Bidirectional three-terminal thyristor, 4 ... Sawtooth wave generation circuit, 5 ... First comparison circuit, 6 ... Second comparison circuit, 7,17 ... Latch circuit, 8 ...
… Photo coupler, 9… Light emitting diode, 10… Photo thyristor, 12… Power supply synchronization circuit, 13… Counter, 14…
Clock circuit, 15 …… Monostable circuit

Claims (1)

[Claims] 1. A closed loop is constituted by an AC power source 1, a load 2, and a bidirectional three-terminal thyristor 3, and a resistor 11 and a photothyristor 10 are provided between one terminal and a gate of the bidirectional three-terminal thyristor 3. Connected in series to form a photocoupler 8 together with a photothyristor 10, and a light-emitting diode 9 to which one level of potential is applied to one terminal.
, And is connected between both terminals of the AC power supply 1 and synchronized with the voltage waveform of the AC power supply 1 in the vicinity of the zero-cross points θ30, θ40, reaching one level before and after the zero-cross points θ30, θ40, and remaining time Then, the power supply synchronization circuit 12 that derives the synchronization signal l8 that is the other level, the means l7 that generates the phase control input signal, the clock circuit 14 that generates the clock signal at a cycle of less than half the cycle of the AC power supply 1, and the power supply synchronization. In response to the output from the circuit 12 and the phase control input signal generating means l7, the phase control input signal is set as a preset value of the count value, and the synchronization signal from the other level of the synchronization signal from the power supply synchronization circuit 12 is set to the synchronization signal. Of the clock signal from the clock circuit 14 from the time when the clock signal changes to the one level, and the counter 13 that counts by decrementing the count value every time the clock signal from the clock circuit 14 and the synchronization signal l8 from the power supply synchronization circuit 12 When the count value of the counter 13 becomes zero during the period when the level is the level, the output is reset from one level of the output to the other level of the output, and the output is output during the period of less than a half cycle of the AC power supply 1. In response to the outputs of the monostable circuit 15 that returns from the other level of the output to the one level of the output, the counter 13 and the monostable circuit 15,
When the count value of 13 is zero, the other terminal of the light emitting diode 9 is applied with the potential of the other level to cause the light emitting diode 9 to emit light, and the output of the monostable circuit 15 changes from the one level of the output to the output of the output. A phase control circuit comprising: a latch circuit 17 for applying a potential for turning off the light emitting diode 9 to the other terminal of the light emitting diode 9 when changing to the other level.