JPH0750156B2 - Memory read control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor tester such as an LSI, and particularly for generating a large number of test patterns used for testing a high performance microprocessor at a high speed. The present invention relates to a suitable memory read control device.

BACKGROUND OF THE INVENTION Generally, when testing a logic LSI such as a microprocessor, a test pattern is stored in advance in a memory of a test apparatus and is read out at high speed to generate a test pattern.

With the recent increase in speed and functionality of microprocessors,
The test is required to generate a large number of test patterns at a very high speed. The interleave operation is known as the most effective means for reading a test pattern at high speed using a memory having a large capacity at a low speed. As a test pattern generator adopting this method, for example, the device disclosed in Japanese Patent Laid-Open No. 54-128646 is known. Normally, when testing a logic LSI, etc.
Not only the sequential reading of test patterns, but the function of repeatedly reading the same test pattern, the function of jumping the reading order, and the like are required. In the above-mentioned conventional example, in order to provide these functions, the low-speed large-capacity memory is interleaved, the output is stored in the high-speed small-capacity memory, and the repetitive reading and the jump reading are performed here. However, with this configuration, it is not possible to jump over the capacity of the high-speed memory, and therefore the test patterns cannot be read completely in an arbitrary order.

[Object of the Invention]

It is an object of the present invention to provide a memory read control device capable of reading and generating a large number of test patterns in any order at high speed.

[Outline of Invention]

According to the present invention, the test pattern after the jump is stored in advance in the high-speed small-capacity memory provided in addition to the low-speed large-capacity memory that interleaves, and when the test patterns are read sequentially, the read-out is performed from the low-speed large-capacity memory. When a jump occurs, the high-speed small-capacity memory is switched to, and the test pattern is read from the high-speed small-capacity memory until the low-speed large-capacity memory can be read again.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a memory read control device. In the present embodiment, the memory read control device reads the low-speed large-capacity memories 11, 12, 13, 14 in order to read data from the four low-speed large-capacity memories 11, 12, 13, 14 and the high-speed small-capacity memory 50. Interleave controller 20 and selector 61 for interleave operation
And a high-speed memory access controller 40 that controls to read data from the high-speed small-capacity memory 50 when a jump occurs in reading, and further reads data from the low-speed large-capacity memories 11 to 14 again at the time of jump. A switching controller 30 and a selector 62 are provided for switching the data reading from the low-speed large-capacity memory side to the high-speed small-capacity memory 50 side until it becomes possible.

FIG. 2 shows an example of test patterns stored in the low-speed large-capacity memory and the high-speed small-capacity memory. The test program shown in FIG. 2 is composed of test patterns stored in the memories 11, 12, 13, 14, and 50, and sequence instructions for controlling the reading order. Here, NOP of the sequence instruction instructs to proceed to the subsequent address, and JUMP instructs to jump. In the example of FIG. 2, addresses 0 → 1 → 2 → 9 → 13 → 14
Test patterns corresponding to each are read out in the order of → 15 → ... When storing such a test pattern in the embodiment shown in FIG. 1, it is performed as shown in FIG.

That is, in the case of a low-speed memory, the interleave operation is performed.
The test patterns corresponding to 0, 1, 2, and 3 are stored.

Also, since the high speed memory is used only when jumping,
The jump destination test pattern corresponding to the JUMP instruction of the test program, in the illustrated example, the test patterns at addresses 9 and 13 are stored. Further, the reading from the high speed memory is continued after the jump is executed until the reading from the low speed memory becomes possible again. That is, in the embodiment shown in FIG. 1, since 4-way interleaving of low-speed memory is performed, even if the worst occurs after the jump is executed,
After the cycle, reading from the low speed memory is possible. Therefore, in the present embodiment, the high speed memory has a 3
Make sure the test patterns for the cycles are effective. As shown in FIG. 2, since there is a jump to address 9 and a jump to address 13 in the test program, the high speed memory corresponds to the jump to address 9, The test pattern is stored, and the test patterns at the addresses 13, 14, and 15 are stored corresponding to the jump to the address 13.

With such a configuration, when sequentially reading data from consecutive addresses, the data is read from the low-speed large-capacity memory that operates in an interleave operation, and when a jump occurs, data can be read from the low-speed large-capacity memory again. , Read data from high speed small capacity memory. This read operation will be described with reference to FIG.

Since addresses 0 → 1 → 2 generated according to the test program example shown in FIG. 2 are consecutive addresses, they are sequentially accessed to the low speed memories 11, 12, and 13, respectively. Since the next address 9 has jumped, the low-speed memory is in a waiting state (WAIT cycle), and the high-speed memory is switched to access. Since the next address 13 is also a jump, it is continuously accessed from the high speed memory 50.

The test pattern to be read next is that of address 14. The low-speed memory in the readable order here is the low-speed large-capacity memory 14, but the test pattern corresponding to the address 14 is not stored in the low-speed large-capacity memory 14 (see FIG. 2). Therefore, the test pattern of the address 14 is continuously read from the high speed small capacity memory 50.

The test pattern corresponding to the address 15 to be read next is stored in the low-speed large-capacity memory 14. Therefore, after this cycle, the test patterns can be sequentially read again from the low-speed memory side. So the address 15,1
6 are read from the low-speed large-capacity memory 14, 11, 12 ,. Since the low-speed memory is interleaved here, the output of the test pattern is delayed by several cycles from the start of access.

As described above, the feature of the present invention resides in the determination as to whether or not the reading from the low-speed memory is possible and the switching control thereof.

FIG. 4 is a detailed configuration diagram of the low-speed memory control side shown in FIG. 1, and FIG. 5 is an operation explanatory diagram thereof.

Low-speed, large-capacity memory that performs 4-way interleave operation 11
Since the access timings of Nos. 14 to 14 are usually shifted by one cycle, the memories 11 to 14 are provided with the registers 23 to 26 for holding the addresses, respectively. Then, the selector 61 sequentially selects and outputs the outputs from the low-speed large-capacity memories 11 to 14.

Control of the registers 23 to 26 and the selector 61 is 4w in this embodiment.
2-bit counter because it is ay interleaved operation
21. The load enable control signals 125 to 128 to the registers 23 to 26 are the outputs of the counter 21 decoded by the decoder 22. The selection signal 129 to the selector 61 is obtained by delaying the output of the counter 21 by the delay register 27. Then, by controlling the count enable signal 131 to the counter 21, the interleave operation of the low speed memory is put in a waiting state (WAIT cycle).

FIG. 6 is a detailed configuration diagram of the high-speed memory control side and the switching controller shown in FIG. 1, and FIG. 7 is an operation explanatory diagram thereof. As described above, in the present embodiment in which the 4-way interleave operation is performed, after the jump, in the worst case, the test pattern data is continuously read from the high speed memory for up to 3 cycles. Therefore, the high-speed memory is
51, 52, 53, and the outputs of the high-speed memories 51, 52, 53 are sequentially selected by the selector 43 each time the post-jump cycle is followed. These high speed memories 51, 52, 53 are addressed by register 41, which in each case jumps to JUMP signal 130-2 (in this example, this signal corresponds to signal 132 in FIG. 1). ), The contents are updated to the next compressed address 140. The compressed address corresponds to each jump instruction.

Incidentally, in the circuit shown in FIG.
Due to the construction of the three high speed memories 51, 52 and 53, a high speed memory output selection circuit 40 'which is not shown in FIG. 1 is added.

The counter 42 designates selection to the selector 43 and is cleared by the JUMP 130-2 each time a jump occurs. The delay register 44 is for aligning the output timing of the high speed memories 51 to 53 with the output timing of the low speed memory.

The down counter 32 outputs 0 in a normal state. Further, the −1 / PASS circuit 33 outputs the output 13 of the down counter 32.
When 4 is 0, 0 is output as it is, otherwise -1
Output the value. When an output occurs, if the value of the down counter 32 is 0, the adder 31 is unique to the jump.
The WAIT number is loaded into the down counter 32 as it is, and the down counter 32 counts down until the value becomes 0 in the subsequent cycles. When jumping, if down counter
If the output value 134 of 32 is not 0 (during continuous jump), a value obtained by adding WAIT number peculiar to the jump to the adder 31 is loaded to the down counter 32.
When the value of the down counter 32 is 0, the 0 detection signal 135
(The same signal as the count enable signal 131 in FIG. 1) is output. The 0 detection signal 135 is used to switch between the high speed memory and the low speed memory. Day register 34
Is for aligning the output timing and the switching timing of the memory.

Figure 8 shows the jump-specific WAIT used in Figures 6 and 7.
It is explanatory drawing which showed the calculation method of a number. As an example, in this embodiment, 4-way interleaving is shown. Therefore, N =
It is 4. Also, since the jump from address 2 to address 9 is K = 2 and L = 9, the WA unique to the jump
The number of IT Is. here Indicates the remainder obtained by dividing A by B.

In the present embodiment, the -1 / PASS circuit 33 and the adder 31 are used to
By correcting the number of IT, continuous jumps are possible. The corrected WAIT number at the time of continuous jump is given by "corrected WAIT number = remaining WAIT number-1 + unique WAIT number". As described with reference to FIGS. 6 and 7, the corrected WAIT number is calculated in real time, and as a result, continuous jumps can be executed without dummy cycles. It will be clear from the description of the figures.

As described above, in this embodiment, the number of interleaves is 4way,
It is not limited to this. The interleaving control method is not limited to this embodiment. In this embodiment, as a high speed memory, a method of accessing three memories in parallel in order to read a test pattern for three cycles has been shown, but the present invention is not limited to this, and the address bit of one high speed memory is used for the division. May be separated.

〔The invention's effect〕

According to the present invention, a low-speed large-capacity memory storing a pattern is operated by Nway interleaving, the pattern after the jump is stored in advance in the high-speed memory, and the necessary pattern is read from the high-speed memory when the jump occurs. Therefore, a high-speed and large-capacity pattern buffer can be obtained. When a jump occurs and the pattern is read from the high-speed memory, the pattern can be read from the high-speed memory continuously until the pattern can be read from the low-speed large-capacity memory. Does not cause a dummy cycle, and the buffer capacity does not decrease to 1 / N.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of a memory read control device to which an embodiment of the method of the present invention is applied, and FIG. 2 is an explanatory diagram of information stored in the memory shown in FIG. FIG. 3 is an operation explanatory diagram of the apparatus shown in FIG. 1, FIG. 4 is a detailed configuration diagram of the low-speed memory side shown in FIG. 1, FIG. 5 is a detailed operation explanatory diagram of the circuit shown in FIG. 4, and FIG. Is a detailed configuration diagram on the high-speed memory side of the device shown in FIG.
FIG. 7 is an explanatory diagram of detailed operation of the circuit shown in FIG. 6, and FIG. 8 is
It is a calculation explanatory view of the WAIT number. 11 to 14 …… Low speed memory, 20 …… Interleave controller,
30 ... Switching controller, 40 ... High-speed memory access controller, 50 ... High-speed memory, 61,62 ... Selector

Claims (1)

[Claims] 1. A memory read control device for sequentially reading a series of test patterns from a memory according to a test program in which a sequence instruction and a test pattern corresponding to each address are defined in a sequential address order and giving the test integrated circuit to a semiconductor integrated circuit under test. Sequential test patterns are cyclically stored in N (N ≧ 2 integer) low-speed large-capacity memories, and N−1 test patterns are stored in the address order from the instruction destination address for the address jump sequence instruction. There are a high-speed memory, an interleave control means for sequentially reading a corresponding test pattern by switching N low-speed large-capacity memories every cycle when the sequence command reads a test pattern of continuous addresses, and an address jump sequence command. When testing from low-speed large-capacity memory High-speed memory access control means for reading the corresponding test pattern from the high-speed memory instead of pattern reading, and switching control means for switching between the interleave control means and the high-speed memory access control means, which are unique to the address jump only when an address jump occurs. A memory read control device comprising: switching control means for operating the high-speed memory access control means for the number of WAITs and for putting the interleave operation of the low-speed large-capacity memory in a waiting state.