JPH0750451B2 - Information processing equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to error processing control when accessing a main memory.

[Conventional technology]

Conventionally, this type of information processing apparatus, when an error is detected during main memory access, recovers from a failure by recovering the error reply to the request source and then retrying the instruction if the request source can retry the instruction. I was worried.

[Problems to be solved by the invention]

The above-described conventional information processing device has a drawback that if the main memory fault is a fixed fault, it will fail even if an instruction retry is executed at the request source. Furthermore, the request source detects an error when the instruction retry is impossible. In that case, it is processed as a failure of the requester itself (JOB abort), the failed device cannot be properly separated, and even if the system is continuously operated thereafter, there is a drawback that the system is greatly affected. .

[Means for solving problems]

An information processing apparatus according to the present invention includes a main storage device including a plurality of memory units that can be accessed independently of each other, a request source processor, a diagnostic processor, and the main storage device, the request source processor, and the diagnostic processor. An information processing apparatus including a memory access control device provided in the request source processor, wherein the request source processor detects an error regarding a memory access from the request source processor, and error detection by the error detection means. Including error notification means for notifying the diagnostic processor, and an error address storage means for holding the memory address when the error is detected by the error detection means, wherein the diagnostic processor has an error regarding memory access from the diagnostic processor. Is detected, the cause of the error is in the main memory An error factor identifying means for identifying whether or not there is a clock, a clock stop control means for stopping the clock of the request source processor when an error is notified from the error notification means, and a clock stop for invalidating the clock stop by the clock stop control means When the error notification is received from the valid control means and the error notification means, the memory is accessed again based on the memory address from the error address storage means, and as a result, the error factor identification means determines the error factor as the main storage device. Error memory access control means for instructing the clock stop valid control means to invalidate the clock stop by the clock stop control means when it is identified that the memory access is performed again by the error memory access control means. Memory error depending on the result of And a failure processing control means for determining whether it is an intermittent failure or a fixed failure and for pointing out the memory unit that is the cause of the error by the address stored in the memory address storage means, wherein the memory access control device comprises: It includes memory configuration control means for separating the memory unit pointed out by the failure processing control means.

[Action]

When a failure occurs in the main memory device, the failure address can be interrupted / fixed by accessing the failure address again without stopping the request source clock. Also, depending on the result, do not abort the job if it is intermittent, if it is fixed,
The influence on the system can be minimized by performing the reconfiguration control of the main memory together with the abort to properly cut the faulty device and disconnect the faulty device thereafter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention.

The information processing apparatus according to this embodiment includes a main storage device 1, a memory access control device 11, a request source processor 13, and a diagnostic processor 14. The main memory 1 has eight memory units 2 to 9 that can be accessed independently of each other, and a request signal.
, 64 to access the memory units 2 to 9 and receive the reply signals 51, 53, ..., 65 from the memory units 2 to 9 and the main memory control unit 10. Memory access controller
11 is a main memory 1 and two request sources 1 request source processor
It is provided between the diagnostic processor 14 and the diagnostic processor 14, and comprises a request control circuit 12 and a memory configuration control circuit 28 that control access to the main memory 1 by control signals 66 and 67. The request source processor 13 is a request control circuit 15 for controlling a request to the memory by the request signal 68,
A reply control circuit 16 for controlling a reply from the memory by a reply signal 69, an error detection circuit 19 for detecting an error related to a memory access from the control signal 73, and the error by the control signal 75 is notified to the diagnostic processor 14 by the control signal 76. Error notification circuit 20 and an error address storage circuit 18 that holds the memory address from the control signal 72 when a memory access error is detected by the control signal 83. The diagnostic processor 14 includes a request control circuit 21 that controls a memory access request by a request signal 70.
And a reply control circuit 22 for controlling the memory access reply by the reply signal 71, and a control signal indicating whether or not the cause of the error is the memory when the memory access error is detected.
From the error factor identification circuit 23 identified from 78, a clock stop control circuit 24 that stops the clock of the request source processor 13 when a memory access error is detected, and when the error is detected,
The clock stop enable control circuit 25 that controls the enable / disable of the clock stop control circuit 24 by the control signal 82, and the error cause identification circuit 23 notifies the memory of the error cause when the error occurrence is notified when the memory access error is detected. When it is identified, the clock stop enable control circuit 25 disables the clock stop control circuit 24 and the error stored in the error address storage circuit 18 causes the error memory access control circuit 27 to perform memory access again, and the error memory access control circuit 27. It comprises a failure processing control circuit 26 which judges the intermittent / fixed state of the memory error according to the result and points out the memory unit of the error to the memory configuration control circuit 28 by the control signal 86 according to the address stored in the error address storage circuit 18.

Next, the operation of this embodiment will be described.

During normal operation or during read operation from the request source to the memory, the request control circuit 15 in the request source processor 13 uses the request signal 68 to request the memory address, request code, read request, etc. in the memory access control device 11. It is issued to the control circuit 12 together with the request. The request control circuit 12 checks the conflict with a request from another request source, and then, according to the memory configuration of the memory configuration control circuit 28 and the read request memory address sent from the request source processor 13, A request signal 66 is sent to the main memory control unit 10. Main memory controller 10
Sends a request signal 50 to a desired memory unit, for example, the memory unit 2 to perform a read operation. The read data is sent to the main memory control unit 10 together with the reply code by using the reply signal 51. Further, under the control of the request control circuit 12, the reply code and reply data are returned to the reply control circuit 16 of the request source processor 13 using the reply signal 69. The reply code at this time indicates where in the main storage device 1, the memory access control device 11 or the request source processor 13 the cause / presence of the detection of the memory access error accompanying the memory access and the factor at the time of the error are located. Contains information. If no memory access error is detected, normal operation continues.

Next, the operation when a failure is detected will be described. During the read operation from the request source to the memory, the reply signal 69 returned to the reply control circuit 16 of the request source processor 13 is the control signal 73.
Is sent to the error detection circuit 19 and the presence or absence of error detection is checked. When an error caused by the main storage device 1 is detected, the error notification circuit 20 uses the control signal 76 to control the error memory access control circuit 27 and the clock stop control circuit 24.
Will be notified to. The clock stop control circuit 24 notified of the error by the control signal 76 stops the clock of the request source processor 13. At this time, the error address is simultaneously stored in the error address storage circuit 18 from the request control circuit 15 by the control signal 72. The error memory access control circuit 27 notified of the error by the control signal 76 instructs the clock stop enable control circuit 25 by the control signal 81 to disable the operation of the clock stop control circuit 24 when an error is detected. The failure processing control circuit 26 instructs the error memory access control circuit 27 to perform memory access again according to the error address read from the error address storage circuit 18 through the data path 74 by the control signal 84. The request control circuit 21 of the diagnostic processor 14 issues a memory access to the main memory 1 according to the address of the error. As a result, the reply code, reply data, etc. are returned to the reply control circuit 22 and the error factor identification circuit 23
The presence or absence of a memory access error is determined by. As a result, even if there is a memory error, the clock of the request source processor 13 is not stopped by the control of the clock stop enable control circuit 25, and continuous operation is possible. If there is an error, the fault processing control circuit 26 regards this fault as a fixed fault and instructs the memory configuration control circuit 28 to separate the memory unit of the error according to the error address stored in the error address storage circuit 18 by the control signal 86. Give instructions. By performing the memory reconfiguration control in this way, it is possible to correctly cut the faulty device and minimize the influence of the system.

〔The invention's effect〕

As described above, according to the present invention, when a failure occurs in the main memory device, the failure address is not stopped and the failure address is accessed again to switch between the intermittent / fixed failures and the intermittent operation according to the result. If it is fixed without JOB Abort, if JOB ABORT is stopped, the faulty device is correctly separated by executing the reconfiguration control of the main storage device together, and the faulty device is separated thereafter, so that the influence on the system can be minimized. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention. 1 ... Main storage device, 2-9 ... Memory unit, 10 ... Main storage control unit, 11 ... Memory access control circuit, 12 ... Request control circuit, 13 ... Request source processor, 14 ... Diagnostic processor , 15 ... Request control circuit, 16 ... Reply control circuit, 18 ... Error address storage circuit, 19 ... Error detection circuit, 20 ... Error notification circuit, 21 ... Request control circuit, 22 ... Reply control circuit , 23 …… Error factor identification circuit, 24 …… Clock stop control circuit, 25 …… Clock stop enable control circuit, 26 …… Fault processing control circuit, 27…
… Error memory access control circuit, 28 …… Memory configuration control circuit, 50,52,54,56,58,60,62,64,68,70 …… Request signal, 51,53,55,57,59,61 , 63,65,69,71 …… Reply signal, 72,73,74,75,76,77,78,79,80,81,82,83,84,85,8
6,88 …… Control signal.

Claims (1)

[Claims] 1. A main memory comprising a plurality of memory units that can be accessed independently of each other, a request source processor, a diagnostic processor, and the main memory and the request source processor and the diagnostic processor. An information processing apparatus including a memory access control device, wherein the request source processor includes an error detection unit that detects an error relating to a memory access from the request source processor, and the error detection by the error detection unit is diagnosed by the diagnosis unit. The diagnostic processor includes an error notification unit for notifying the processor and an error address storage unit for holding the memory address when the error is detected by the error detection unit, and the diagnostic processor detects an error regarding memory access from the diagnostic processor. At this time, it is necessary to know whether the cause of the error is in the main memory. Error factor identification means, clock stop control means for stopping the clock of the request source processor when the error notification means gives an error, and clock stop enable control means for invalidating the clock stop by the clock stop control means. When the error notification is received from the error notification means, the memory is accessed again based on the memory address from the error address storage means, and as a result, the error cause is identified by the error cause identification means in the main storage device. Depending on the result of another memory access by the error memory access control means, an error memory access control means for instructing the clock stop valid control means to invalidate the clock stop by the clock stop control means when identified. Memory error is an intermittent failure The memory access control device, wherein the memory access control device determines whether or not there is a fixed fault, and points out the memory unit that caused the error based on the address stored in the memory address storage unit. An information processing apparatus, comprising: a memory configuration control means for separating the memory unit pointed out by.