JPH0750741B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having programmable chip functions.

[Technical background of the invention and its problems]

In recent years, the following LSIs have appeared with the demand for small-quantity, large-variety products.

(1) Standard cell method The circuit blocks having basic logic functions used in LSI are registered in advance in the computer, and these circuit blocks are arranged and wired by the automatic processing of the computer to obtain the desired final product. To get

(2) Gate array method The basic circuits that make up the logic gates are arranged in an array on the wafer in advance, and the wiring pattern is determined on this by automatic wiring as in the standard cell method, and the desired LSI
To get

Although these products have a shorter development period than fully hand-designed LSIs, they are wafers that use mask manufacturing processes and lithography technology between the end of individual design that determines the functions of the LSI and the completion of the LSI. A processing step is required. Therefore, there is a problem that it takes several weeks to several months from the end of individual design to the completion of the final LSI.

On the other hand, the following method has been proposed by the applicant (Japanese Patent Application No. 58-157718).

That is, as shown in FIG. 4, a plurality of circuit blocks 11a, 11b, ... The output signals are electrically guided to the switch matrix where ON / OFF states can be written, and all the output signals of each circuit block are switch elements such as MOSFET with E ² PROM or 1-bit memory for all the input signals. It is possible to connect via. Reference numeral 13 denotes a first wiring 12 provided in a direction perpendicular to the circuit block rows 11a, 11b ... And a second wiring 12 provided in a direction parallel to the circuit block row.

According to this method, since the method is field programmable, the user can obtain a desired LSI having a high function remarkably quickly by writing the logic function with his / her own hand. Moreover, the LSI can be designed by connecting the input signal and the output signal of the logic block having a certain logic function, and even a designer who is familiar with the logic design on the board can easily understand. Easy to design.

However, when the circuit block becomes large in this new method, the input / output signals to the wiring area increase,
The wiring area and the switch element are increased. With the increase of the wiring area, the output line from the circuit block is controlled connection by the ON / OFF state of the switch element on the wiring area, the wiring length until it becomes the input line of the circuit block again increases,
As a result, there is a drawback that the propagation delay time of the signal is increased.

[Object of the Invention]

An object of the present invention is to provide an LSI capable of shortening a propagation delay time of a signal from a circuit block having a logical function via the wiring area.

[Outline of Invention]

The present invention provides wiring areas on both sides of the circuit block area,
By allocating the second wiring group of the first wiring group and the second wiring group to both sides of the wiring area, and providing the first wiring group in the direction crossing the circuit block area for both wiring areas, respectively. The wiring length of the first wiring group is shortened.

〔The invention's effect〕

When the present invention is used, compared to the prior art
The wiring length of the wiring group is about half. Therefore, the area of the switch matrix is divided into left and right, and each area is about half that in the conventional case. Therefore, the wiring length of the signal line from the output of the first logic circuit block to the input of the second logic circuit block is reduced, and the signal propagation time is shortened.

Example of Invention

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the layout will be described with reference to FIG.

That is, circuit blocks 11a, 11b ... 11n are built in a Si wafer, and each circuit block is composed of one or more logic function elements such as a 4-input NAND gate. This logic function element has a CMOS structure and is a dedicated IC, that is, a handwritten standard cell in a standard cell system or a pre-wired gate array. The complex logic function element may be formed by combining standard cells by mutual wiring by the standard cell method.

The structure of the circuit block is as follows.

Block with two 4-input NAND gates ... 15
Block with four 2-input NAND gates ... 14
Block with one 8-input NAND gate ...... 1 block with four inverters …… 100 block with 8 bit register …… 19 block with two D-type flip-flops …… 19 block 4-input AND Block with two gates ... 17 Blocks with four 2-to-1 data selectors ... 13 Blocks with two 4-bit binary counters ... 11 Blocks with two 2-4 line decoders ... 7 Blocks with 3-8 line decoders ... 3 Blocks with two 4-1 selectors ... 5 Blocks with 8-1 selectors ... 4 Blocks with 8-bit serial input-parallel output shift registers ... ... 3 blocks 8-bit parallel input-serial output shift register block ... 3 8-bit serial input-serial output shift register block Block …… 2 blocks with 2 monostable multivibrator …… 4 blocks with 4 2-input OR gates …… 4 blocks with 4 2-input NOR gates …… 3 AND-OR inverters Block with 2 ...... 3 blocks 64-bit RAM ...... 3 locks with 4 2-input EXCLUSIVE-OR gates ...... 2 4-bit comparator blocks ...... 3 JK flip-flops 2 Block: 4 blocks 9-bit even / odd parity generator / checker block: 3 blocks 4-bit binary full adder block: 2 blocks with 4 2-input multiplexers: 5 SR Block with 4 latches …… 2 blocks ALU block …… 1 block 8-bit addressable latch block …… 1 block Look-ahead carrier Block ...... 1 i.e. the over data, provided with a circuit block composed of 274 pieces of MSI, 1
It is made possible to make LSIs of all functions from various types of chips. The average number of inputs of each circuit block is 8 and the number of outputs is 4. The input section and the output section of the logic function element serve as the input section and the output section of the circuit block, and the output section is provided with an output buffer (not shown). And the output part of the circuit block is
The second wiring 12 and the input section are connected to the first wiring 13 intersecting the second wiring 12 and the input section, respectively. And at the intersection, a switch element
14 are provided.

Then, by controlling ON / OFF of the switch, a chip having a desired function can be produced.

As shown in FIG. 1, the second wiring 12 is distributed to the left and right wiring regions, while the first wiring 13 is common. That is, of the output lines from the circuit block area 10, 01,0
3,05 extends to the right wiring area, and 02,04,06 extends to the left wiring area.

2 (a) shows the case where the output of 05 is transmitted as the input of I10, and FIG. 2 (b) shows the case of 05 '→ I10' corresponding to this in FIG. is there.
In (a), the wiring length is shortened by (L-1), so that the wiring capacitance is reduced and the signal propagation delay time can be shortened.

In the above example, the output from the circuit block is directly connected to the second wiring region, but the input force to the circuit block may be directly connected to the second wiring region.

Further, the signal line in the direction crossing the circuit block area is a wiring that runs in a straight line from one end to the other end of the chip, as shown in the figure.
It may be connected to one output (or input) terminal of the circuit block, or the same output (or input) terminal may be provided at both ends of the circuit block and extended from there to wiring regions on both sides.

FIG. 3 shows an example applied to a method called a divided block method. That is, the previously mentioned 274 circuit blocks of ~ are grouped into some islands and divided circuit blocks 31a, 31b, 31
It constitutes c ... ……. The division circuit blocks can be programmed by the method shown in FIG. Among the above-mentioned items, the same type of circuit block is distributed to each divided circuit block.

According to this method, the number of switch elements can be significantly reduced. That is, taking the divided circuit block 31a as an example, the total number of input / output lines from the divided circuit block 31a may be smaller than the total number of input / output lines included in the circuit blocks 11a to 11d. Also in this example, as in FIG. 1, wiring regions are provided on both sides of the circuit block region formed by the divided circuit blocks 31a, 31b, 31c ... And the same effect as in FIG. 1 is obtained.

[Brief description of drawings]

1 is a plan view showing an embodiment of the present invention, FIG. 2 is a plan view showing the effect of the present invention, FIG. 3 is a plan view showing another embodiment, and FIG. 4 is a plan view showing a comparative example. Is. In the figure, 11a, 11b ... 11n ... Circuit block, 12 ... Second wiring, 13 ... First wiring, 14 ... Switch element.

Claims (1)

[Claims] 1. A circuit block area in which circuit blocks having a signal input portion and a signal output portion are arranged in a row, a first wiring group in a direction perpendicular to the circuit block row, and a second wiring group in a direction parallel to the circuit block row. Wiring group and the first wiring group and the second wiring group
And a wiring region provided at a position where the wiring groups intersect each other and provided with a switch element that interconnects the signal output unit and the signal input unit, and the second wiring group is distributed to both sides of the circuit block. , The first wiring group is provided on both sides of the wiring region in a direction crossing the circuit block, and either one of the signal output unit and the signal input unit is directly connected to the second wiring group. A semiconductor integrated circuit characterized by being provided.