JPH0750752B2 - Printed circuit elements - Google Patents
Printed circuit elementsInfo
- Publication number
- JPH0750752B2 JPH0750752B2 JP13323685A JP13323685A JPH0750752B2 JP H0750752 B2 JPH0750752 B2 JP H0750752B2 JP 13323685 A JP13323685 A JP 13323685A JP 13323685 A JP13323685 A JP 13323685A JP H0750752 B2 JPH0750752 B2 JP H0750752B2
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- wiring board
- conductor layer
- printed wiring
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Combinations Of Printed Boards (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、トランジスタ、ICあるいはLSIなどの半導体
素子が形成された半導体基板（以後、半導体素子基板と
記す）を印刷配線板へ直接的にとり付けた構造の印刷回
路素子に関する。Description: TECHNICAL FIELD The present invention directly attaches a semiconductor substrate having semiconductor elements such as transistors, ICs or LSIs (hereinafter referred to as a semiconductor element substrate) to a printed wiring board. Structured printed circuit element.
従来の技術 近年、トランジスタ、ICあるいはLSIなどの半導体素子
基板を直接的に印刷配線板へとりつけた構造の印刷回路
素子が電子機器の回路部に使用されるに至っている。た
とえば、この印刷回路素子の構造としては、ガラス基材
エポキシ樹脂系の基板からなる印刷配線板に半導体素子
基板を直接的に取り付けた構造あるいはポリイミドフィ
ルムからなる印刷配線板に半導体素子基板を直接的に取
り付けフィルムキャリヤとした構造などがある。なお、
これらの印刷回路素子では、半導体素子基板は被覆樹脂
によって被覆される。2. Description of the Related Art In recent years, a printed circuit element having a structure in which a semiconductor element substrate such as a transistor, an IC or an LSI is directly attached to a printed wiring board has come to be used in a circuit portion of an electronic device. For example, as the structure of this printed circuit element, a semiconductor element substrate is directly attached to a printed wiring board made of a polyimide film or a printed wiring board made of a glass-based epoxy resin. There is a structure such as a mounting film carrier. In addition,
In these printed circuit elements, the semiconductor element substrate is covered with a coating resin.
発明が解決しようとする問題点 従来の印刷回路素子の構造では、半導体素子基板を取り
付ける導出リードとして印刷配線板の銅箔導体が用いら
れるが、この銅箔導体は印刷配線板の表面に突出するも
のであるため、この導出方向が被覆樹脂の拡がり方向と
直角であると拡がりがこの銅箔導体によって抑制され、
一方、平行であると拡がった被覆樹脂の裾部に空隙が生
じるおそれがあった。また、半導体素子基板が取り付け
られた銅箔導体の導出にあたっては、十分な幅と導出長
とを付与することによって動作時に半導体素子で生じる
熱の放散経路を確保しなければならない。なお、半導体
素子基板を印刷配線板へ直接的に接続し、回路部品によ
る占有面積を縮少して高密度の配置を意図したものの、
上記の銅箔導体を印刷配線板上へ外部端子として導出す
る必要があるにより付加的な占有面積の問題が派生す
る。Problems to be Solved by the Invention In the structure of the conventional printed circuit element, the copper foil conductor of the printed wiring board is used as the lead-out lead for mounting the semiconductor element substrate, and this copper foil conductor projects onto the surface of the printed wiring board. Therefore, if this lead-out direction is perpendicular to the spreading direction of the coating resin, spreading is suppressed by this copper foil conductor,
On the other hand, if they are parallel to each other, there is a possibility that voids may occur at the hem of the expanded coating resin. Further, when deriving the copper foil conductor to which the semiconductor element substrate is attached, it is necessary to secure a heat dissipation path for heat generated in the semiconductor element during operation by providing a sufficient width and lead length. Although the semiconductor element substrate is directly connected to the printed wiring board and the area occupied by the circuit components is reduced to achieve high-density arrangement,
Due to the need to derive the copper foil conductor as an external terminal on the printed wiring board, an additional occupied area problem arises.
さらに、電子機器への実装後に半導体素子基板を交換す
る必要があるときには、印刷回路素子全体を交換しなけ
ればならない。Furthermore, when it is necessary to replace the semiconductor element substrate after mounting on the electronic device, the entire printed circuit element must be replaced.
従来の印刷回路素子には、上記のような問題点があっ
た。The conventional printed circuit device has the above problems.
問題点を解決するための手段 本発明の印刷回路素子は、印刷配線板の表裏両面に所定
形状の導体層が形成されるとともに、表面側導体層が樹
脂による被覆領域内に形成され、さらに、同被覆領域内
の所定の位置に貫通孔を有する前記配線板の表面側導体
層の１つに半導体素子基板が接着され、残余の表面側導
体層と半導体素子基板上の電極との間が電気的に相互接
続され、前記貫通孔が導電ペーストで封塞され、かつ、
前記表面側導体層と外部との接続端子となる裏面側導体
層との間が前記貫通孔を通して電気的に接続されてなる
組立構体の前記被覆領域が樹脂で被覆された構造となっ
ている。Means for Solving the Problems In the printed circuit element of the present invention, a conductor layer having a predetermined shape is formed on both front and back surfaces of a printed wiring board, and a surface-side conductor layer is formed in a resin-coated region, and further, A semiconductor element substrate is adhered to one of the front surface side conductor layers of the wiring board having a through hole at a predetermined position in the same covering area, and an electrical connection is provided between the remaining front surface side conductor layer and the electrodes on the semiconductor element substrate. Electrically interconnected, the through hole is sealed with a conductive paste, and
The covering region of an assembly structure in which the front-side conductor layer and a back-side conductor layer serving as a connection terminal to the outside are electrically connected through the through hole is covered with resin.
作用 本発明の印刷回路素子では、導体層が被覆樹脂を通して
外部へ導出されることがなく、被覆樹脂の拡がりの抑制
あるいは裾部での空隙の発生などの不都合は生じない。
また、印刷配線板の裏面に形成した導体層が外部との接
続端子として用いられるため、印刷回路素子の形成に必
要とされる印刷配線板の面積が減少する。Action In the printed circuit element of the present invention, the conductor layer is not led out through the coating resin, and the disadvantages such as the suppression of the spreading of the coating resin and the formation of voids at the skirt do not occur.
Further, since the conductor layer formed on the back surface of the printed wiring board is used as a connection terminal to the outside, the area of the printed wiring board required for forming the printed circuit element is reduced.
また、この印刷回路素子は、これをチップ形部品として
取り扱うことが可能な形状であり、親印刷配線板に対し
て着脱可能な関係でとりつけるならば、これの交換の必
要性が生じても親印刷配線板はそのままにして印刷回路
素子のみを交換することができる。Further, this printed circuit element has a shape that allows it to be handled as a chip-shaped component, and if it is attached to the parent printed wiring board in a detachable relationship, even if it becomes necessary to replace it, the parent It is possible to replace only the printed circuit element while leaving the printed wiring board as it is.
実施例 以下に図面を参照して本発明の印刷回路素子について詳
しく説明する。EXAMPLES Hereinafter, the printed circuit device of the present invention will be described in detail with reference to the drawings.
図は、本発明の印刷回路素子とこれがとりつけられる親
印刷配線板との相対的な関係を両者の構造とともに示し
た断面図である。図中１は、厚さが0.5mmのガラス布基
材エポキシ樹脂積層板でできた印刷配線板であり、この
表面ならびに裏面に厚さが35μｍの銅箔導体層2,21およ
び3,31が形成され、さらにワイヤボンド部引出用孔４と
ダイボンド部引出用孔５が形成されている。半導体素子
基板６はその裏面電極７を銅箔導体層２に接着する関係
で固着され、さらに、半導体素子基板６の表面側電極８
と銅箔導体層21との間が金などの金属細線９によって接
続されている。The figure is a cross-sectional view showing the relative relationship between the printed circuit element of the present invention and the parent printed wiring board to which the printed circuit element is attached together with the structures of both. In the figure, 1 is a printed wiring board made of a glass cloth-based epoxy resin laminate having a thickness of 0.5 mm, and copper foil conductor layers 2, 21 and 3, 31 having a thickness of 35 μm are provided on the front surface and the back surface thereof. The hole 4 for drawing out the wire bond portion and the hole 5 for drawing out the die bond portion are further formed. The semiconductor element substrate 6 is fixed by adhering the back surface electrode 7 to the copper foil conductor layer 2, and further the front surface side electrode 8 of the semiconductor element substrate 6 is attached.
The copper foil conductor layer 21 and the copper foil conductor layer 21 are connected by a thin metal wire 9 such as gold.
なお、図示する例では孔４と５が銀粉−エポキシ樹脂系
の導電ペースト10で封塞され、また、印刷配線板１の表
裏に形成した銅箔導体層をこの導電ペーストで電気的に
相互接続している。この導電ペーストを半導体素子基板
６の接着以前にメタルマスクを用いて印刷しておき、15
0℃,30分間の熱処理で硬化させ導通状態とする。以上の
過程を経ることによって形成された組立構体は、次い
で、エポキシ樹脂11をステイジＡの状態でディスペンサ
によりポッティングしたのち、100℃,10分間の熱処理で
予備硬化させてステイジＢの状態とし、さらに、155℃,
30分間の熱処理でステイジＣの状態とする被覆過程を経
て封止され、印刷回路素子が完成する。In the illustrated example, the holes 4 and 5 are sealed with a silver powder-epoxy resin-based conductive paste 10, and the copper foil conductive layers formed on the front and back of the printed wiring board 1 are electrically interconnected with this conductive paste. is doing. This conductive paste is printed using a metal mask before the semiconductor element substrate 6 is bonded.
It is cured by heat treatment at 0 ° C for 30 minutes to make it conductive. The assembly structure formed through the above process is then potted with the epoxy resin 11 by the dispenser in the state of stage A, and then pre-cured by heat treatment at 100 ° C. for 10 minutes to be in the state of stage B. , 155 ℃,
The printed circuit element is completed by a covering process in which it is brought into a state of C by a heat treatment for 30 minutes and then sealed.
このようにして形成された本発明の印刷回路素子では、
図示するように、エポキシ樹脂による被覆範囲Ａは、印
刷配線板１の面積とほぼ等しくなっている。In the printed circuit element of the present invention thus formed,
As shown, the area A covered with the epoxy resin is substantially equal to the area of the printed wiring board 1.
一方、印刷回路素子をとりつける親印刷基板12は、下部
に係止部13が突出した印刷回路素子収納用の貫通孔14な
らびに他の回路部品の外部リード挿通孔15を有するとと
もに、裏面に導体層16を備えた構造となっている。かか
る親印刷配線板12への印刷回路素子のとりつけは、貫通
孔14の中へ印刷回路素子を嵌め込み、さらに図示するよ
うに他の回路部品17のリード線18を挿通孔15へ挿通した
のち、ディップソルダリングにより銅箔導体層31および
リード線18と導体層16とを接合することによってなされ
る。On the other hand, the parent printed circuit board 12 on which the printed circuit element is mounted has a through hole 14 for accommodating the printed circuit element in which the locking portion 13 projects and an external lead insertion hole 15 for other circuit parts, and a conductor layer on the back surface. It has a structure with 16. The mounting of the printed circuit element on the parent printed wiring board 12 is such that the printed circuit element is fitted into the through hole 14, and the lead wire 18 of the other circuit component 17 is inserted into the insertion hole 15 as shown in the drawing. This is done by joining the copper foil conductor layer 31 and the lead wire 18 to the conductor layer 16 by dip soldering.
以上、一例を示したが、印刷配線板１としては、基材と
して純フェノールあるいは純エポキシなどからなる硬質
板、ポリイミドなどのフレキシブル板を用いることもで
きる。また、実施例では、印刷配線板１の貫通孔４と５
の封塞および表裏面の導体層の相互接続が導電ペースト
でなされているが、導体層間の熱伝導を良好なものとす
る必要があるときには、貫通孔の内面に金属めっきを施
す金属めっきスルー構造を採用し、貫通孔を樹脂で封塞
するようにすればよい。Although one example has been described above, as the printed wiring board 1, a hard plate made of pure phenol or pure epoxy as the base material, or a flexible plate made of polyimide or the like can be used. Further, in the embodiment, the through holes 4 and 5 of the printed wiring board 1 are used.
Although the conductive paste is used to seal the conductors and interconnect the conductor layers on the front and back surfaces, a metal-plated through structure is used in which the inner surface of the through-hole is metal-plated when heat conduction between the conductor layers is required to be good. And the through hole may be sealed with resin.
発明の効果 本発明によれば、半導体素子基板を直接実装した印刷回
路素子が次のような特徴をもって得られる。まず、平面
的なリード導出部がないので被覆樹脂と印刷配線板との
密着性がよく、耐湿性が向上する。TTLのあるモデルで
はプレッシャクッカーテスト２気圧30時間の従来レベル
が２気圧100時間以上にまで向上した。スルーホール構
造を半導体素子基板接着領域およびワイヤボンド領域を
覆う樹脂被覆層下に設けることにより、例えば14本のボ
ンディング線を配置した半導体素子基板の実効接合面積
を印刷配線板面上において約40％減少することができ
た。導体径路も短縮され、裏面の導体層に導かれるの
で、半導体素子基板で生じた熱の放散はよくなり、デュ
アルインラインパッケージで250mW,表面リード導出形で
半導体素子基板直接実装で300mWの最大定格出力のもの
が、450mWにまで増強できた。また、製造時におけるは
んだディップ260℃５秒における温度上昇度は銅スルー
ホールめっき樹脂閉鎖スルーの場合75℃に達したが銀粉
−樹脂系導電ペーストスルーの場合35℃に留まった。つ
まり、銀粉−樹脂系導電ペーストは、半導体素子基板へ
のはんだ熱衝撃を弱めていることになる。本発明の印刷
回路素子は、さらに印刷配線板に載置して他の部品と同
時に実施するディップソルダリングにより電気的接続を
実現することができる。また取りはずす事も可能である
ので半導体チップキャリヤー又は半導体ハイブリッド回
路板として使用する事もできる。EFFECTS OF THE INVENTION According to the present invention, a printed circuit element having a semiconductor element substrate directly mounted thereon can be obtained with the following features. First, since there is no planar lead lead portion, the adhesion between the coating resin and the printed wiring board is good, and the moisture resistance is improved. In the model with TTL, the conventional level of pressure cooker test 2 atmosphere 30 hours improved to 2 atmosphere 100 hours or more. By providing the through-hole structure under the resin coating layer that covers the semiconductor element substrate bonding area and the wire bond area, for example, the effective bonding area of the semiconductor element substrate on which 14 bonding lines are arranged is about 40% on the printed wiring board surface. Could be reduced. Since the conductor path is also shortened and guided to the conductor layer on the back side, the heat generated in the semiconductor element substrate is well dissipated, and the maximum rated output of 250 mW in the dual in-line package and 300 mW in the direct mounting of the semiconductor element substrate with the surface lead derivation type. Can be increased up to 450mW. In addition, the temperature rise at a solder dip of 260 ° C. for 5 seconds during manufacturing reached 75 ° C. in the case of copper through-hole plating resin closed through, but remained at 35 ° C. in the case of silver powder-resin-based conductive paste through. That is, the silver powder-resin-based conductive paste weakens the thermal shock of the solder to the semiconductor element substrate. The printed circuit element of the present invention can be further mounted on a printed wiring board to realize electrical connection by dip soldering performed simultaneously with other components. Since it can be removed, it can be used as a semiconductor chip carrier or a semiconductor hybrid circuit board.
図は、本発明の印刷回路素子の構造および親印刷配線板
との相対的な関係を示す図である。 １……印刷配線板、2,21,3,31,16……導体層、4,5……
引出用の孔、６……半導体素子基板、７……裏面電極、
８……表面側電極、９……金属細線、10……導電ペース
ト、11……エポキシ樹脂、12……親印刷配線板、13……
係止部、14……貫通孔、15……外部リード挿通孔、17…
…回路部品、18……外部リード。The figure shows the structure of the printed circuit element of the present invention and the relative relationship with the parent printed wiring board. 1 …… Printed wiring board, 2,21,3,31,16 …… Conductor layer, 4,5 ……
Hole for extraction, 6 ... Semiconductor element substrate, 7 ... Back electrode,
8 ... Front side electrode, 9 ... Metal fine wire, 10 ... Conductive paste, 11 ... Epoxy resin, 12 ... Parent printed wiring board, 13 ...
Locking part, 14 ... Through hole, 15 ... External lead insertion hole, 17 ...
… Circuit parts, 18 …… External leads.
Claims (1)
が形成されるとともに、表面側の前記導体層が樹脂によ
る被覆領域内に形成され、さらに、同被覆領域内の所定
位置に貫通孔を有する前記印刷配線板の前記表面側導体
層の１つに半導体素子基板が接着され、残余の表面側導
体層と前記半導体素子基板上の電極との間が電気的に相
互接続され、前記貫通孔が導電ペーストで封塞され、か
つ、前記表面側導体層と外部との接続端子となる裏面側
導体層との間が前記貫通孔を通して電気的に接続されて
なる組立構体の前記被覆領域が樹脂で被覆されたことを
特徴とする印刷回路素子。1. A conductor layer having a predetermined shape is formed on both front and back surfaces of a printed wiring board, the conductor layer on the front surface side is formed in a resin-covered region, and further penetrates at a predetermined position in the covered region. A semiconductor element substrate is bonded to one of the front surface side conductor layers of the printed wiring board having holes, and the remaining front surface side conductor layer and electrodes on the semiconductor element substrate are electrically connected to each other, and The covering area of the assembly structure in which the through-hole is sealed with a conductive paste, and the front-side conductor layer and a back-side conductor layer serving as a connection terminal for the outside are electrically connected through the through-hole. A printed circuit device, wherein the printed circuit element is coated with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13323685A JPH0750752B2 (en) | 1985-06-19 | 1985-06-19 | Printed circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13323685A JPH0750752B2 (en) | 1985-06-19 | 1985-06-19 | Printed circuit elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61290758A JPS61290758A (en) | 1986-12-20 |
| JPH0750752B2 true JPH0750752B2 (en) | 1995-05-31 |
Family
ID=15099891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13323685A Expired - Fee Related JPH0750752B2 (en) | 1985-06-19 | 1985-06-19 | Printed circuit elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750752B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769766A (en) * | 1980-10-17 | 1982-04-28 | Matsushita Electric Ind Co Ltd | Ship carrier |
-
1985
- 1985-06-19 JP JP13323685A patent/JPH0750752B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61290758A (en) | 1986-12-20 |
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