JPH0750802B2 - Superconducting magnetic flux quantum logic circuit - Google Patents
Superconducting magnetic flux quantum logic circuitInfo
- Publication number
- JPH0750802B2 JPH0750802B2 JP3168055A JP16805591A JPH0750802B2 JP H0750802 B2 JPH0750802 B2 JP H0750802B2 JP 3168055 A JP3168055 A JP 3168055A JP 16805591 A JP16805591 A JP 16805591A JP H0750802 B2 JPH0750802 B2 JP H0750802B2
- Authority
- JP
- Japan
- Prior art keywords
- loop
- sub
- logic circuit
- flux quantum
- superconducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】超伝導磁束量子論理回路は超高速
アナログ・デジタル変換器、超高速デジタル・アナログ
変換器、超高速加算器等に用いられる。特にその超高速
加算器は脳磁界計測用多チャンネルSQUID磁束計の
信号処理に用いることができる。[Industrial application] Superconducting magnetic flux quantum logic circuits are used in ultra-high speed analog-digital converters, ultra-high speed digital-analog converters, ultra-high speed adders, and the like. In particular, the ultra-high speed adder can be used for signal processing of a multi-channel SQUID magnetometer for measuring brain magnetic fields.
【0002】[0002]
【従来技術】磁束駆動型超伝導磁束量子論理回路(特開
昭61−34986号公報参照)を図6に示す。同図で
L1 は第1の副ル−プ、L2 は第2の副ル−プ、Sはト
ランスの2次側、Pはトランスの1次側、Tはトランス
そしてJ1 、J2 はジョセフソン接合である。この超伝
導磁束量子論理回路ではトランス結合とジョセフソン結
合とがスイッチ部を構成している。図8と図9とを参照
して動作を説明する。先ずトランスの1次側Pにクロッ
ク交流電流を流すとそれによって交番磁束が発生する。
この磁束の振幅の変化に応じてジョセフソン接合が開閉
する。ジョセフソン接合の電流・電圧特性を示す図9か
ら明らかなように、クロック交流信号がからへ変化
すると電圧はからへヒステリシスル−プを描いて変
化する。この変化の内からは電圧状態でジョセフソ
ン接合は超伝導状態にはなくスイッチ部は開いている。
このスイッチ部が開いている状態では、図8の左の図に
示すように磁束量子Φ0 =h/2e(hはプランクの定
数、eは電子の電荷量)は主ル−プ内にはあるが、左右
の副ル−プの何れにも含まれてはいない。臨界点を超
えると、電圧は零となりジョセフソン接合は超伝導状態
となり、この状態はからを経て再び臨界点を超
えるまで継続し、その間スイッチ部は閉じ、磁束量子Φ
0 は図8の右上又は左下に示すように左右何れかの副ル
−プに入る。左右どちらの副ル−プに磁束量子Φ0 を入
れるかは外的条件(入力信号)によるのであり、この外
的条件に応じて左右何れかの副ル−プに入った状態を0
もしくは1に対応させることにより超伝導磁束量子論理
回路として機能させることができる。電圧・電流特性が
ヒステリシスを持っている場合について説明したが、電
圧・電流特性のがに接近し、がに接近して
電圧・電流特性がヒステリシスを持たない場合でも全く
同様に動作することは図9から理解されよう。2. Description of the Related Art FIG. 6 shows a magnetic flux driving type superconducting magnetic flux quantum logic circuit (see Japanese Patent Laid-Open No. 61-34986). In the figure, L 1 is the first sub loop, L 2 is the second sub loop, S is the secondary side of the transformer, P is the primary side of the transformer, T is the transformer and J 1 , J 2 Is the Josephson junction. In this superconducting magnetic flux quantum logic circuit, the transformer coupling and the Josephson coupling constitute the switch section. The operation will be described with reference to FIGS. 8 and 9. First, when a clock alternating current is passed through the primary side P of the transformer, an alternating magnetic flux is generated thereby.
The Josephson junction opens and closes according to the change in the amplitude of the magnetic flux. As is apparent from FIG. 9 showing the current-voltage characteristic of the Josephson junction, when the clock AC signal changes from to, the voltage changes in a hysteresis loop from to. From this change, the Josephson junction is not in the superconducting state in the voltage state and the switch is open.
In the state where the switch portion is open, the magnetic flux quantum Φ 0 = h / 2e (h is Planck's constant, e is the amount of electron charge) is in the main loop as shown in the left diagram of FIG. However, it is not included in any of the left and right sub-loops. When the voltage exceeds the critical point, the voltage becomes zero and the Josephson junction becomes a superconducting state. This state continues until the voltage exceeds the critical point again after passing through, during which the switch part closes and the flux quantum
0 enters either the left or right sub-loop as shown in the upper right or lower left of FIG. It depends on an external condition (input signal) which one of the left and right sub-loops contains the magnetic flux quantum Φ 0. According to the external condition, the state of entering the left or right sub-loop is 0.
Alternatively, by corresponding to 1, it can function as a superconducting magnetic flux quantum logic circuit. The case where the voltage / current characteristics have hysteresis has been described, but it is true that even if the voltage / current characteristics are close to, and if the voltage / current characteristics have no hysteresis, exactly the same operation is possible. As you can see from 9.
【0003】図6の磁束駆動型超伝導磁束量子論理回路
は満足すべきものではあるが、磁束駆動型であるためト
ランス2次側のインダクタンスと、トランスの1次側と
2次側との相互インダクタンスとはある必要とする大き
さとしなければならず、このためスイッチ部のコイルの
サイズを小さくすることができず、製作の困難さとあい
まって、どうしても回路が大きくなるという問題があっ
た。Although the magnetic flux drive type superconducting magnetic flux quantum logic circuit of FIG. 6 is satisfactory, since it is a magnetic flux drive type, the inductance on the secondary side of the transformer and the mutual inductance between the primary side and the secondary side of the transformer are high. However, the size of the coil of the switch cannot be reduced, which causes a problem that the circuit becomes large due to difficulty in manufacturing.
【0004】図7に従来の電流注入型のスイッチを含む
超伝導磁束量子論理回路を示す。動作にあたってはクロ
ック電流は片方の副ル−プL2 だけに流れる。この比較
的大きい副ル−プに流れるクロック電流は隣接する論理
回路の誤動作を生じさせる雑音磁界をつくる。FIG. 7 shows a superconducting flux quantum logic circuit including a conventional current injection type switch. In operation, clock current only flows in one of the sub-loops L 2 . The clock current flowing through this relatively large sub-loop creates a noise magnetic field that causes malfunction of the adjacent logic circuit.
【0005】[0005]
【発明が解決しようとする課題】以上に鑑み、本発明は
微細加工技術が許す限り小さくすることができ、周囲へ
雑音磁界を漏洩させることのない超伝導磁束量子論理回
路を提供することを目的とする。In view of the above, it is an object of the present invention to provide a superconducting magnetic flux quantum logic circuit which can be made as small as possible by fine processing technology and which does not leak a noise magnetic field to the surroundings. And
【0006】[0006]
【課題を解決するための手段】上記の本発明の目的は電
流注入型超伝導磁束量子論理回路のスイッチ部を改良す
ることにより達成される。すなわち、図1に示すように
スイッチ部は第1の副ル−プL1 の第2の副ル−プL2
への隣接側の部分l1 に直列に接続した一対のジョセフ
ソン接合J1 ,J2 と、第2の副ル−プL2 の第1の副
ル−プL1 への隣接側の部分l2 に直列に接続した一対
のジョセフソン接合J3 ,J4 と、各対の2つのジョセ
フソン接合の接続点C1 ,C2 に接続したクロック信号
供給手段と、各対のジョセフソン接合と副ル−プとの接
続点を相互に接続する手段l3 、l4 とを含む。ここに
使用するジョセフソン接合は準平面型ジョセフソン接合
であり、図5にその構成の概略を示す。同図において1
0は超伝導体(ニオブ)であり、12は絶縁層であり、
11は超伝導体(ニオブ)であり、そして13は常伝導
金属の弱結合部であり、一例としてその接合面積は2.
2×10-11 cm2 である。このデバイスを液体ヘリウ
ム温度にすると超伝導状態となり、無電圧で有限値の電
流(クロック電流)が超伝導体11、常伝導金属13、
超伝導体10を流れる。この超伝導状態でスイッチ部は
閉じ、主ル−プは2つの副ル−プに分けられ、一方の副
ル−プへ量子磁束を入れる。The above object of the present invention is achieved by improving the switch portion of a current injection type superconducting flux quantum logic circuit. That is, as shown in FIG. 1, the switch unit includes a second sub-loop L 2 of the first sub-loop L 1 .
A pair of Josephson junctions J 1 and J 2 connected in series to the part 1 1 on the side adjacent to the first sub-loop L 1 and the part on the side adjacent to the first sub-loop L 1 of the second sub-loop L 2 a pair of Josephson junctions J 3 and J 4 connected in series with l 2 , clock signal supply means connected to the connection points C 1 and C 2 of the two Josephson junctions of each pair, and Josephson junctions of each pair and Fukuru - and means l 3, l 4 which connects the connection point between the up mutually. The Josephson junction used here is a quasi-planar Josephson junction, and the configuration thereof is schematically shown in FIG. 1 in the figure
0 is a superconductor (niobium), 12 is an insulating layer,
Reference numeral 11 is a superconductor (niobium), and 13 is a weakly-bonded portion of a normal-conducting metal.
It is 2 × 10 -11 cm 2 . When this device is heated to liquid helium temperature, it becomes superconducting, and a finite-value current (clock current) with no voltage is applied to the superconductor 11, the normal metal 13,
It flows through the superconductor 10. In this superconducting state, the switch section is closed, the main loop is divided into two sub-loops, and quantum flux is injected into one of the sub-loops.
【0007】図1においてクロック電流はC1 −J2 −
l4−J4 −C2 を通り、そしてC1−J1 −l3−J3 −
C2 を通って流れ、いずれの副ル−プも流れることはな
く、隣接回路に対して雑音磁界を発生することはない。
又このスイッチ部は構造が簡単であり、集積回路として
作り易く、微細加工技術の限界まで小さくすることがで
き、それに従って集積度を上げることができる。In FIG. 1, the clock current is C 1 -J 2-
through l 4 -J 4 -C 2 and C 1 -J 1 -l 3 -J 3-
Flows through the C 2, any Fukuru - flop also not flow, does not occur the noise magnetic field to the adjacent circuit.
Further, this switch portion has a simple structure, is easy to manufacture as an integrated circuit, can be reduced to the limit of the fine processing technology, and accordingly the degree of integration can be increased.
【0008】[0008]
【実施例】本発明の第1の実施例を図2に示し、そのス
イッチ部を図10に示す。10、は水晶基板(図の紙面
に相当)に形成したニオブ膜であり、J1 、J2 、
J3 、J4 は図5のジョセフソン接合であって、図5に
示すようにニオブ膜10の上に絶縁層12を介してニオ
ブ膜11を形成し、常伝導金属の弱結合部13を形成す
る。クロック電流の流れは図10に示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG. 2 and its switch section is shown in FIG. 10 is a niobium film formed on a quartz substrate (corresponding to the paper surface of the figure), J 1 , J 2 ,
J 3 and J 4 are Josephson junctions shown in FIG. 5, and as shown in FIG. 5, a niobium film 11 is formed on the niobium film 10 with an insulating layer 12 interposed therebetween, and a weakly bonded portion 13 of a normal conductive metal is formed. Form. The flow of clock current is shown in FIG.
【0009】本発明の第2の実施例を図3に示し、第3
の実施例を図4に示す。いずれも第1の実施例に比して
製作し易い。A second embodiment of the present invention is shown in FIG.
An example of the above is shown in FIG. Both are easier to manufacture than the first embodiment.
【0010】[0010]
【発明の効果】本発明に従ってスイッチ部を構成するこ
とによりクロック電流は極めて限られた中心区域に流
れ、周囲への雑音源となるような広範囲に磁束を漏洩す
ることはない。又、そのスイッチ部の構成は非常に小さ
く、密度の高い集積回路の形成に有利である。By constructing the switch section according to the present invention, the clock current flows in a very limited central area, and magnetic flux does not leak to a wide area which becomes a noise source to the surroundings. Further, the switch portion has a very small structure, which is advantageous for forming an integrated circuit having a high density.
【図1】図1は本発明の超伝導磁束量子論理回路の回路
構成を示す。FIG. 1 shows a circuit configuration of a superconducting flux quantum logic circuit of the present invention.
【図2】図2は本発明の第1の実施例を示す。FIG. 2 shows a first embodiment of the present invention.
【図3】図3は本発明の第2の実施例を示す。FIG. 3 shows a second embodiment of the present invention.
【図4】図4は本発明の第3の実施例を示す。FIG. 4 shows a third embodiment of the present invention.
【図5】図5は準平面型ジョセフソン接合を略図的に示
す斜視図である。FIG. 5 is a perspective view schematically showing a quasi-planar Josephson junction.
【図6】図6は従来の超伝導磁束量子論理回路の回路構
成を示す。FIG. 6 shows a circuit configuration of a conventional superconducting flux quantum logic circuit.
【図7】図7は別の従来の超伝導磁束量子論理回路の回
路構成を示す。FIG. 7 shows a circuit configuration of another conventional superconducting flux quantum logic circuit.
【図8】図8は超伝導磁束量子論理回路の動作説明図で
ある。FIG. 8 is an operation explanatory diagram of a superconducting flux quantum logic circuit.
【図9】図9はジョセフソン接合の電圧・電流特性を示
すグラフである。FIG. 9 is a graph showing voltage-current characteristics of a Josephson junction.
【図10】図10は本発明の第1の実施例のスイッチ部
の拡大斜視図である。FIG. 10 is an enlarged perspective view of a switch unit according to the first embodiment of this invention.
J1 、J2 、J3 、J4 はジョセフソン接合 10、11はニオブ膜 12は絶縁層 13は常伝導金属 L1 は第1の副ル−プ L2 は第2の副ル−プ l1 は第1の副ル−プL1 の第2の副ル−プL2 への隣
接側の部分 l2 は第2の副ル−プL2 の第1の副ル−プL1 への隣
接側の部分 C1 ,C2 は接続点 l3 、l4 は副ル−プとジョセフソン接合の接続点を相
互に接続する手段J 1 , J 2 , J 3 , and J 4 are Josephson junctions 10 and 11 are niobium films 12 are insulating layers 13 are normal-conducting metals L 1 is a first subloop L 2 is a second subloop l 1 is the first Fukuru - second Fukuru the flop L 1 - part l 2 adjacent side to flop L 2 second Fukuru - first Fukuru the flop L 2 - flop L 1 The portions C 1 and C 2 on the side adjacent to the connection points l 3 and l 4 are means for mutually connecting the connection points of the sub-loop and the Josephson junction.
Claims (2)
ル−プを2つの隣接した第1と第2の副ル−プに分割す
るスイッチ部とを備えた超伝導磁束量子論理回路におい
て、前記のスイッチ部は第1の副ル−プの第2の副ル−
プへの隣接側の部分に直列に接続した一対のジョセフソ
ン接合と、第2の副ル−プの第1の副ル−プへの隣接側
の部分に直列に接続した一対のジョセフソン接合と、各
対の2つのジョセフソン接合の接続点に接続したクロッ
ク信号供給手段と、各対のジョセフソン接合と副ル−プ
との接続点を相互に接続する手段とを含むことを特徴と
した超伝導磁束量子論理回路。1. A superconducting flux quantum device comprising one superconducting main loop and a switch section for dividing the superconducting main loop into two adjacent first and second sub-loops. In the logic circuit, the switch unit includes a second sub-loop of the first sub-loop.
Pair of Josephson junctions connected in series to the portion adjacent to the first sub-loop and a pair of Josephson junctions connected in series to the portion adjacent to the first sub-loop of the second sub-loop And a clock signal supply means connected to the connection point of the two Josephson junctions of each pair, and a means for mutually connecting the connection points of the Josephson junction and the sub-loop of each pair. Superconducting magnetic flux quantum logic circuit.
超伝導体である請求項1に記載の超伝導磁束量子論理回
路。2. The superconducting flux quantum logic circuit according to claim 1, wherein the electrode portion of the Josephson junction is an oxide high temperature superconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3168055A JPH0750802B2 (en) | 1991-07-09 | 1991-07-09 | Superconducting magnetic flux quantum logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3168055A JPH0750802B2 (en) | 1991-07-09 | 1991-07-09 | Superconducting magnetic flux quantum logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0522118A JPH0522118A (en) | 1993-01-29 |
| JPH0750802B2 true JPH0750802B2 (en) | 1995-05-31 |
Family
ID=15860997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3168055A Expired - Fee Related JPH0750802B2 (en) | 1991-07-09 | 1991-07-09 | Superconducting magnetic flux quantum logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750802B2 (en) |
-
1991
- 1991-07-09 JP JP3168055A patent/JPH0750802B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0522118A (en) | 1993-01-29 |
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