JPH0752120B2 - Charge integration type photodetector and its signal readout circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge integration type photodetector and a signal read circuit thereof.

[0002]

2. Description of the Related Art A conventional charge integration type photodetector (hereinafter referred to simply as "photodetector") will be described with reference to a portion related to the present invention, that is, an output signal reading circuit.

In this type of photodetector, an output signal readout circuit basically has a charge storage capacitor connected in series to a photodetection element, and the charge generated in the photodetection element is integrated for a certain period of time by the capacitor. Then, the terminal voltage of the capacitor generated by this integration is read as an output signal. In the technical field to which the present invention pertains, a capacitor for storing charges is charged in advance to a predetermined voltage to store charges, and then a current-determining element such as a photodiode connected in series to the capacitor is connected. Discharging with a flowing current is called integrating a charge generated in the photodiode with a capacitor.

FIG. 4 shows a circuit diagram of an example of a conventional photodetector. Referring to FIG. 4, a conventional photodetector includes a photodetector element 2, a column selection transistor 3, and a DIG (Direct Injection Gate).
(ion gate) transistor 4 and an integrating circuit 1 including a capacitor 5. The charges generated in the photodetection element 2 are integrated in the capacitor 5 via the DIG transistor 4 only while the column selection transistor 3 is turned on (periods T1 and T4 in the timing chart shown in FIG. 5). When the column selection transistor 3 is opened and integration is completed, the row selection transistor 8 controlled by the control signal S2 becomes conductive, the terminal voltage of the capacitor 5 is read out to the read line 9, and the output signal is output via the output amplifier 10. It is output as S4. Further, in the latter half of the read-out period (periods T3 and T6 in FIG. 5), the reset transistor 11 controlled by the control signal S3 is turned on and the capacitor 5 is recharged to prepare for the next integration.
A constant voltage is applied to the gate electrode of the DIG transistor 4 so that the transistor operates in a saturation region, and even if the terminal voltage of the capacitor 5 changes during the read operation, the discharge is performed with a constant current. I have to.

As described above, the conventional photodetector is characterized in that the integration, reading, and reset (charge) operations are performed as one cycle, and the optical signal input to the photodetector element 4 is output as a voltage signal. .

As a structure for actually realizing the photodetector shown in FIG. 4, as a structure including the photodetection element 2 and the other circuit portion formed on the same substrate, There is a structure in which the container 2 and the other circuit portion are formed on separate substrates and then electrically integrated and connected.

[0007]

In the conventional photodetector described above, it is difficult to simultaneously satisfy the requirements for the S / N ratio of the output signal and the dynamic range.

That is, from the viewpoint of the S / N ratio, it is required to make the capacitance value of the capacitor 5 as small as possible so that the voltage swing of the output voltage becomes large. On the other hand, in order to cope with a transiently large amount of incident light, it is necessary to design the capacitor capacitance to be large. Generally, the capacitor is designed so that the S / N ratio becomes maximum with respect to the normal incident light amount, but in this case, the saturation phenomenon of the output signal with respect to a transiently large signal is unavoidable.

As described above, the conventional photodetector has a problem that the S / N ratio and the dynamic range are in a trade-off relationship in the optimum design of the capacitor capacitance.

[0010]

A signal readout circuit for a charge integration type photodetector according to the present invention comprises a charge integration capacitor and a current from the charge integration capacitor to a connecting portion to a photodetection element provided outside. A constant current element provided in the path, and a switching element for opening and closing the current path, including an integrating circuit configured to include the photodetector element in series to form a discharge path, A signal for a charge integration type photodetector configured to integrate the charge generated in the photodetection element for a predetermined time by the charge storage capacitor and read the terminal voltage of the charge integration capacitor after the integration as an output signal. In the readout circuit, a second capacitor for charge integration, a constant current source provided in the discharge path of the second capacitor, and a discharge path of the second capacitor are provided. A second integrating circuit including a second switching element that opens and closes in accordance with the terminal voltage of the charge integrating capacitor is provided, and the charge integrating capacitor and the second capacitor are charged in advance to a predetermined voltage, and The terminal voltage of the charge integration capacitor and the terminal voltage of the second capacitor after integration for a predetermined time are read as output signals.

[0011]

The charge integration type photodetector and the signal readout circuit thereof according to the present invention have a second integrating circuit which works when the incident light amount transiently increases, in addition to the first integrating circuit which works with the normal incident light amount. . This second integration circuit has a switching transistor that controls the start of the integration operation. The gate input of this switching transistor is given by the node voltage between the capacitor in the first integrating circuit and the DIG transistor,
Design so that the switching transistor is turned on at an arbitrary node voltage or less. When the amount of incident light transiently increases due to the action of this switching transistor,
The second integrator circuit automatically starts its operation, and the signal voltage integrated by the first / second integrator circuit is output via the independent read line and output amplifier.

Here, the capacitor of the first integrating circuit is designed so that a high S / N ratio can be obtained with respect to a normal incident light amount, and the capacitor of the second integrating circuit is optimally designed for a transiently large incident light amount. By doing so, it becomes possible to make the S / N ratio and the dynamic range compatible.

As a result, it is possible to detect a large signal light, which has been impossible in the past, while securing the same S / N ratio as that of the conventional photodetector.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. Referring to FIG. 1, this embodiment has two integrating circuits 1A and 1B. The first integrator circuit 1A corresponds to the integrator circuit 1 (see FIG. 4) of the conventional signal readout circuit, and the charges generated in the photodetector element 2 pass through the DIG transistor 4A only while the column selection transistor 3 is in the conductive state. Are integrated by the capacitor 5A.

On the other hand, the second integrating circuit 1B includes a constant current source 4B.
And a capacitor 5B (5.0 pF) and a switching transistor 6 in series. The gate input of the switching transistor 6 is given by the node voltage of the DIG transistor 4A and the capacitor 5A of the first integrating circuit. Here, as the switching transistor 6, a p-channel depletion type MOS transistor having a threshold voltage of 2.0 V is used. That is, when the node voltage falls below 2.0V, the switching transistor 6
Are conducted, and the integration operation of the second integration circuit 1B starts. The terminal voltage of each capacitor 5A / 5B is output as an output signal S4A / S4B from the independent read lines 9A and 9B via the output amplifiers 10A and 10B.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG. In FIG. 2, control signals S1 to S3 correspond to the transistors 3 and 8 in FIG.
The gate input signals of A, 8B, 11A and 11B are shown. First, when the control signal S1 is high, that is, the periods T1 and T4 (200 μm each) during which the column selection transistor 3 is conducting.
The integration is performed in s). When the integration is completed, the control signal S2 becomes high, and the two row selection transistors 8A / 8B become conductive. The first half of the period in which the row selection transistors 8A / 8B are conducting, that is, the periods T2 and T5 in FIG.
(Each 100 μs), each capacitor 5A / 5B
The voltage integrated by is output as the output signal S4A / S4B from the read line 9A / 9B. Finally, in the latter half of the periods T3 and T6 (100 μs each), the control signal S3 becomes high at the same time, and both capacitors 5A / 5B are recharged.

In the first integration cycle (period T1), a diode current of 10 nA is generated in the photodetector 2 with a normal incident light amount, and in the second integration cycle (period T4), the incident light amount is increased and a current of 40 nA is generated. The output signal when it is generated will be described. The output signals S4A / S4B represent the output signal of the first integrating circuit 1A and the output signal of the second integrating circuit 1B, respectively. Here, the reset voltage (capacitor 5
The charging voltage of A and 5B) was 4 V, and the output amplifier used had a gain of 1.0. The constant current source 4B is 100
Used at nA.

During the period T1, since the incident light quantity is at a normal level, the integration of the capacitor 5A does not saturate,
The voltage of the output signal S4A was 3V. At this time, the switching transistor 6 does not become conductive, and the output signal S
The voltage at 4B remained at 4V.

On the other hand, in the period T4, 100 μs after the start of integration.
At time P1 in FIG. 2, the node voltage (the terminal voltage of the capacitor 5A) becomes 2V, the switching transistor 6 is turned on, and the second integrating circuit 1B starts the integrating operation. After the integration was completed, the output voltage of the output signal S4B was 2V. At this time, the output signal S4A was already saturated at 150 μs (the same time P2) after the start of integration, and the output voltage was 1V.

When the current value of the photodetector 2 was changed, the first integrator circuit 1A was saturated at 30 nA, but the second integrator circuit 1B was not saturated up to 80 nA. In this embodiment, the dynamic range can be further expanded by appropriately changing the circuit constant. Moreover, since the first integrating circuit 1A performs integration with a normal light amount (current value of the photodetector element 2 is 30 nA or less), S / S that is almost the same as the conventional one
The N ratio can be maintained.

From the above, it was confirmed that when the amount of incident light is large, the integration operation is normally performed by the second integrating circuit 1B by the action of the switching transistor 6. In this embodiment, the dynamic range could be expanded to 2.7 times while maintaining the same S / N ratio as the conventional one.

In the above-mentioned first embodiment, the second integrating circuit 1
The charge accumulated in the B capacitor 5B is discharged by the constant current source 4B dedicated to the integrating circuit 1B.
As in the second embodiment shown in (1), the photodetector 2 can be used as the current source for discharging the capacitor 5B.

Referring to FIG. 3, in the second embodiment of the present invention, the discharge path of the capacitor 5B of the second integrating circuit 1C is such that the switching transistor 6, the DIG transistor 4C, the column selection transistor 3 and the photodetector. It is a series circuit with the element 2. Similar to the first embodiment, the switching transistor 6 controls the timing of starting the integration in the second integrating circuit 1C by the terminal voltage of the capacitor 5A in the first integrating circuit 1A. The DIG transistor 4C is provided to prevent the discharge current from changing due to the change in the terminal voltage of the capacitor 5B accompanying the progress of integration in the second integrating circuit 1C, and the gate electrode has this A constant bias voltage is applied so that the transistor 4B operates in the saturation region. The configuration of the present embodiment is substantially a configuration in which the first integrator circuit 1A and the second integrator circuit 1C share the photodetection element 2 as a discharge current source of the respective capacitors 5A / 5B. A part of the electric charges generated in 2 will be integrated in the second integrating circuit 2C. Also in this embodiment, in addition to the first integrator circuit that performs the integration with the normal incident light amount, the second integrator circuit that performs the integration when the incident light amount increases is provided.
The dynamic range can be expanded while ensuring the ratio.

[0024]

As described above, the charge integration type photodetector and the signal reading circuit thereof according to the present invention are used for charge integration of a capacitance value such that a high S / N ratio can be obtained with respect to a normal incident light amount. A first integrator circuit having a capacitor, and a second integrator circuit having a charge integrating capacitor optimally designed for a transiently large incident light amount and a switching element provided in a discharge path of the capacitor. And
When the amount of incident light transiently increases and the first integrating circuit is saturated, the switching element detects this and the second integrating circuit automatically starts the integrating operation.

As a result, according to the present invention, a high dynamic range can be realized while maintaining the S / N ratio of the charge storage type photodetector to the same level as the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a conventional charge integration type photodetector.

5 is a timing chart diagram for explaining the operation of the circuit shown in FIG. 4. FIG.

[Explanation of symbols]

 1, 1A, 1B, 1C Integrator circuit 2 Photodetector 3 Column selection transistor 4, 4A, 4C DIG transistor 4B Constant current source 5, 5A, 5B Charge integration capacitor 6 Switching transistor 8, 8A, 8B Row selection transistor 9, 9A, 9B Read line 10, 10A, 10B Output amplifier 11, 11A, 11B Reset transistor

Claims (4)

[Claims] 1. A constant current element provided in a current path from a charge integration capacitor to a connection portion between the charge integration capacitor and a photodetection element provided outside, and a switching for opening / closing the current path. The element includes an integrating circuit configured to include the photodetection element in series to form a discharge path, and integrates the charge generated in the photodetection element for a predetermined time by the charge storage capacitor. In a signal readout circuit for a charge integration type photodetector configured to read out the terminal voltage of the charge integration capacitor after the integration as an output signal, a second capacitor for charge integration and the second capacitor Constant current source provided in the discharge path of the second switch and a second switch for opening and closing the discharge path of the second capacitor according to the terminal voltage of the charge integration capacitor. A second integration circuit including a charge element, the charge integration capacitor and the second capacitor are charged to a predetermined voltage in advance, and the terminal voltage of the charge integration capacitor after integration for the predetermined time and A signal readout circuit for a charge integration type photodetector, characterized in that the terminal voltage of the second capacitor is read out as an output signal. 2. The signal readout circuit for a charge integration type photodetector according to claim 1, wherein a constant current element is connected instead of the constant current source of the second integration circuit, and the second integration circuit is connected. By connecting the photodetection element and the switching element of the integration circuit in series to the discharge path of, the constant current source is configured by the constant current element and the photodetection element, and the photodetection element A signal readout circuit for a charge integration type photodetector, characterized in that a part of charges generated in the element is integrated by the second capacitor. 3. A charge integration type photodetector, characterized in that the signal readout circuit according to claim 1 or the signal readout circuit according to claim 2 and a photodetection element are formed and integrated on the same semiconductor substrate. 4. The signal readout circuit according to claim 1, or the signal readout circuit according to claim 2 and a photodetector are formed on different semiconductor substrates, and each semiconductor substrate is formed on the semiconductor substrate of the signal readout circuit. A charge integration type photodetector, characterized in that a connection portion with the photodetection element and the photodetection element are integrated so as to be electrically connected.