JPH0752337B2 - Memory controller - Google Patents

Description

The present invention relates to a memory control device for moving an image displayed on a display device to another place in the same screen.

A memory control device according to the present invention regards a memory space as a two-dimensional plane and transfers a rectangular region of a part of the two-dimensional plane to another region within the same two-dimensional plane. The image on the display device can be moved to a predetermined location by the transfer of the memory area by.

[Conventional technology]

FIG. 1 shows image data of an area (S ₁ ) initially stored in a memory space (S) regarded as a two-dimensional plane in an image memory, for example, a VRAM, in a desired area (S ₁ ). it is a diagram for explaining a case of transferring S ₂₎ to. Typically,
Such transfers can be performed using direct memory access (DM
A) It is done by transfer. That is, the address 33 of the data 1 in the X direction is read and written to the address 38 of the data 1 ', and then the address 34 of the data 2 is read to read the data 2'.
The procedure for writing to the address 39 of 1 is alternately performed byte by byte and transferred.

As is apparent from FIG. 1, the addresses corresponding to the addresses 33 to 38 are continuous, but the last 6 of the row and the first 7 of the next row are address-discontinuous. Therefore,
In the conventional transfer method, first from 1 to 6 from address 33
After the sequential access and transfer are completed by 38, new parameters are set for the transfer of the next 7 to 12 blocks and the data 7 to 12 are transferred. This transfer is also performed for the next row 13 and finally the number of rows 1 is transferred.

[Problems to be solved by the invention]

In the memory transfer method as described above, as described above, each line is transferred and the central processing unit (CPU) is transferred before the transfer of the next line.
After setting the parameters of each line, the transfer of that line is started. Therefore, the longer the number of rows l is, the more frequently the CPU intervenes, so that the processing efficiency is lowered and the speeding up of transfer is hindered.

[Means for solving problems]

The present invention is a memory control device for transferring a plurality of data blocks each having a plurality of data and having non-consecutive addresses to different memory areas in a memory space, wherein the first block of the plurality of data blocks is A base register for writing and reading whose address is initially set as a start address, a memory counter for writing and reading which sequentially generates memory addresses with the address of the base register as an initial value, and a memory counter for reading A first counter that outputs a first control signal each time the number of addresses to be counted is counted, and a value corresponding to the number of data included in one data block is counted; and a first counter is transferred in response to the first control signal. Counts the number of data blocks and indicates the end of transfer when the preset count value is reached A second counter that outputs a second control signal, an offset register in which a value corresponding to the difference between the addresses of each data block and the data block to be transferred next is set as an offset value, and one data block are included. The base register is added as the start address of the data block to be transferred next, by adding the offset value and the base register value in response to the first control signal each time the address generation of a plurality of data is completed. And an adder for writing and reading set to, and each time the generation of consecutive addresses in one data block is completed, the base register value is updated by the offset register and the adder to By sequentially generating the addresses of the data contained in the data block,
The data of the plurality of data blocks is continuously transferred by direct memory access.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a memory controller as an embodiment according to the present invention. In FIG. 2, 1 is a write base register, 2 is a read base register, 3 is an offset register, 4 is a row buffer, 5 is a column counter,
6 and 7 are adders, 8 is a row counter, 9 is a control circuit, 10 and 11 are memory counters, 12 is a multiplexer, 13 is an image memory, and 14 is a temporary register.

In the above configuration, the memory transfer method by DMA transfer for transferring the first memory area (S ₁ ) of the memory space (S) to the desired memory area (S ₂ ) as shown in FIG. ₁ is basically It is performed as follows. That is, the difference between the address between the data 6 and 7 (the address 38 of the data 6 and the address 48 of the data 7 (33 in FIG. 1 corresponds to 48)) and the data 6
The offset indicated by the sum of the difference in the number of data between 5 and 7 is
If the offsets of the data 12 and 13 are the same, and the same applies to the following lines, the CPU sets the start address 1 of address 33 before transfer, and then the number of transfer data in one section is 6. Then, the address offset between the data 6 and 7 (data 6 in this example)
Since the address is 38 and the data 7 is the address 48, the offset is set to 15), and finally the number of lines 1 is set. As a result, when the transfer of the continuous section data 1 to data 6 is completed by the memory control device described below,
The address 48 of the next data 7 is calculated without the intervention of the CPU, and the transfer of the data 12 from the data 7 in the next section is started. When the transfer of this row is completed, the address of the next data 13 can be calculated, and the subsequent transfer can be performed in the same manner.

The basic operation described above will be described in detail with reference to screens. As described above, in DMA transfer, writing and reading are alternately performed. The data bus A is connected to the CPU and first the switch SW ₁
Is set to the B side, and the CPU initializes the base register 2, the offset register 3, the row buffer 4, and the column counter 5. That is, the address 33 of data 1 is input to the base register 2, and the difference between the addresses of data 1 and data 7 is input to the offset register 3 as an offset value.
In the present embodiment, the X-direction address of the memory space S is assumed to be addresses 31 to 45 for the sake of explanation.

Next, the switch SW ₁ is set to the A side, the contents of the base register 2 are transferred to the memory counter 10, and DMA transfer is started. The value of the base register 2 is taken into the memory counter 10,
The memory counter 10 counts from the added value of the base register 2 and outputs it as a desired transfer source memory address. The number of transfers in one section (one row), that is, 6 in this example, is input to the row buffer 4, and the number of rows l is input to the column counter 5.
Enter. The row counter 5 counts down the number of transfers 6, and when it reaches 0, sends an update pulse U for updating to the next row to L of the base register 2. In response to the update pulse U, the output of the adder, that is, the sum of the value of the base register 2 and the offset value of the offset register 3 is loaded into the base register 2.

As a result, the base register 2 is updated to the address of the data 7 in the next row. In this way, the contents of the memory counter 10 and the row counter 8 are updated for each transfer, and when the row counter overflows indicating 0, the value of the base register is updated by the adder 7, and the result is stored in the memory as described above. It is input to the counter 10, and the contents of the row counter 8 and the column counter 5 are also updated.

The address thus counted is sent to the image memory 13 via the multiplexer 12, one byte of data is read from the image memory 13 designated by this address, and this is written in the temporary register 14. The data stored in this temporary register 14 is
The transfer destination address is written in the image memory 13, and the transfer destination address is specified by the value of the memory counter 11. Here, as in the case of the memory counter 10, the contents obtained by adding the contents of the base register 1 and the contents of the offset register 3 by the adder 6 are input to the memory counter 11 via the base register 1, The memory counter 11 counts this value and sets it as a desired transfer destination address.

Such transfer is continued until the column counter 5 overflows, and when the overflow occurs, the DMA transfer ends. When the column counter 5 overflows, it sends a signal indicating the end of DMA transfer to the control circuit 9, and the control circuit 9 transfers a signal indicating the end of DMA transfer to a CPU (not shown). In addition, the control circuit 9 can also read or write data to be DMA-transferred by 1
A write / read memory control signal (R / W) for instructing the next write or read is sent to the multiplexer 12, the image memory 13, and the temporary register 14 each time a byte is completed.

The memory control signal (R / W) causes the multiplexer 12 to
Memory count 11 that counts the number of the write address
, And one of the outputs of the memory counter 10 for counting the number of the read address is alternately selected and input to the image memory 13. In the image memory 13, as described above, the data is sent from the specified address of the image memory 13 to the temporary register 14 in the case of reading, and the content of the temporary register 14 is transferred to the specified address of the image memory 13 in the case of writing. Processing is performed. The control of writing and reading in the image memory 13 and the switching of writing / reading data to / from the temporary register 14 are performed based on the control signal (R / W) sent from the control circuit 9.

FIG. 3 shows a timing chart of the above memory transfer. As described above, in the DMA transfer, writing and reading are alternately performed for each 1 byte. Initial values are set in the base register, offset register, row counter, and row counter via the CPU data bus A. After that, the DMA transfer is started, the address 33 is read from the base register (R), written to a desired address in the image memory (W), and so on. When R arrives at the address 38, a pulse U for updating the row is output from the point B of the row counter to switch to the next row, and at the same time, the row counter outputs a pulse O ₁ for counting down the row. In this way, when the column counter overflows, an overflow pulse O ₂ is output and the transfer ends.

〔The invention's effect〕

As described above, according to the present invention, all the rows can be continuously transferred by setting the initial value without setting and transferring the parameters of the next row for each row.
It is possible to speed up the transfer of image data.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a memory area before transfer and a memory area of a transfer destination in a memory space, FIG. 2 is a block diagram of a memory control device as one embodiment according to the present invention, and FIG. 3 is a memory transfer. 3 is a timing chart for explaining the above. 1,2 ... Base register, 3 ... Offset register,
4 ... Row buffer, 5 ... Column counter, 6,7 ... Adder, 8 ... Row counter, 9 ... Control circuit, 10, 1
1 …… Memory counter, 12 …… Multiplexer, 13 ……
Image memory, 14 ... Temporary register.

Claims (1)

[Claims] 1. A memory control device for transferring a plurality of data blocks each having a plurality of data and having non-contiguous addresses to different memory areas in a memory space, wherein a head of the plurality of data blocks is provided. A write / read base register (1, 2) whose block address is initially set as a start address, and a write / read memory counter (10, 10) which sequentially generates memory addresses with the base register address as an initial value. 11) and the number of addresses generated by the memory counter (10) for reading is counted, and a first control signal (O ₁ is generated every time the value corresponding to the number of data included in one data block is counted. ) Is output, and the number of transfer data blocks is counted in response to the first control signal (O ₁ ) and a preset value is set in advance. It corresponds to a second counter (5) that outputs a second control signal (O ₂ ) indicating the end of transfer when the count value reaches a predetermined value, and the difference between the address of each data block and the data block to be transferred next. An offset register (3) whose value is set as an offset value, and the offset value in response to the first control signal (O ₁ ) each time the address generation of a plurality of data included in one data block is completed. Add the base register value,
A write and read adder (6, 7) for setting the added value to the base register as a start address of a data block to be transferred next, and the generation of consecutive addresses in one of the data blocks. By updating the base register value by the offset register and the adder each time it is finished, and sequentially generating the address of the data included in the next data block,
A memory control device, characterized in that data of the plurality of data blocks are continuously transferred by direct memory access.