JPH0752441B2 - Vector arithmetic controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vector operation control device that performs a dimension check of vector operations.

[Conventional technology]

Conventional devices of this type include, for example, Japanese Patent Publication No. 58-35294,
Magazine “Nikkei Electronics” (April 11, 1983 issue)
Indicated by. FIG. 2 is a block diagram showing a conventional vector operation control device. In the figure, 1 is a main memory, 2 is a logic operation, addition / subtraction, sum of products operation, etc. m
, 2m is a parallel processing operator capable of parallel processing of m operations, 3 is a scalar accumulator (hereinafter referred to as SAcc), and 4 is a vector accumulator (hereinafter referred to as SA). , VAcc). Reference numerals 5a and 5b are load paths between the main memory 1 and VAcc4, and reading of vector data from the main memory 1 is performed by a pipeline operation. Reference numeral 6 is a store path between the VAcc 4 and the main memory 1, and the vector data is written into the main memory 1 by a pipeline operation. 7 is vector load path 5a, 5b and vector store path 6, SAcc3 and VAcc
4 is a transfer switching circuit for switching data transfer, and 8 is a calculation switching circuit for allocating data to be calculated and allocating a calculation result storage destination.

Figure 3 shows VAcc4 as the first-in first-out
FIG. 1 is a block diagram composed of a memory (hereinafter referred to as a FIFO memory) 17, in which 9 is a readable / writable memory body, 10 is a read-only address counter register (hereinafter referred to as RDreg) of the memory body 9, 11 Is a write-only address counter register (hereinafter referred to as WTreg) of the memory body 9.

Next, the operation of FIG. 2 will be described. The scalar and vector data stored in the main memory 1 are controlled in their transfer destinations by the load paths 5a and 5b and the transfer switching circuit 7, and are stored in SAcc3 and VAcc4. SAcc
The data stored in 3 or VAcc4 is assigned to the arithmetic processing units 2a, 2b ... 2m of the parallel processing arithmetic unit 2 by the arithmetic switching circuit 8, and these arithmetic units 2a, 2b ... 2m are used. Is calculated. The arithmetic result output from the parallel arithmetic processing unit 2 is stored in VAcc4 via the arithmetic switching circuit 8. At this time, the arithmetic switching circuit 8 is VAcc.
Specify the storage destination of 4. The vector data stored in the VAcc4 is stored in the main memory 1 via the transfer switching circuit 7 and the vector store path 6. At this time, the transfer switching circuit 7 selects VAcc4. VAcc4
Is basically composed of a FIFO memory 17 as shown in FIG. 3, and every time vector data is written in the memory body 9, the write-only WTreg 11 is counted up,
Read-only RDreg1 each time the memory body 9 is read
0 is counted up.

[Problems to be solved by the invention]

Since the conventional vector operation controller is configured as follows, when performing a vector operation check, the dimensions are counted when vector data is loaded into VAcc4, and at the end of operation for each element. Also requires special software processing such as counting the number of vector elements, the control of the transfer switching circuit 7 and the arithmetic switching circuit 8 becomes complicated, pipeline processing is not utilized, and data throughput is reduced. There was a flaw.

The present invention has been made to solve the above-mentioned problems, and does not require special software processing for dimension error, simplifies control of the switching circuit as much as possible, and does not drop data throughput. The purpose is to obtain a vector operation control device that can be checked.

[Means for solving problems]

The vector arithmetic control device according to the present invention is
The read and write address values of the FIFO memory are made readable, and these values and the value of the vector order storage register (hereinafter referred to as DIMreg) or zero value are used as input signals for comparison operation in the comparison operation unit. Then, the number of dimensions of the vector data to be calculated is checked.

[Action]

The comparison operation unit in the present invention performs a comparison operation between the read address value and write address value of the FIFO memory and the next numerical value or zero value of the vector data stored in DIMreg, and at the time of vector data loading and at the time of completion of the operation. Alternatively, it acts to notify the occurrence of a dimension error when storing the vector data in the main memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The overall basic configuration of the vector operation control device of the present invention is the same as that shown in FIG. The present invention is an improvement of VAcc of such a vector operation control device. An example of the configuration is shown in FIG. In the figure, the same reference numerals as those in FIG. 3 described above indicate the same or corresponding portions. 12 is RDre
A subtracter that subtracts the values of g10 and WTreg11, 13 is a DIMreg that stores the degree of the vector, 14 is a comparator that compares the output of subtractor 12 with the output value of selector 15, and 15 is DIMreg13 and zero. Is a selector that selects, and the comparator 14 and the selector 15 constitute a comparison means. In this embodiment, the subtractor 12, the comparator 14, and the selector 15 constitute a comparison operation unit 18.

Next, the operation will be described. The operation when performing the vector operation is the same as that of the conventional technique, and is omitted here.

Now, let the sum of vector X and vector Y be vector Z,
Consider an operation using the main memory 1. First, in the initial state, RDreg10 and WTreg11 are both reset. When loading vector X into VAcc4, the dimension N of vector X is DIM
Stored in reg13, elements of vector X are sequentially stored in VAcc4 by the operation of FIFO memory 17, WTreg11 is counted up each time, and the value of WTreg11-RDreg10 is output from subtracter 12 of comparison operation unit 18. To be done. At this time, the selector 15 of the comparison operation unit 18 selects DIMreg13, and the comparison operation unit 18 selects the comparator.
At 14, the output of the subtractor 12 is compared with the value of DIMreg 13, and the comparison operation part 18 checks the order of the vector X. Similarly, the vector Y is loaded into VAcc4 and its order is checked by the comparison operation unit 18.

Next, when the elements of the vector X and the vector Y are transferred to the parallel processing unit 2, the RDreg10 of the FIFO memory 17 is counted up this time, the parallel computing unit 2 calculates the sum, and the result is again stored in VAcc4. Store. At the end of the calculation, the comparison calculation unit 18 again compares the values of WTreg11-RDreg10 and DIMreg13 with the comparator 1
Compare with 4 and check the order of vector X and vector Y.

Finally, when the value of X + Y in VAcc4 is stored in the main memory 1, the comparator 14 of the comparison operation unit 18 outputs the output of the subtractor 12
The value of WTreg11-RDreg10 is compared with the zero selected by the selector 15 to detect a dimension error.
By the way, after the calculation result is stored in the main memory 1,
The values of WTreg11 and RDreg10 indicate the same address in the FIFO memory 17. Further, the address and the contents of the FIFO memory 17 may be indefinite, and the load / operation / store can be performed from the address of the FIFO memory 17 currently shown at the time of the next vector operation.

〔The invention's effect〕

As described above, according to the present invention, the value stored in the read-only address counter register and the write-only address counter register is compared with the value stored in the vector order storage register or the zero value at the end of the operation. Since the calculation is performed and the number of dimensions of the vector data to be calculated is checked, the dimension error of the vector data is detected without reducing the throughput without requiring complicated control or software. There is an effect such as being able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing the internal structure of a VAcc of a vector operation control device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional vector operation control device, and FIG. 3 is a conventional VAcc and transfer, It is a block diagram showing a basic configuration of a switching circuit for calculation. 4 is a vector accumulator (VAcc), 9 is a memory body, 10 is a read-only address counter register (RDreg), 11 is a write address counter register (WTreg), 12 is a subtracter, and 13 is a vector order. Storage register (DIMreg), 14 is a comparator, 15 is a selector, 17 is a far-in-fast-out memory (FIFO memory), and 18 is a comparison operation unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A main memory for storing vector data, and a vector operation stored in the main memory when the vector operation is performed. A first-in first-out memory for storing, and a first-in first-counter for incrementing the vector data or the operation result when the vector data or the operation result is stored in the first-in first-out memory. A write-only address counter register for storing the write address value of the first-out memory, and when vector data or a calculation result is read from the first-in first-out memory, only the order of the vector data or the calculation result is read. Fast toy to be counted up A read-only address counter register for storing the read-out address value of the first-out memory, a vector order storage register for storing the order of the vector data, and a write-address value stored in the write-only address counter register A subtracter for subtracting the read address value stored in the read-only address counter register from the read-only address counter register, and a vector in the first-in first-out memory.
When the data is stored, the subtraction result of the subtractor is compared with the order of the vector data stored in the vector order storage register to check the order of the vector data, and the first-in / first-out When the vector data stored in the memory is read out by the arithmetic unit, the subtraction result of the subtractor is compared with the order of the vector data stored in the vector order storage register to compare the vector data When the order is checked and the operation result stored in the first-in first-out memory is stored in the main memory, the order of the operation result is compared by comparing the subtraction result of the subtractor with a zero value. A vector arithmetic control device comprising a comparing means for checking.