JPH0752833B2 - Input/Output Circuit - Google Patents

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) The present invention relates to an input/output circuit incorporated in a CMOS type semiconductor integrated circuit, and more particularly to an input/output circuit in which a signal potential higher than the power supply potential within the input/output circuit or a signal potential lower than the reference potential within the input/output circuit is supplied from the outside to an input/output terminal where a signal is input/output.

2. Description of the Related Art In semiconductor devices such as CMOS type semiconductor integrated circuits, in order to minimize the number of terminals, one terminal is often used for both input and output of signals.

4 is a circuit diagram showing the configuration of a conventional input/output circuit provided with input/output terminals for inputting and outputting signals as described above. This input/output circuit is provided in the peripheral circuit of a CMOS type semiconductor integrated circuit. In the figure, when both internal signals S1 and S2 are set to "H" level, the output of a NAND gate 11 to which both signals S1 and S2 are input becomes "L" level, and the output of a NOR gate 12 to which an inverted signal ▲▼ of the signal S1 and the signal S2 is input also becomes "L" level, and a P-channel MOS transistor 1
3 is turned on, and the N-channel MOS transistor 14 is turned off. Therefore, at this time, a signal of "H" level is outputted from the input/output terminal 15 to the outside. Next, when the internal signal S1 is set to "L" level and S2 is set to "H" level, the NAND gate
The output of 11 becomes "H" level, the output of NOR gate 12 becomes "H" level, and P-channel MOS transistor 13 turns off.
The N-channel MOS transistor 14 is turned on. At this time, a signal of the "L" level is outputted from the input/output terminal 15 to the outside. Furthermore, when the internal signal S2 is set to the "L" level, the output of the NAND gate 11 is set to the "H" level, and the output of the NOR gate 12 is set to the "H" level.
The output of the potential detector 16 goes to the "L" level, and both the P-channel and N-channel transistors 13 and 14 are turned off. Therefore, the input/output terminal 15 goes into a high impedance state, and it becomes possible to input a signal from the outside. At this time, the external signal input via the input/output terminal 15 is detected by the potential detector 16.
The potential level is detected by the potential detector 16 and is supplied to the inside of the integrated circuit. The potential detector 16 is for detecting a signal voltage higher than the power supply voltage, and may be implemented by an inverter circuit, for example.

5 is a cross-sectional view showing the device structure of the P-channel and N-channel MOS transistors 13, 14 of the output stage in the above-mentioned conventional circuit. For example, the P-channel MOS transistor 13 is composed of a pair of P-type source/drain diffusion regions 21, 22 formed in an N-type substrate 20 and a gate structure 23 provided therebetween, while the other N-channel MOS transistor 14 is composed of a pair of N-type source/drain diffusion regions 25, 26 formed in a P well region 24 provided in the N-type substrate 20.
and a gate structure 27 provided therebetween.

By the way, when a signal is applied from the outside to the input/output terminal 15, there is no problem if a signal having the same value as the power supply voltage Vcc of the internal circuit is applied as the high potential.
When a potential higher than c is applied and detected by the potential detection circuit 16, the high potential applied to the input/output terminal 15 creates a forward bias state between the P-type drain diffusion region 22 of the transistor 13 and the N-type substrate 20.
A current flows from the drain diffusion region 22 to the N-type substrate 20, and the high potential applied to the input/output terminal 15 drops. As a result, not only does it become impossible for the potential detection circuit 16 to detect the high potential, but there is also the risk that the circuit may deteriorate and be destroyed.
That is, a negative potential is applied, and this is detected by a potential detection circuit.
When detection is performed at 16, a forward bias current is generated between the P-well region 24 and the N-type drain diffusion region 26, causing the negative low potential applied to the input/output terminal 15 to rise.

(Problem to be solved by the invention) In this way, in conventional input/output circuits, a potential detection circuit or the like is connected to the input/output terminals, and when a voltage outside the range of the power supply voltage of this circuit is applied from the outside, a current is generated at the input terminal, which in the worst case scenario leads to circuit destruction, and there is also the problem that the voltage cannot be maintained at the input/output terminals, making it impossible to detect the potential.

The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide an input/output circuit which, when a potential higher or lower than the range of the operating power supply voltage of the internal circuit is applied to the input/output terminal from the outside, can hold the potential at the input/output terminal and can stably detect the potential by a potential detection circuit.

[Configuration of the Invention] (Means for Solving the Problem) An input/output circuit of the present invention is characterized by comprising: a first MOS transistor of a first conductivity type, one end of whose current path is connected to a first potential; a second MOS transistor of a second conductivity type, one end of whose current path is connected to a second potential; a signal input/output terminal to which an output is obtained depending on the potential relationship of the other ends of the current paths of the first and second MOS transistors which are either in a conductive state and to which an external signal can be input in a high impedance state when both MOS transistors are non-conductive; and a third MOS transistor connected in series between the first and second MOS transistors, of the same conductivity type as either of the MOS transistors which commonly connects the signal input/output terminal, and which serves as a depletion load which is in a reverse bias state with respect to the potential level of the external signal.

(Function) The first and second MOS transistors are both turned off, and the signal input terminal is set to a high impedance state. At this time, if a signal potential higher or lower than the normal range of the power supply voltage is applied to the terminal, the third MOS transistor is turned off because its conductivity type is the opposite to that of the first or second MOS transistor.
One or the other of the source and drain of a transistor
One of the PN junctions is in a reverse bias state, and the signal potential applied to the above terminal is maintained as is.

EXAMPLES Hereinafter, the present invention will be described by way of examples with reference to the drawings.

1 is a circuit diagram showing the configuration of one embodiment of an input/output circuit of the present invention. The same reference numerals are used to denote parts corresponding to those in the conventional circuit. In this embodiment, as shown in the figure, the source-drain path of a depletion-type N-channel MOS transistor 1 is inserted between an input/output terminal 15 and the drain of a P-channel MOS transistor 13. An internal signal S2 is supplied to the gate of this transistor 1.

In the figure, when the internal signals S1 and S2 are both set to the "H" level, a NAND gate 1
The output of 1 is at the “L” level, and is the inverted signal of signal S1 and signal S2▲
The output of the NOR gate 12, to which ▼ is input, also goes to "L" level, turning on the P-channel MOS transistor 13 and turning off the N-channel MOS transistor 14. At this time, since the transistor 1 is of the depletion type, the "H" level of the signal S2 is supplied to the gate, and when it turns on, no voltage drop occurs between the source and drain. Therefore, at this time, an "H" level signal is output from the input/output terminal 15 to the outside.

Next, when the internal signal S1 is set to the “L” level and S2 is set to the “H” level, the output of the NAND gate 11 is set to the “H” level, and the NOR
The output of gate 12 becomes "H" level, and the P-channel MOS
Transistor 13 turns off and N-channel MOS transistor 14 turns on. Meanwhile, transistor 1, whose gate is supplied with the "H" level of S2, is also in the on state, but at this time, transistor 13 is off and transistor 14 is on, causing an "L" level signal to be output from input/output terminal 15 to the outside.

Furthermore, if the internal signal S2 is set to the “L” level,
The output of the NAND gate 11 becomes "H" level, the output of the NOR gate 12 becomes "L" level, and both the P-channel and N-channel transistors 13, 14 are turned off. Therefore, at this time, the input/output terminal 15 becomes a high impedance state, and it becomes possible to input a signal from the outside. At this time, the input/output terminal
The potential level of the external signal input via 15 is detected by a potential detection circuit 16 and is supplied to the inside of the integrated circuit.

FIG. 2 is a cross-sectional view showing the element structure of the P-channel and N-channel MOS transistors 13 and 14 of the output stage in the circuit of FIG. 1, and the depletion-type N-channel MOS transistor 1. For example, the P-channel MOS transistor 1
Reference numeral 3 denotes a pair of P-type source/drain diffusion regions 21, 22 formed in an N-type substrate 20 and a gate structure 2 provided therebetween.
The other N-channel MOS transistor 14 is composed of a pair of N-type source/drain diffusion regions 25, 26 formed in a P-well region 24 provided in an N-type substrate 20.
6 and a gate structure 27 provided therebetween.
The transistor comprises a pair of N-type source/drain diffusion regions 3, 4 formed in a P-well region 2 provided in an N-type substrate 20, and a gate structure 5 provided therebetween.

As described above, the internal signal S2 is set to the "L" level.
The operation of the circuit when an external signal is input to the input/output terminal 15 will be described with reference to FIG.
When a high level is supplied to the input/output terminal 15, if a potential higher than the power supply voltage Vcc of the internal circuit is applied as a high potential, the gate-source potential of the transistor 1 becomes negative, and the transistor 1 turns off. Moreover, the PN junction between the N-type source diffusion region 3 and the P-well region 2, and the PN junction between the N-type drain diffusion region 26 and the P-well region 24 are each in a reverse bias state, so that the input/output terminal 15 and Vcc
No leakage current occurs between input/output terminal 15 and terminal c. Therefore, a high potential is maintained at input/output terminal 15, and the high potential applied to input/output terminal 15 is stably detected by potential detection circuit 16 in FIG.

In this way, it is possible to prevent a drop in potential due to leakage current of the high potential of the input/output terminal 15. Also, when S2 is at the "H" level and the transistor 13 is turned on, the Vcc level must be transmitted to the input/output terminal 15. At this time, no voltage drop occurs due to the depletion type transistor 1, so the Vcc level can be reliably transmitted to the input/output terminal 15.

3 is a circuit diagram showing the configuration of another embodiment of the present invention. In the embodiment circuit of FIG. 1, a depression-type N-channel MOS transistor 1 is provided between the input/output terminal 15 and the drain of the transistor 13 to prevent a drop in potential when a high positive potential is applied to the input/output terminal 15. In contrast, in the embodiment circuit of this embodiment, a depression-type P-channel MOS transistor 6 is provided between the input/output terminal 15 and the drain of the transistor 14 as shown in the figure to prevent a rise in potential when a negative voltage lower than the ground voltage Vss is applied to the input/output terminal 15. As a result, the low voltage of the input/output terminal 15 is stably maintained and can be detected by the potential detection circuit 16. Furthermore, in normal operation, the transistor 14 is turned on as in the circuit of FIG. 1,
When an "L" level is output to the input/output terminal 15, since the transistor 6 is of the depletion type, no voltage drop occurs between its source and drain, and therefore the potential of the input/output terminal 15 can be set to the "L" level.

[Effects of the Invention] As described above, according to the present invention, when a potential higher or lower than the range of the operating power supply voltage of the internal circuit is applied from the outside, an input/output circuit can be provided that can hold the potential at the input/output terminal and can be stably detected by a potential detection circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the configuration according to one embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram showing a partial configuration of the circuit of FIG. 1 in a cross-sectional view, FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention, FIG. 4 is a circuit diagram showing the configuration of a conventional input/output circuit, and FIG. 5 is an equivalent circuit diagram showing a partial configuration of the circuit of FIG. 4 in a cross-sectional view. 1 ... Depletion type N-channel MOS transistor, 1
1... NAND gate, 12... NOR gate, 13... P-channel MOS transistor, 14... N-channel MOS transistor, 15... input/output terminal, 16... potential detection circuit.

───────────────────────────────────────────────────────── Continued from the front page (72) Inventor: Abe Isao 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa-ken Toshiba Microcomputer Engineering Co., Ltd. (56) References: JP 53-91560 (JP, A) JP 60-87521 (JP, A)

Claims (3)

[Claims] [Claim 1] A first MOS transistor of a first conductivity type, one end of a current path of which is connected to a first potential; a second MOS transistor of a second conductivity type, one end of a current path of which is connected to a second potential; a signal input/output terminal to which an external signal can be input in a high impedance state when both MOS transistors are non-conductive, and a third MOS transistor as a depletion load connected in series between the first and second MOS transistors, having the same conductivity type as one of the first and second MOS transistors commonly connecting the signal input/output terminal, and being in a reverse bias state with respect to the potential level of the external signal.
An input/output circuit comprising a MOS transistor and 2. An input/output circuit according to claim 1, wherein said first and second transistors are of the enhancement type, and said third transistor is of the depletion type. 3. The input/output circuit according to claim 1, further comprising a potential detection circuit connected to said signal input/output terminal for detecting a signal potential supplied to said signal input/output terminal.